JP2003018228A - Symbol synchronization circuit - Google Patents

Abstract

(57) [Problem] To reduce the number of parts, the time required for design calculation, and the time required for adjustment after assembly because an analog circuit is used in a symbol synchronization circuit of a digital receiver. To reduce costs. A baseband I obtained by orthogonally detecting a received signal.
A / D converter 1 for digitally converting phase and Q phase signals, memory 2, phase determiner 3, D / A converter 4, LPF 5, and V
A synchronous circuit including a CO 6 and a frequency divider 7,
Includes two registers that operate at twice the symbol rate, and is configured to output a phase determination value by holding a zero-crossing point and holding a sign and a change amount of a phase.

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a symbol synchronization circuit used for a demodulation circuit of a receiver in digital communication. 2. Description of the Related Art When synchronizing symbols in a digital receiver, conventionally, I-phase and Q-phase analog signals after quadrature detection are used, and the polarity change point and amplitude peak point of the received signal are synchronously reproduced. 2. Description of the Related Art A PLL (Phase Locked Loop: symbol synchronization) type symbol synchronization circuit that compares the phases of clocks in a clock and corrects and controls the phase of the clock by a feedback loop configuration according to the comparison result is widely used. However, in such a conventional symbol synchronization circuit, an LPF (low-pass filter) of an analog circuit is usually used as a loop filter, and this circuit includes an operational amplifier. , Resistors, variable resistors for circuit adjustment, capacitors, etc. are used in many parts. It takes time to calculate the circuit constants at the time of design.
There is a problem that it takes time to adjust the characteristics by a variable resistor or the like. An object of the present invention is to provide a symbol synchronization circuit which has a simplified circuit in order to solve the problems of the conventional symbol synchronization circuit and reduce the number of design steps and adjustment steps. is there. A symbol synchronization circuit according to the present invention has a baseband I based on quadrature detection of a digital reception signal.
An A / D converter for digitally converting phase and Q phase signals, a memory for storing digital I-phase and Q-phase signals output from the A / D converter at an externally designated write address, and the memory A phase determiner that reads a signal stored in the phase calculator, calculates a phase change amount from the signal, and outputs a phase determination value, and a harmonic component of a signal obtained by converting the phase determination value output from the phase determiner into an analog signal. An LPF that removes a noise component, a voltage-controlled oscillator that uses the output of the LPF as a control voltage and outputs a clock signal having a frequency corresponding to the control voltage,
The output clock of the voltage controlled oscillator is divided to generate the A / D
A symbol synchronization circuit comprising: a clock for a converter and a frequency divider for the write address of the memory, wherein the phase determiner operates at a speed twice as high as a symbol rate. A first shift register for holding a zero-cross point, a second shift register for holding a sign and a change amount of a phase, and adding a calculation result of an I phase and a Q phase. The phase information obtained as a result is output as the phase determination value. The present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration example of a symbol synchronization circuit according to the present invention. In the figure, 1 is A / D
The converter 2 is a memory, 3 is a phase determiner, 4 is a D / A converter, 5 is an LPF (low-pass filter), 6 is a VCO (voltage controlled oscillator), and 7 is a frequency divider. In FIG. 1, I-phase and Q-phase of a received signal subjected to quadrature detection are input to an A / D converter 1 and converted from an analog signal to a digital signal. A /
The operation clock of the D converter 1 is supplied from the frequency divider 2 and is set to an even multiple, for example, twice the symbol rate. The I-phase and Q-phase digital signals output from the A / D converter 1 are stored in the memory 2. An address is output from the frequency divider 7 to the memory 2 at the same timing as the operation speed of the A / D converter 1, and data is written to the address. [0008] The phase determiner 3 reads data from the memory 2 at each frame timing, performs a phase determination described later, and outputs phase information indicating a phase determination value to the D / A converter 4. The D / A converter 4 converts the digital phase determination value output from the phase determiner 3 into an analog voltage value and outputs it. The LPF 5 removes harmonic components from the analog voltage output from the D / A converter 4 and outputs the same as a control voltage for the VCO 6. The VCO 6 changes the frequency according to the control voltage, outputs a clock corresponding to the frequency, and supplies the clock to the frequency divider 7. By repeating the above processing, symbol synchronization can be achieved. The above-described phase determiner 3 will be described below. There are various methods for determining the phase. In this case, a determination based on zero crossing is used. For the determination at the zero cross, two shift registers for each of the I and Q phases operating at twice the symbol rate, a multiplier and an adder for each one, and one adder for the I and Q phases If it can be configured. FIG. 2 is a detailed block diagram (A) of the phase determiner 3 of the present invention and an eye pattern (B) for explaining the operation. In FIG. 2, 31, 32 and 31 'and 32' are shift registers (Z ^-1/2 ), 33 and 33 'are adders, 34 and 34' are multipliers, and 35 is an adder. FIG.
(A) T0 of the input / output points of the shift registers 31 and 32,
The amplitudes at T1 and T2 are calculated by the following equation 1, and "lead" and "lag" of the phase are detected depending on whether the result is positive or negative. ## EQU1 ## T1 × (T0−T2) (1) (i) If the calculation result is negative, it indicates that the phase is delayed. (Example 1) When T0 = + 1, T2 = + 1, T1 = + △, T1 · (T0−T2) = + △ · (−2) <0 (negative) (Example 2) T0 = + 1, T2 = −1 , T1 = − △, T1 · (T0−T2) = − △ · (+2) <0 (negative) (ii) If the calculation result is positive, it indicates that the phase is advanced. (Example 3) When T0 = -1, T2 = + 1, T1 = − △, T1 · (T0−T2) = − △ · (−2)> 0 (positive) (Example 4) T0 = + 1, T2 = − 1, when T1 = + △, T1 · (T0−T2) = + △ · (+2)> 0 (positive) In the circuit of FIG. 2A, T1 × (T0 −T2) is calculated and added by the adder 35 to output the averaged phase information. In the input data processing, a shift operation is performed at twice the symbol rate. Addition and multiplication processes are performed at a speed. The eye pattern shown in FIG. 2B is difficult to describe with an actual eye pattern, and therefore will be described using a BPSK (Binary Phase Shift Keying) eye pattern created only with a sin function. When the symbol synchronization is completely established, the data of the value of the grid point (cross point of the grid) of the eye pattern of FIG. 2B is input to the circuit of FIG. For example, in the case of the curve of FIG.
1, T1 = 0, T2 = −1, and the output result is 0. Similarly, in the case of a curve, T0 = -1, T1 = 0, T
2 = 1, and the output becomes 0. Then, by repeating the processing, it can be considered that the probability that the data with the curve is input is equal, and therefore, the results cancel each other out and become 0. Next, there is a shift in symbol synchronization,
It is assumed that data is input at points T0, T1, and T2 indicated by dotted lines in FIG. In the case of curve data, T0 = 0.9, T1 = -0.1, T2 = -1.
The data of 1 is input, the result is -0.2, and since it is negative, the phase is delayed and it can be seen that the shift amount is 0.2. In the case of curve data, respectively, approximately T0 = −0. 9, data of T1 = 0.1 and T2 = 1.1 are input, and the result is -0.2, which indicates that the same result as in the case of the curve data is obtained. In the case of data with a curve, the result becomes 0 by repeating the process for the same reason as described above. From the above, it can be seen that no matter what data pattern is input, a result of −0.2 can be obtained by repeating the processing. It can be seen that even in the case of the digital modulation method of 16 QAM or more, the phase can be detected by repeating the processing to some extent. This operation may be performed on all data in the memory 2 or only on a known symbol such as a preamble signal. In the case of performing this for all data in the memory 2, the number of "1" and "0" of the transmission data becomes statistically equal, so that only the phase shift amount remains after all. There is no. It is convenient for the transmitting side to perform differential encoding so that transmission data is not constant. This processing can be easily realized by software such as a DSP (Digital Signal Processor). As described in detail above, according to the present invention, since analog synchronization such as a loop filter is not required and symbol synchronization can be established, design man-hours and adjustment man-hours are reduced. Is done. Further, since it can be realized by software such as a DSP, there is an advantage that a larger circuit scale can be reduced by combining with processing such as decoding.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration example of a symbol synchronization circuit according to the present invention. FIGS. 2A and 2B are a detailed block diagram and an eye pattern diagram of a phase determiner which is a main part of the present invention. [Description of Signs] 1 A / D converter 2 Memory 3 Phase determiner 4 D / A converter 5 LPF 6 VCO 7 Dividers 31, 31 ', 32, 32' Shift registers 33, 33 ', 35 Adders 34, 34 'multiplier

   ────────────────────────────────────────────────── ─── Continuation of front page    F term (reference) 5J106 AA04 CC01 CC21 CC38 CC41                       CC52 DD33 DD35 DD36 JJ02                       KK37 KK39                 5K004 AA05 AA08 FG00 FH08 JG00                       JH05                 5K047 AA15 EE02 EE04 GG11 MM27                       MM33 MM45 MM46 MM55 MM63

Claims (1)

Claims: 1. An A / D converter for digitally converting baseband I-phase and Q-phase signals obtained by quadrature detection of a digital reception signal.
A D converter; a memory for storing digital I-phase and Q-phase signals output from the A / D converter at an externally designated write address; reading a signal stored in the memory and changing a phase from the signal A phase determiner for calculating an amount and outputting a phase determination value; and an LPF for removing harmonic components and noise components of a signal obtained by converting the phase determination value output from the phase determination value into analog.
A voltage-controlled oscillator that outputs a clock signal having a frequency corresponding to the output of the LPF as a control voltage;
A symbol synchronization circuit comprising: a clock for a converter and a frequency divider for the write address of the memory, wherein the phase determiner operates at a speed twice as high as a symbol rate. A first shift register for holding a zero-cross point, a second shift register for holding a sign and a change amount of a phase, and adding a calculation result of an I phase and a Q phase. A symbol synchronization circuit configured to output the resulting phase information as the phase determination value.