JP2003077832A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Problem] To provide a high-performance semiconductor device with high reliability and high integration on a large-sized glass substrate to be mass-produced by a simple manufacturing process. SOLUTION: A partial region (a high-concentration impurity) of a crystalline silicon film 108 crystallized by heat-treating an a-Si film 103 into which nickel 105 which is a very small catalytic element for promoting crystallization is introduced. Phosphorus 117, which is an impurity selected from Group V B, is selectively introduced into the (region) 108b, and a second heat treatment is performed, so that the phosphorus 117 of the crystalline silicon film 108 is formed.
Is moved to the high-concentration impurity region in the region 108a in which is not introduced (active region) 108a. This second heat treatment is performed so that the concentration of nickel 105 included in active region 108a and the concentration of nickel 105 included in high-concentration impurity region 108b do not at least reach a segregation state in a thermal equilibrium state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a crystalline silicon film obtained by crystallizing an amorphous silicon film as an active region and a method of manufacturing the same. . In particular, the semiconductor device of the present invention has a thin film transistor (TFT) provided on a substrate having an insulating surface and is used for an active matrix type liquid crystal display device, an organic EL display device, a contact image sensor, a three-dimensional IC, etc. It is possible to use.

[0002]

2. Description of the Related Art In recent years, large-sized high-resolution liquid crystal display devices,
In order to realize organic EL display devices, high-speed and high-resolution contact-type image sensors, three-dimensional ICs, etc., attempts have been made to form high-performance semiconductor elements on insulating substrates such as glass and insulating films. There is. A thin film silicon semiconductor is generally used for such a semiconductor element. As a thin film silicon semiconductor, an amorphous silicon semiconductor (a-S
i) and a silicon semiconductor having crystallinity.

Amorphous silicon semiconductors have a low production temperature,
It is most commonly used because it can be produced relatively easily by the vapor phase method and is excellent in mass productivity. However, since an amorphous silicon semiconductor is inferior in physical properties such as conductivity to a silicon semiconductor having crystallinity, a semiconductor device formed of a silicon semiconductor having crystallinity in order to obtain further high speed characteristics in the future. There is a strong demand for the establishment of a simple production method.

The following methods (1) and (2) are known as methods for producing a crystalline thin film silicon semiconductor.

(1) After the amorphous silicon semiconductor film is formed, the formed amorphous silicon semiconductor film is irradiated with an energy beam such as a laser beam, and the light energy causes the amorphous silicon semiconductor to be irradiated. The film is crystallized to obtain a crystalline silicon semiconductor film.

(2) After the amorphous silicon semiconductor film is formed, the amorphous silicon semiconductor film is heated and crystallized in the solid state by the heat energy to obtain a crystalline silicon semiconductor film. .

Generally, the above method (1) is used. Since this method utilizes the crystallization phenomenon in the melting and solidification process, the crystal grains have a small grain size, but there are few crystal defects in the crystal grains, and a relatively high-quality crystalline silicon film can be obtained.
However, in the crystalline silicon film produced by the above method (1), since the defect density in the grain boundary portion becomes high, the defect in this grain boundary portion acts as a large trap for the carriers, and is sufficiently used as a semiconductor device. Performance is not obtained. Taking the example of using an excimer laser that is most commonly used as a laser light source, the stability of the laser light is not sufficient, so uniform treatment should be performed over the entire semiconductor film. However, there is a problem that the characteristics vary among the formed semiconductor elements.

The method (2) is superior to the method (1) in the uniformity and stability of the semiconductor element formed in the substrate, but the high temperature condition of 600 ° C. or higher requires a long time of about 30 hours. Since the heat treatment is required for a long time, there is a problem that the treatment time becomes long and the throughput cannot be improved. Further, in the method (2), since the crystal structure is a twin crystal structure, a relatively large crystal grain of about several μm can be obtained in one crystal grain, but a large number of twin crystal defects are present in one crystal grain. Its crystallinity is
There is a problem that it is inferior to the silicon semiconductor film formed by the above method (1).

On the other hand, a method for improving the above method to obtain a high-quality crystalline silicon film has been developed. By introducing a catalytic element that promotes crystallization of an amorphous silicon film, Attention has been paid to methods for lowering the heating temperature, shortening the processing time, and improving the crystallinity. Specifically, a crystalline silicon film is obtained by introducing a trace amount of a metal element such as nickel into the surface of the amorphous silicon film and then performing heat treatment.

In the method using such a catalyst element, crystal nuclei centered on the introduced metal element are generated in the amorphous silicon film at an early stage, and thereafter, crystallization centering on the crystal nuclei is formed. It progresses rapidly.

Further, according to this method, the crystal-grown crystalline silicon film is formed by an ordinary solid-phase growth method (method (2) above).
The crystalline silicon film grown by means of has a twin structure in which many crystal defects are present, whereas a plurality of columnar crystals have a structure in which they are connected by a network, so although it is small,
The inside is almost in a single crystal state.

[0012]

The method of crystallizing an amorphous silicon film by introducing a catalytic element into the amorphous silicon film and heat-treating it can lower the heating temperature, and The heating time can be shortened,
The crystallinity of the crystalline silicon film obtained by the heat treatment is clearly superior to that of the crystalline silicon film obtained by another crystallization method.

However, the presence of a large amount of catalytic elements mainly containing these metals in the semiconductor means that the semiconductor device using the silicon film obtained by this method has reliability, electrical stability, etc. Therefore, the catalytic element such as nickel that promotes crystallization of the amorphous silicon film needs to be contained as little as possible after crystallization. Therefore, the method of reducing the amount of the catalytic element contained in the crystallized silicon film by minimizing the amount of the catalytic element introduced for the crystallization of amorphous silicon is the first method. Can be considered as a method of. However, when the amount of the catalytic element introduced into the amorphous silicon film becomes small, the crystal growth state becomes very unstable, and the crystalline silicon film produced in such an unstable state is There is a possibility that it may not be able to be used as a film forming an active region of a semiconductor device due to a large variation in properties.

On the other hand, a method of removing or reducing the catalyst element in the element region by moving (gettering) the catalyst element after introducing the catalyst element to crystallize the amorphous silicon film is described below. It is considered as the second method.

In Japanese Patent Laid-Open No. 10-270363, a part of a silicon film crystallized by a catalytic element is a region in which a Group 5 element B such as phosphorus is selectively introduced,
A method of reducing the amount of the catalyst element in the region other than the group 5 B element introduced by moving (gettering) the catalyst element to the region where the group 5 B element is introduced by performing heat treatment is known. It is disclosed. In this publication, a region in which a Group 5 B element is not introduced and a catalytic element is reduced by gettering is used as an active region of a semiconductor device.

In Japanese Patent Laid-Open No. 11-40499, a region in which a Group 5 element B for selectively gettering a catalytic element is selectively introduced is irradiated with intense light such as laser light, and the like. It is described that the gettering effect of the catalytic element is further improved by performing the heat treatment on. Further, Japanese Patent Laid-Open No. 11-54760 discloses that
By introducing the Group 3 B element in addition to the Group 5 B element,
It is described that the effect of gettering the catalytic element is enhanced.

Japanese Patent Laid-Open No. 2000-323722 discloses that
The concentration of the catalytic element contained in the impurity region of the semiconductor element is limited to 1 × 10 ¹⁷ atoms / cm ³ or more. In this publication, attention is paid to recrystallization by a catalytic element,
In order to recover the crystallinity from the damage to the crystalline silicon film by doping the impurity regions with impurities, and to activate the impurity regions efficiently and quickly, the concentration of the catalytic element is increased. Is optimized and introduced into the impurity region. However, this publication makes no mention of gettering.

By actually using the method proposed in the above publication, most of the catalytic elements can be gettered from within the element region, but there are various problems.

First, one problem is that it is necessary to add a new step in order to getter the catalytic element from within the element region. Complicated production due to the addition of new steps is not preferable in order to reduce the production cost and improve the yield rate, and in this respect, JP-A-11-40499 and JP-A-11-40499.
In Japanese Patent Laid-Open No. 54760, the impurity region (source / drain region) into which the Group 5 B element is introduced is used as a gettering sink, and the entire active region (element region) of the semiconductor device is not gettered. A method of gettering only the active region (channel region) is described.
By this method, an extra group 5 B element doping step for only gettering the catalytic element, a heat treatment step,
A mask forming step for selectively introducing the Group 5 B element can be omitted, and the gettering process can be incorporated in almost the same number of steps as a manufacturing step in which normal gettering is not performed. As a result, the problem that the number of steps increases can be solved.

However, even if this method is used, there are two other major problems.

One problem is that even if the methods of these publications are used, a sufficiently high gettering effect cannot be obtained yet, and the residual amount of the catalytic element in the active region of the semiconductor device cannot be sufficiently reduced. That is.

The inventors of the present invention actually disclosed the above-mentioned Japanese Patent Laid-Open No. 10-
When a thin film transistor (TFT) was prototyped using 270363, JP-A-11-40499, and JP-A-11-54760, a sufficiently high gettering effect could not be obtained by the methods described in these publications.
It was revealed that the residual amount of the catalytic element in the active region of the semiconductor device cannot be reduced sufficiently.

Specifically, in the TFTs prototyped according to the above publications, although there are some differences in the effects, defective TFTs having a very large leak current during the OFF operation occur with a probability of about several percent. It was Analysis of the cause of the increase in leak current in the defective TFT confirmed that silicide due to the catalytic element was present at the junction between the channel portion and the drain portion. As a result, the method according to the above publication has a high defect rate in which defective TFTs are generated, resulting in low reliability and a problem in mass productivity.

Another problem is heat treatment. In the method according to the above three publications, under heating conditions of 550 ° C. or higher,
Heat treatment is performed for several hours to several tens of hours. Such heat treatment is 100 mm x 100 mm (100 mm
When using a small glass substrate having a size of about mm mm, an expensive quartz substrate, or the like, there is no particular problem.

However, in the case of manufacturing an active matrix substrate for a liquid crystal display device in which a semiconductor element to be a semiconductor device is formed, an active matrix substrate is formed on a single mother board (glass substrate) which is a large number of active matrix substrates. Since the semiconductor element of the substrate is formed, the motherboard tends to be large in size for cost reduction. Furthermore, in order to make the device compact and lightweight, the motherboard tends to be thin, and it is very difficult to heat the large-sized and thin motherboard at high temperature for a long time.

Actually, the inventors of the present invention, as a commonly used mother board (glass substrate), 600 m
When the heat treatment was performed using a glass substrate of Corning Code 1737 having a size of mx720 mm and a thickness of 0.7 mm, under the heating condition of about 500 ° C, the heat treatment for several hours is almost the limit. It revealed that. The biggest problem caused by this heat treatment is that the weight of the glass substrate causes bending and warping. Further, as proposed in JP-A-11-40499 and JP-A-11-54760, in the method of using the impurity region (source / drain region) of the semiconductor device as a gettering sink, after pattern formation, Since heat treatment is performed, shrinkage (shrinkage) peculiar to the glass substrate occurs, and it is very difficult to perform pattern matching before and after this heat treatment step.

The present invention has been made in order to solve the above problems, and can sufficiently reduce the amount of the catalytic element contained in the element region, and can be applied to a large glass substrate to be mass-produced. An object of the present invention is to provide a semiconductor device capable of forming a crystalline silicon film that can be used as a region and a method for manufacturing the semiconductor device.

[0028]

In order to solve the above-mentioned problems, the semiconductor device of the present invention comprises:
A semiconductor device in which a crystalline silicon film is formed as an active region, wherein the active region has an active region and a high-concentration impurity region, and the active region prevents crystallization of an amorphous silicon film. The catalyst element contains a catalyst element that promotes, and the concentration of the catalyst element is configured to be low in the vicinity of the end of the active region.

In the above semiconductor device of the present invention, it is preferable that the concentration of the catalytic element contained in the active region is continuously reduced from the central portion to the end portion of the active region.

Further, the semiconductor device of the present invention is a semiconductor device in which a crystalline silicon film is formed as an active region on a substrate having an insulating property, and the active region includes an active region and a high concentration impurity. A region, the active region contains a catalytic element that promotes crystallization of the amorphous silicon film,
The catalyst element is characterized in that, in the vicinity of the end of the active region, it does not precipitate as a silicide state but is in a solid solution state.

In the semiconductor device of the present invention, the length of the region in which the catalytic element is in a solid solution state without being deposited as a silicide state in the active region is 2 μm from the end of the active region. The above is preferable.

In the semiconductor device of the present invention, the average concentration of the catalytic element contained in the high concentration impurity region is higher than the average concentration of the catalytic element contained in the active region. Is preferred.

In the above semiconductor device of the present invention, the catalyst element contained in the high-concentration impurity region is not deposited as silicide in the crystalline silicon film containing a high concentration of impurities but is in a solid solution state. Is preferred.

In the above semiconductor device of the present invention, it is preferable that a low concentration impurity region is formed between the active region and the high concentration impurity region.

In the above semiconductor device of the present invention, it is preferable that an offset region containing an impurity having a concentration approximately equal to that of the active region is formed between the active region and the high concentration impurity region.

In the above semiconductor device of the present invention, the concentration of the catalytic element contained near the end of the active region is 1/10 of the concentration of the catalytic element contained near the center of the active region.
The following is preferable.

In the above semiconductor device of the present invention, the concentration of the catalytic element contained near the end of the active region is 1 × 1.
It is preferably in the range of 0 ¹⁵ to 1 × 10 ¹⁷ atoms / cm ³ .

In the above semiconductor device of the present invention, the catalytic element is Ni, Co, Fe, Pd, Pt, Cu, Au.
It is preferably one or more selected from

In the above semiconductor device of the present invention, it is preferable that at least Ni is contained as the catalyst element.

In the above semiconductor device of the present invention, it is preferable that the high-concentration impurity region contains one or a plurality of kinds of Group 5 B elements selected from P, As, and Sb.

In the semiconductor device of the present invention, it is preferable that the high concentration impurity region contains at least P.

In the above semiconductor device of the present invention, it is preferable that the high concentration impurity region further contains a Group 3 B element in addition to the Group 5 B element.

In the semiconductor device of the present invention, it is preferable that the high-concentration impurity region contains P as an element selected from Group 5 B and B as an element selected from Group 3 B.

In the above semiconductor device of the present invention, it is preferable that the high-concentration impurity region contains one or more kinds of Ar, Kr, and Xe as an element selected from rare gas elements.

In the above semiconductor device of the present invention, it is preferable that the high concentration impurity region contains at least Ar as an element selected from the rare gases.

The method of manufacturing a semiconductor device of the present invention is
A step of forming an amorphous silicon film on a substrate having an insulating surface and introducing a catalyst element that promotes crystallization of the amorphous silicon film onto the amorphous silicon film; and the amorphous silicon film. A first heat treatment for crystallizing the amorphous silicon film to crystallize the amorphous silicon film into a crystalline silicon film, and selectively in a partial region of the crystalline silicon film. An impurity introduction step of introducing an element selected from Group 5B to form a high-concentration impurity region, and moving the catalytic element contained in the crystalline silicon film to the region into which the Group 5B element is introduced. A second heat treatment for moving the catalytic element contained in the active region of the crystalline silicon film, in which the Group 5 element B is not introduced, to the high-concentration impurity region; And the second heat treatment of the transfer step includes: The concentration and the concentration of the catalytic element contained in the high concentration impurity regions of the catalytic element is characterized in that which is performed so as not to reach the segregation state of at least a thermal equilibrium state.

The method of manufacturing a semiconductor device of the present invention is
A step of forming an amorphous silicon film on a substrate having an insulating surface, and introducing a catalyst element that promotes crystallization of the amorphous silicon film to a partial region of the amorphous silicon film; The first heat treatment for crystallizing the crystalline silicon film is performed, and from the partial region into which the catalytic element is introduced to the peripheral region, a horizontal direction parallel to the substrate surface is performed. A crystallization step of crystallizing the amorphous silicon film into a crystalline silicon film in a direction, and forming a crystalline silicon film region consisting only of the crystalline silicon film in the laterally grown region. A region forming step, an impurity introducing step of selectively introducing an element selected from Group 5B into a partial region of the crystalline silicon film to form a high concentration impurity region, and the crystalline silicon film And moving the catalytic element contained in Second heat treatment for moving the catalytic element contained in the region which does not become a Group 5 B element and becomes an active region to the high-concentration impurity region. The second heat treatment is performed so that the concentration of the catalytic element contained in the active region and the concentration of the catalytic element contained in the high-concentration impurity region do not reach at least the segregation state in the thermal equilibrium state. It is a feature.

In the method for manufacturing a semiconductor device of the present invention, before or after performing the impurity introducing step, between the high concentration impurity region and the active region,
It is preferable to further include a step of forming a region into which an element selected from Group 5 B is introduced at a lower concentration than the high concentration impurity region.

In the method of manufacturing a semiconductor device of the present invention, before or after performing the impurity introducing step, between the high concentration impurity region and the active region,
It is preferable to further include a step of forming an offset region into which a Group 5 element is not introduced.

In the method for manufacturing a semiconductor device of the present invention, the second heat treatment in the moving step is performed at a heating temperature of 400.
It is preferable that the treatment is carried out within a temperature range of 550 to 550 ° C. for a treatment time of 30 minutes to 2 hours.

In the method of manufacturing a semiconductor device according to the present invention, the second heat treatment in the moving step is performed on the substrate with the second heat treatment.
The temperature is increased at a temperature increase rate of at least 5 ° C./min or more until the temperature reaches the heat treatment temperature for performing the heat treatment of, and after the second heat treatment is completed, at least 5 ° C./min is decreased at a temperature decrease rate of the above. It is preferable to lower the temperature.

In the method of manufacturing a semiconductor device according to the present invention, the second heat treatment in the moving step is performed in the core tube having a cross-sectional shape substantially similar to the planar shape of the insulating substrate. It is preferable to use a furnace in which the substrate surface of the substrate is oriented toward the core tube and the distance between the inner peripheral side surface of the core tube and the substrate is minimized.

In the method of manufacturing a semiconductor device of the present invention, the substrate has a rectangular planar shape, and the furnace core tube of the furnace has a cross-sectional shape that is slightly larger than the planar shape of the substrate. It is preferably formed in a substantially rectangular shape.

In the method for manufacturing a semiconductor device of the present invention, the second heat treatment in the moving step is 600 to 750.
It is preferable to perform the rapid thermal annealing treatment in the temperature range of ° C for a treatment time of 1 second to 10 minutes.

In the method of manufacturing a semiconductor device according to the present invention, the rapid thermal annealing treatment is performed from a residual heat temperature of 500 ° C. or lower to an annealing temperature at which the rapid thermal annealing treatment is performed.
It is preferable to raise the temperature at a heating rate of 100 ° C./min or more.

In the method for manufacturing a semiconductor device of the present invention, the rapid thermal annealing treatment is performed by lamp irradiation using a tungsten-halogen lamp, xenon arc lamp, UV lamp or the like, or by spraying a high temperature gas on the substrate surface. It is preferable to use heat treatment.

In the method of manufacturing a semiconductor device according to the present invention, at least a part of the high concentration impurity region is formed at the time of performing the impurity introducing step or before or after the impurity introducing step.
It is preferable to further include a step of introducing an element selected from Group B.

In the method of manufacturing a semiconductor device according to the present invention, at least a part of the high-concentration impurity region is formed before or after the impurity introduction step.
It is preferable to further include a step of introducing an element selected from rare gases.

In the semiconductor device manufacturing method of the present invention, the element selected from Group 5 B is P, As, Sb.
It is preferably one or more selected from

In the method for manufacturing a semiconductor device of the present invention, it is preferable that at least P is contained as an element selected from Group 5B.

In the method for manufacturing a semiconductor device of the present invention, it is preferable to use P as an element selected from Group 5 B and B as an element selected from Group 3 B.

In the method for manufacturing a semiconductor device of the present invention, the element selected from the rare gases is Ar, Kr,
It is preferable to include one or more kinds selected from Xe.

In the method for manufacturing a semiconductor device of the present invention, it is preferable that at least Ar is contained as an element selected from the rare gases.

In the method of manufacturing a semiconductor device according to the present invention, the catalyst element is Ni, Co, Fe, Pd, Pt,
It is preferable that it is one or more kinds selected from Cu and Au.

In the method for manufacturing a semiconductor device of the present invention, it is preferable that at least Ni is contained as the catalyst element.

The semiconductor device manufacturing method of the present invention preferably further includes the step of irradiating the crystalline silicon film with laser light to enhance its crystallinity after performing the crystallization step.

[0067]

BEST MODE FOR CARRYING OUT THE INVENTION The semiconductor device and the manufacturing method thereof according to the present invention will be described in detail below.

In the semiconductor device of the present invention, the active region is
The main target is a field effect transistor composed of an active region (channel region) and a high-concentration impurity region (source / drain region). Further, in the semiconductor device of the present invention, the active region contains a catalytic element that promotes crystallization of the amorphous silicon film, and the concentration of the catalytic element in the active region is higher than that in the central portion of the active region. Even if the catalytic element in the active region is formed to be low in the vicinity of the impurity region or the catalytic element in the active region exceeds the solid solubility in the central part of the active region and is deposited as a silicide state, It is characterized in that it is in a solid solution state in which it is not precipitated as a silicide state in the vicinity of the region.

A method of manufacturing the semiconductor device of the present invention having the above characteristics will be briefly described.

The semiconductor device manufacturing method of the present invention is characterized in that the following steps (1) and (2) are sequentially performed.

(1) After introducing a catalyst element for promoting crystallization into an amorphous silicon film formed on an insulating substrate,
The amorphous silicon film is crystal-grown by performing heat treatment (first heat treatment).

(2) An element selected from Group 5 B is selectively introduced into a part of the crystalline silicon film crystallized by the first heat treatment to form a high-concentration impurity region ( After forming a region to be a source / drain region), heat treatment is performed to move a catalytic element contained in a region to be an active region (channel region) of the semiconductor device to a high-concentration impurity region (second heating). processing).

In the method of manufacturing a semiconductor device of the present invention, it is important to make the heating conditions of the second heat treatment proper, and the catalyst element concentration in the active region and the catalyst in the high concentration impurity region of the semiconductor device are important. The element concentration is performed under the condition that at least the segregation state in the thermal equilibrium state is not reached. By setting such heating conditions, the semiconductor device of the present invention having the above-described characteristics can be manufactured.

FIG. 6A shows the concentration gradient of the catalytic element from the channel region to the drain region of the semiconductor device of the present invention obtained by the above manufacturing method.
(B) shows a plan view of the semiconductor device of the present invention.

FIG. 6B shows an element region 506 formed in an island shape, where 504 is a channel region and 5 is a channel region.
Reference numerals 05 respectively indicate drain regions. FIG. 6 (A)
Then, the channel region 504 and the drain region 505
The solid line 501 represents the concentration distribution of the catalytic element in FIG.

As shown in FIG. 6A, in the semiconductor device of the present invention, the concentration of the catalytic element is kept constant in the channel region 504 and the drain region 505, respectively. In the vicinity of the boundary (joint portion) 503 with the region 505, the distribution is such that the catalytic element in the channel region 504 sharply decreases and the catalytic element in the drain region 505 sharply increases. For comparison, in FIG. 6A, a dashed line 502 shows the concentration distribution of the catalytic element of the semiconductor device in which the catalytic element existing in the channel region 504 is gettered uniformly by the conventional method (the method of the above-mentioned three publications). , The concentration of the catalyst element is constant in each of the channel region 504 and the drain region 505.

As shown in FIG. 6A, the drain region 505 is used as a gettering sink for the catalytic element in both the semiconductor device manufacturing method of the present invention and the conventional manufacturing method. In the semiconductor device, the channel region 5
In the region 04, except for the vicinity of the boundary 503 with the drain region 505, the catalytic element remains in a higher concentration than in the semiconductor device manufactured by the conventional method.
In the vicinity of the junction 503 with 05, the concentration of the catalyst element is reduced, and the concentration of the remaining catalyst element is lower than that of the semiconductor device by the conventional method.

Further, as shown in FIG. 6B, when the concentration of the catalytic element exceeds a certain value, the silicide 50
7 is deposited, but in the region at a distance L from the joint portion 503 where the concentration of the catalyst element is a certain value or less, the catalyst element is in a solid solution state and silicide is not deposited.

In order to make it easier to understand the effects obtained by the above-described structure of the present invention, the possible causes of the leakage current during the OFF operation will be described first.

9A to 9C show N-type TFs, respectively.
FIG. 7B is a band diagram of a region extending from the channel region to the drain region in T, where (a) is a gate voltage Vg> 0,
(B) is the gate voltage Vg = 0, (c) is the gate voltage Vg
<0 is shown. In FIG. 9, the solid line 801 represents the conduction band, the solid line 802 represents the valence band, and the solid line 803 represents the film level.

When the gate voltage Vg> 0, FIG.
A band diagram as shown in (a) is obtained, a positive bias is applied from the channel region to the drain region, the TFT is turned on, and a current flows from the channel region to the drain region. When the gate voltage Vg = 0, FIG.
As shown in (b), the Fermi level 803 has the same level in the channel region and the drain region.

When the gate voltage Vg <0 shown in FIG. 9C, the TFT is turned off, and the conduction band 801 and the valence band 802 are formed in the junction between the channel region and the drain region. A large wavy state is formed at the junction between the channel region and the drain region. In this state,
When a trap level as indicated by a point 804 in FIG. 9C exists at the junction, carriers 805 existing in the channel region pass through the trap level 804 and an arrow 80.
Position 806 on the conduction band 801 through the path indicated by 7.
Will be moved to. This carrier movement is understood as a kind of tunnel current phenomenon via the trap level 804.

Although the junction between the channel region and the drain region has been described with reference to FIGS. 9A to 9C, since the actual TFT element is driven by AC, the junction between the channel region and the source region is performed. The same phenomenon will appear in the part.

The current drive capability of the TFT, that is, the ON characteristic is
It is mainly determined by the crystallinity of the silicon film in its channel region. On the other hand, the leak current generated during the OFF operation of the TFT is caused by the trap level existing near the junction between the channel region and the source region or the drain region as described above.

The crystalline silicon film crystallized by introducing the catalytic element has good crystallinity, and therefore high ON characteristics can be obtained. However, in the process of crystallization by the catalytic element, the catalytic element is deposited in the crystalline silicon film in the silicide state. When the inventors of the present application disassembled and analyzed a TFT having an abnormally high off current, it was actually confirmed that a catalyst element silicide was generated in the vicinity of the junction between the drain region and the channel region. As a result, in the TFT using the crystalline silicon film crystallized by introducing the catalytic element in the active region, the reason why an abnormally high off current frequently occurs is that the junction between the channel region of the TFT and the source region or the drain region is caused. It is considered that this is because the silicide of the contact element is present in the portion and this silicide becomes the trap level shown by 804 in FIG. 9C and causes the tunnel ring.

Therefore, if the concentration of the catalyst element at the junction between the channel region and the source / drain region in the TFT is lowered, the increase in leak current due to the catalyst element can be suppressed. From the opposite point of view, even if the concentration of the catalytic element is increased to some extent in the central portion of the channel region that is apart from the junction to some extent, it does not pose a problem in the characteristics of the semiconductor device. Also, the catalyst element itself does not cause the trap level to occur, and the problem is that it is precipitated as a silicide state.
In the vicinity of the junction in the channel region, it is possible to suppress an increase in the leak current due to the catalyst element if it is in a solid solution state without being deposited as a silicide state. Further, so-called hot electron characteristic deterioration and the like occur near the drain end (junction with the channel region) where electric field concentration occurs. In the semiconductor device of the present invention, the catalytic element is reduced at the junction between the channel region and the source / drain regions, so that a highly reliable semiconductor device can be obtained without deterioration of characteristics or the like.

Further, in the semiconductor device of the present invention, the catalytic element is reduced in the vicinity of the source / drain regions in the channel region, and the catalytic element present in the central part of the channel region and its precipitates are present. How much (silicide) influences the characteristics of the semiconductor device becomes a problem, but according to the experiments conducted by the present inventors, the catalytic element is fixed in the central part of the channel region which is apart from the junction to some extent. Even if it exceeds the solubility and precipitates in a silicide state, it does not cause any particular problem in the characteristics of the semiconductor device, and all the problems that the residual catalytic element gives to the characteristics of the semiconductor device are the drain junction where electric field concentration occurs. It is clear that they are aggregated in the vicinity of.

In addition, the above-mentioned three publications (JP-A-10-2
70363, JP-A-11-40499, and JP-A-11-54760), the catalytic element is uniformly gettered in all regions of the active region or the channel region of the TFT, and the concentration difference of the catalytic element in the region is reduced. There is no state. In order to realize such a state, heat treatment at high temperature for a long time is required.
However, if high-temperature heat treatment is performed for a long time, thermal changes such as bending, warping, and shrinking occur, so apply it to large motherboards (glass substrates) used for active matrix substrates for liquid crystal displays. I can't.

On the other hand, in the semiconductor device of the present invention,
The concentration of the catalytic element at the junction, which is a problem in the characteristics of the semiconductor device, is reduced, preventing an increase in leak current regardless of whether the catalytic element in the other region of the channel region is sufficiently gettered. From the viewpoint of the process, the heat treatment for gettering can be performed at a low temperature and in a short time, and the present invention can be applied to a large-scale mother board for mass production.

Further, the active (channel) in the present invention
If the concentration of the catalytic element in the region is continuously reduced from the central portion of the active region to the boundary with the high-concentration impurity region, the effect of preventing an increase in off current can be obtained. It can be higher.

Further, the distance L from the bonding portion 503 at which the concentration of the catalytic element shown in FIG.
It is preferably m or more. When the distance L is 2 μm or less, the silicide precipitate 507 becomes a leak path due to the influence of the electric field concentration generated at the junction 503. When the silicide precipitate 507 is present at a distance of 2 μm or more from the junction 503, the electric field at the junction 503 is hardly affected by the practical use voltage level, and the off characteristics of the semiconductor device are reduced. There is no adverse effect on reliability.

The semiconductor device of the present invention has the above structure. In order to easily manufacture this structure, it is effective to use the high-concentration impurity regions (source / drain regions) as gettering sinks of the catalytic element.

Further, in the semiconductor device of the present invention, the average value of the concentration of the catalyst element existing in the high concentration impurity region is
It is desirable that the concentration is higher than the average value of the concentration of the catalytic element in the active region. In such a state, the catalytic element has a concentration distribution / concentration gradient as shown in FIG. 6A from the central portion of the channel region to the junction portion, and the above-mentioned semiconductor device of the present invention has the above-mentioned structure. The effect can be enhanced.

Further, it is important that the catalytic element existing in the high-concentration impurity region is in solid solution in the silicon film and is not deposited as silicide. Even in the high-concentration impurity region, electric field concentration similarly occurs in the vicinity of the junction with the channel region, and if a deposit of the catalytic element in the silicide state is present in this portion, the off characteristics and reliability of the semiconductor device may be deteriorated. It will have an adverse effect. Therefore, in the semiconductor device of the present invention, it is effective to make the high-concentration impurity region act as a gettering sink, and in this respect also, the concentration of the catalyst element in this region is higher than that in the channel region. desirable. Then, in this high-concentration impurity region, in particular, in the vicinity of the joining portion joined to the channel region, the catalyst element needs to be in a solid solution and not be deposited as silicide. In order to achieve such a state, it is necessary to select the impurity species, which will be described later.

In order to further enhance the effect of reducing the abnormal increase in off-current and the deterioration of reliability of the semiconductor device of the present invention, the active region (channel region) and the high-concentration impurity region (source / drain region) are formed. It is desirable that a low-concentration impurity region (LDD region) or a region having an impurity concentration equivalent to that of the active region (offset region) is provided between the first and second regions. If such a region is provided,
The electric field concentration at the junction between the channel region and the source / drain region is relaxed. As a result, in addition to the effect of reducing the concentration of the catalyst element near the junction of the channel region and the reduction of silicide precipitates, a synergistic effect of dispersing the electric field concentrated in that region occurs, which causes an abnormal increase in off current. It is possible to reduce the reliability and further improve the reliability (hot electron resistance).

In the active region of the semiconductor device of the present invention
The concentration distribution of the catalytic element should be in the vicinity of the high-concentration impurity region.
The catalytic element concentration at
Therefore, it is desirable that it is 1/10 or less. Active territory
The concentration ratio of catalytic elements in the region is as high as 1/10 or less
If it is higher, the rate of occurrence of abnormalities in the off characteristics of semiconductor devices
It has been found that the effect of the present invention
ing. Furthermore, the semiconductor device of the present invention is provided in the active region.
In the vicinity of the joint that joins the high-concentration impurity region
Elemental concentration is 1 × 10¹⁶~ 1 x 10¹⁷atoms / cm
³It is desirable to be within the range. Catalyst source in this area
Elemental concentration is 1 × 10¹⁷atoms / cm ³Became
In the case of
No adverse electrical effects are seen. Residual catalyst source
It goes without saying that the more the element concentration is reduced, the better
However, the method of crystallization using a catalytic element is used.
As long as the minimum is 1 × 10¹⁶atoms / cm³Degree of catalyst
It is unavoidable that elements remain, and it is reduced below this concentration.
You cannot do it. Therefore, the semiconductor device of the present invention
Even at least 1 × 10¹⁶atoms / cm³
The above-mentioned concentration of the catalytic element near the junction in the channel region
It remains.

FIG. 7A is a graph showing a characteristic curve of a P-type TFT actually manufactured by the method for manufacturing a semiconductor device of the present invention, and FIG. 7B is a graph showing a uniform concentration over the entire element region. 2 shows characteristic curves of a P-type TFT manufactured by a conventional method containing a catalytic element. In both characteristic curves, the gate voltage Vg when a voltage of 1 V and 4 V is applied between the source and drain is taken as the horizontal axis. , Drain current I
Vg-I of TFT, where d is the logarithmic scale and is shown on the vertical axis
It is a d characteristic curve. In FIGS. 7A and 7B, the characteristics for 24 points are displayed in an overlapping manner.

In the characteristic curve shown in FIG. 7A, the off current Id diverges when the gate voltage Vg is applied in the positive direction (direction in which the P-type TFT is turned off), and each TF is diverged.
Different off currents appear for each T, and TFTs having a significantly high off current are generated.

On the other hand, in the characteristic curve shown in FIG. 7B, it can be seen that the off current is low in all TFTs and is well aligned.

There is no difference between the two curves in the drain current Id when the gate voltage Vg is applied so that the direction of the electric field from the source region to the drain region is in the positive direction, and the on characteristics are different in both semiconductor devices. You can see that there is no.

Only the amount of the catalytic element contained in the active region used in both semiconductor devices is almost equal, and the concentration distribution of the catalytic element in the active region is different, which is a noticeable difference in the above characteristics. There is. From these results, the TFT manufactured by the method for manufacturing a semiconductor device of the present invention is very effective for reducing the leak current, and the semiconductor device of the present invention reduces the leak current and is a high-performance TFT. Can be realized.

Further, Japanese Patent Application Laid-Open No. 10-270363,
JP-A-11-40499, JP-A-11-5476
In each of the methods described in Japanese Patent Publication No. 0, the treatment for reducing the catalytic element in the active region is also performed, and in this case, the off current which is remarkable as shown in the characteristic curve of FIG. However, even with this method, a defective TFT with a large leak current during the OFF operation appears with a probability of about several percent.

In the semiconductor device of the present invention, up to now 100
Although TFTs exceeding 0 points are measured, no defective TFTs in which the off-state current has abnormally increased have been confirmed so far. In addition, an active matrix type liquid crystal display device equipped with a TFT manufactured by the method for manufacturing a semiconductor device of the present invention has a linear display which frequently occurs in an active matrix liquid crystal display device equipped with a TFT manufactured by a conventional method. There were no unevenness (due to the sampling TFT in the driver section) and pixel defects due to the leak current of the off operation, and the display quality could be greatly improved, and the non-defective rate could be dramatically increased.

In the method for manufacturing a semiconductor device of the present invention, the Group 5 B element introduced for gettering the catalytic element serves as an impurity introduced for forming the impurity region (source / drain region). Doubles as Therefore, the impurity region formed by introducing impurities is
It can also be used as a gettering sink for gettering the catalytic element. Therefore, it is necessary to perform a step of forming a dedicated mask for selectively forming a region for gettering the catalytic element. Absent. Further, the step of heating and activating the impurities introduced into the impurity region and the second heating step for gettering the catalytic element can be performed at the same time, and the number of steps can be significantly reduced. The manufacturing process can be simplified. As a result, according to the method of manufacturing a semiconductor device of the present invention, the productivity can be greatly improved, and the cost can be reduced and the yield rate can be improved.

Further, in the method of manufacturing a semiconductor device of the present invention, the second heat treatment for gettering the catalytic element is performed by the catalytic element concentration in the channel region and the catalytic element concentration in the source / drain regions of the semiconductor device. Is performed under heating conditions such that at least does not reach the segregated state, and the heat treatment temperature in the second heat treatment for gettering the catalytic element is higher than the heat treatment temperature for gettering the normal catalytic element. The temperature is lowered and the heating time is shortened. Specifically, in the above three publications, 550
It requires heat treatment for several hours to several tens of hours at a high temperature of ℃ or higher, and cannot be used for such large-scale inexpensive glass substrates under such heat treatment conditions and cannot be mass-produced. In the present invention, since heat treatment at a low temperature for a short time is sufficient, there is no bending or warping due to the weight of the glass substrate, and shrinkage (shrinkage) peculiar to the glass substrate can be suppressed within the usable range. A glass substrate generally used in a mass production process of active matrix substrates for liquid crystal displays, for example, Corning Code 1737 non-annealed glass substrate having an outer diameter of 600 mm × 720 mm or more and a thickness of 0.5 to 0.7 mm. It can be used and can be applied to a large glass substrate that is a target for mass production.

Further, in the method for manufacturing a semiconductor device of the present invention, the catalytic element is selectively introduced into a part of the amorphous silicon film formed on the insulating substrate, and then the first heat treatment is performed. By this, the amorphous silicon film is crystallized in the lateral direction (direction parallel to the substrate) from the region in which the catalytic element is selectively introduced to the peripheral region thereof, and the crystalline silicon in the laterally crystal-grown region is grown. A method of utilizing the film as a channel region of a semiconductor device is effective. An element selected from Group 5B is selectively introduced into the active region thus formed, and the high-concentration impurity region (source.
After forming the drain region), the second heat treatment is performed so that the concentration of the catalytic element in the active region of the semiconductor device and the concentration of the catalytic element in the high-concentration impurity region do not reach at least the segregated state in the thermal equilibrium state. Then, the catalytic element in the crystalline silicon film to be the active region (channel region) of the semiconductor device is gettered to the high concentration impurity region.

In this case, the crystalline silicon film obtained by the crystal growth in the lateral direction is crystal-grown by the crystal nuclei randomly generated in the amorphous silicon film by introducing the catalytic element over the entire surface. Since the crystallinity is superior to that of the obtained crystalline silicon film, it is possible to obtain a high-performance semiconductor device having higher current drivability. Furthermore, the crystalline silicon film obtained by crystal growth in such a lateral direction is
Since the residual amount of the catalytic element is smaller than that of the crystalline silicon film obtained by introducing the catalytic element over the entire surface, gettering of the catalytic element by the second heat treatment becomes easier.

In the method of manufacturing a semiconductor device of the present invention, in the step of forming a high concentration impurity region (source / drain region) by introducing an element selected from Group 5B,
Alternatively, before and after that, a region in which an element selected from Group B element B is introduced at a lower concentration than the high concentration impurity region is formed between the high concentration impurity region and the active region, or In the step of introducing an element selected from Group 5 B elements into the high-concentration impurity region, it is desirable to form a region into which the element selected from Group 5 B is not introduced. By doing so, the low-concentration impurity region (LDD region) or the impurity having the same concentration as that of the active region is introduced between the active region (channel region) and the high-concentration impurity region (source / drain region). A region (offset region) is formed, and in addition to the effect of reducing the concentration of the catalyst element near the channel end and the reduction of silicide precipitates, a synergistic effect can be obtained by dispersing the electric field concentrated in this region, It is possible to further reduce the abnormal increase in off current and improve reliability (hot electron resistance).

In the method of manufacturing a semiconductor device of the present invention,
The second heat treatment for gettering the catalytic element is
It is necessary to set the heating conditions such that the catalytic element concentration in the active region of the semiconductor device and the catalytic element concentration in the high-concentration impurity region do not reach at least the segregated state in the thermal equilibrium state. As such a heating condition, it is desirable to perform the treatment within a temperature range of 400 to 520 ° C. for a treatment time of 30 minutes to 2 hours. Under such heating conditions, the outer shape has a size of 600 mm × 720 mm or more, which is generally used in the process of mass-producing active matrix substrates for liquid crystal displays, and has a size of 0.5 to 0.7 mm. The use of Corning Code 1737 non-annealed glass substrate with thickness does not pose a problem. However, if the treatment temperature is lowered to 400 ° C. or lower, the gettering of the catalytic element cannot be sufficiently achieved even if the heat treatment time is extended, or the treatment time becomes extremely long, which deteriorates the throughput. As a result, the number of production units / footprint increases, which causes problems as a mass production process.

In the second heat treatment in the method for manufacturing a semiconductor device of the present invention, both the temperature rising rate and the temperature lowering rate for reaching the predetermined temperature for gettering the catalytic element are at least 5 ° C./min. It is desirable to raise and lower the temperature at a rate above. If the rate of temperature increase / decrease is slower than this rate, unintended extra heat treatment is added, and the catalytic element in the active region of the semiconductor device and the catalytic element in the high-concentration impurity region are at least in a segregated state in thermal equilibrium. It becomes impossible to obtain the heating condition of not reaching.
In addition, when the temperature raising / lowering rate is slow, thermal damage to the glass substrate increases. According to an experiment conducted by the present inventor, when the second heat treatment is performed at a temperature rising rate and a temperature lowering rate of 5 ° C./minute or more, the above problems do not occur and the semiconductor having the features of the present invention is obtained. It has been shown that a device is obtained.

In the method of manufacturing a semiconductor device of the present invention,
When performing the second heat treatment, as an apparatus for that,
It has a core tube formed in a cross-sectional shape similar to a substrate having a planar shape (rectangular shape), and the substrate placed in this core tube has a substrate surface oriented in the core direction. It is desirable to use a furnace in which the space between the core tube and the substrate is minimized.

FIGS. 8 (a) to 8 (c) each schematically explain a furnace used for the second heat treatment in the method for manufacturing a semiconductor device of the present invention.

In this furnace, as shown in FIG. 8 (a), a quartz board in which a plurality of substrates 701 are placed in a horizontal state in such a manner that they are vertically arranged at equal intervals (indicated by 705 in the figure). A quartz board 702, which has a plurality of substrates 701 and has a substrate 702, is fitted from below into a hollow quartz tube (core tube) 703 that houses the quartz board 702. Substrate 701 in the state
Heat treatment is performed.

The cross-sectional shape of the quartz tube 703 is shown in FIG.
As shown in (b), it has a rectangular shape which is slightly larger than the outer shape of the substrate 701 and is substantially similar to the substrate 701.

Conventionally, a silicon wafer such as an IC has been formed in a circular shape, and a furnace for heating such a wafer has a cross-sectional shape of a quartz tube 703 'as shown in FIG. 8 (d). Is formed to have a circular shape. On the other hand, since the glass substrate, which is a mother board such as an active matrix substrate for liquid crystal display, is all formed in a rectangular shape, when the rectangular substrate is set in the quartz tube 703 'of the conventional furnace, the glass substrate shown in FIG.
As shown in (d), the substrate 701 and the quartz tube 70.
A large gap 706 will be formed between this and 3 '. When such a gap 706 is generated, the temperature distribution generated in the substrate 701 during the temperature increase / decrease during the heat treatment is large, and for example, the temperature between the peripheral portion and the central portion of the substrate 701 exceeds 200 ° C. A distribution is generated, and due to the influence of the temperature distribution, the substrate may be warped or cracked frequently.

The present inventor has made a gap 706 formed between the side peripheral portion of the quartz tube 703 and the side portion of the substrate 701.
It has been found that the substrate pitch 705 between the substrates 701 is a large parameter for the temperature distribution in the substrate 701 during temperature increase / decrease in the heating process by the furnace.
Further, it was also found that by appropriately setting such parameters, the temperature rising / falling speed of the substrate 701 can be improved as compared with the conventional apparatus, and the processing capacity can be improved.

The gas flow of the atmospheric gas supplied from the upper part of the quartz tube 703 and circulated in the furnace is:
As shown by arrows 709 to 711 in FIG. 8C, the flow flows along the surface of each substrate 701 through the gap 706 formed between the inner peripheral portion of the quartz tube 703 and the side edge of the substrate 701. The gas supply amount of the atmospheric gas supplied onto the substrate 701 by the flow indicated by the arrow 711 is proportional to the flow velocity of the atmospheric gas 710 flowing through the gap 706 between the substrate 701 and the quartz tube 703, and It is proportional to the square of the substrate pitch 705 between the substrates. Therefore, in order to increase the flow rate of the atmospheric gas indicated by the arrow 710,
It is not enough to increase the gas supply amount of the supply gas,
By minimizing the gap 706 between the quartz tube 703 and the substrate 701, the flow rate of the atmospheric gas can be improved.

In the furnace used in the method for manufacturing a semiconductor device of the present invention, a furnace core tube (quartz tube) 70 having a substantially similar rectangular cross section that is slightly larger than the substrate 701 is used.
3 is used, the gap 706 between the substrate 701 and the quartz tube 703 can be minimized over the entire circumference of the outer edge of the substrate 701. As a result, in addition to optimizing the substrate pitch 705 formed between the substrates 701, the temperature distribution generated in the substrates 701 during temperature rising / falling can be kept substantially constant, and each side has a size of about 1 meter. Even if the second heat treatment is performed using a large-sized glass substrate having a thickness, it is possible to perform a stable treatment without cracking, warping, or the like. Even if the conventional circular quartz tube 703 'shown in FIG. 8 (d) is used, there is a portion where the gap between the substrate 701 and the quartz tube 703 is wide, so that such a thing can be realized. I can't.

In the furnace shown in FIG. 8A, the quartz board 702 on which a plurality of substrates 701 are set is located at the home position 707 below the quartz tube 703 before starting the heat treatment. Position 7
At 07, some preheating of about 200 ° C. is performed. Then, when heat treatment is performed, the quartz tube 703 is fitted into the quartz tube 703 at the same time as the quartz tube 703 is fitted in the quartz tube 703 in the direction indicated by the arrow 704.
When the temperature inside is raised and the entire quartz board 702 is fitted into the quartz tube 703 and enters a predetermined position (annealing zone) 708 for performing the heat treatment, the heat treatment is started. On the contrary, the temperature reduction after the heat treatment is performed by moving the quartz board 702 to the home position 707 which is the preheating zone.

In addition, the furnace shown in FIG.
Quartz tube 703 having a multi-chamber structure that accommodates a plurality of quartz boards 702 connected in a cluster.
And a plurality of quartz boards 702 having a large number of substrates 701 set therein can be heat-treated simultaneously, a heating device having an extremely high processing capacity can be obtained.

As the second heat treatment in the method for manufacturing a semiconductor device of the present invention, in addition to the heat treatment using the furnace, the heating temperature is set to 600 ° C. to 750 ° C. by rapid thermal annealing treatment. Temperature range is 1 second to 1
The treatment may be performed for a treatment time of 0 minutes. further,
As for the heating conditions, it is desirable to raise the temperature from a residual heat temperature of 500 ° C. or less to a high-speed annealing temperature at a temperature rising rate of more than 100 ° C./min. Under such heating conditions, it is possible to realize a state in which the catalytic element in the active region of the semiconductor device and the catalytic element in the high-concentration impurity region do not reach at least the segregation state in the thermal equilibrium state. Further, if the heat treatment is performed under such rapid thermal annealing conditions, the treatment temperature rises, but since the heat treatment can be performed instantaneously, the bending and warpage of the glass substrate can be suppressed. According to the experiments by the present inventors, under such rapid thermal annealing conditions, 600 mm × which is generally used in the mass production process of active matrix substrates for liquid crystal display.
It has an outer shape of 720 mm or more, and is 0.5 to 0.7.
Corning Code 173 with size having a thickness of mm
It has been shown that a 7 non-annealed glass substrate can be used. Further, the processing time per substrate can be greatly shortened, which is suitable for a mass production process. However, since the processing temperature becomes high, the annealing time needs to be accurately controlled. If the temperature raising / lowering rate is slow,
Unintended extra heat treatment is added, and it becomes impossible to prevent the catalytic element in the active region of the semiconductor device and the catalytic element in the high-concentration impurity region from reaching at least a segregated state in a thermal equilibrium state. In addition, thermal damage to the glass substrate increases.

As a concrete apparatus for performing such rapid thermal annealing, a tungsten-halogen lamp,
It is preferable to perform lamp irradiation using a xenon arc lamp, a UV lamp, or the like, or heat treatment by blowing high-temperature gas onto the substrate surface. In such lamp irradiation of a tungsten-halogen lamp or the like, since the Si layer is mainly used as an absorption layer and the substrate can be instantly heated and cooled, it can be suitably used in the method for manufacturing a semiconductor device of the present invention.

When performing rapid thermal annealing by blowing a high temperature gas onto the substrate surface, a resistive heating furnace is also used to form a thermal gradient in this furnace to reduce the heat capacity of the substrate. Insert one board at a time into the furnace. At that time, the temperature increase rate can be controlled by the insertion speed of the substrate and the blowing of the high temperature gas onto the surface of the substrate. In this case,
The entire substrate can be uniformly and instantaneously heated, and the temperature rising rate and the temperature lowering rate can be accurately controlled.

As a mechanism for gettering the catalytic element into the high-concentration impurity region, by increasing the solid solubility with respect to the catalytic element in the high-concentration impurity region to be higher than that in the active region, A method of gettering the catalytic element in the concentration impurity region (first gettering action), and a local segregation site for trapping the catalytic element in the high concentration impurity region are formed, and the catalytic element is attached to the segregation site. There is a method of moving and trapping (second gettering action).

When an element selected from Group 5B is introduced into the crystalline silicon film, the solid solubility of the catalytic element in the region can be dramatically increased, and the difference in solid solubility causes the catalytic element to move. That is, since the first gettering action is performed, the Group 5 B element is introduced into the high-concentration impurity region in the method for manufacturing a semiconductor device of the present invention. Specifically, elements selected from Group 5 B include P and A.
At least one element selected from s and Sb can be used. With one or more elements selected from these, the catalytic element contained in the active region can be efficiently moved, and a sufficient gettering effect can be obtained. It has been found that P has the highest gettering effect among these elements.

Further, 3 is added to the high-concentration impurity regions (source / drain regions) into which the element selected from Group 5 B is introduced.
When an element selected from Group B is further introduced, a Group 3 B element is contained in addition to the element selected from Group 5 B, and a larger gettering effect can be obtained. It has been found that such a state changes the mechanism of gettering the catalytic element in the high-concentration region, and when only the Group 5 B element is contained, the difference in solid solubility between the two regions becomes large. Utilizing this, the catalyst element is moved by the first gettering action of diffusing and moving the catalyst element, but by adding the Group 3 B element, the catalyst element easily precipitates in the high-concentration impurity region serving as the gettering sink. Then, a second gettering action for moving and trapping the catalytic element to the defect or segregation site is added. Thus, in addition to the elements selected from Group 5 B, 3
By introducing the element selected from the group B, the catalytic element can be moved by both the first and second gettering actions, and the junction with the source / drain region is formed in the channel region of the semiconductor device. In the vicinity of, the concentration of the catalytic element can be reduced more greatly. Specifically, the highest gettering effect is obtained when P (phosphorus) is used as the element selected from Group 5 B and B (boron) is used as the element selected from Group 3 B. You can

Furthermore, as another method for enhancing the effect of gettering the catalytic element, a step of introducing a rare gas element selected from Ar, Kr, and Xe into the high-concentration impurity region serving as the gettering sink may be added. It is very effective. If these rare gas elements are present in the high-concentration impurity region that serves as a gettering sink, a large interstitial strain is generated in the high-concentration impurity region, and the second gettering that moves and traps the catalytic element to the defect or segregation site. The action works powerfully. Therefore, by introducing the rare gas element, both of the two mechanisms for gettering the catalytic element work, and the effects can be obtained by these two mechanisms. In the channel region of the semiconductor device, the source / drain region of the source / drain region can be obtained. The catalytic element can be reduced more effectively in the vicinity of the joint. If the element selected from the rare gases is one or more selected from Ar, Kr, and Xe, the gettering efficiency can be improved, but among these rare gas elements,
The greatest effect can be obtained when Ar is used.

Further, in the method of manufacturing a semiconductor device of the present invention, the kind of the catalytic element that promotes crystallization of the amorphous silicon film is one of Ni, Co, Fe, Pd, Cu, Au, etc., Alternatively, a plurality of kinds of elements selected from these can be used, and if these elements are used as catalyst elements, crystallization can be promoted in a small amount.

These catalytic elements do not act alone,
Since the crystal growth is promoted by combining with the silicon atoms of the amorphous silicon film and silicidation, it is preferable that the lattice constant of the silicide compound of the catalytic element be close to the lattice constant of single crystal silicon. Ni is a two-atom Si
And NiSi ₂ which is a silicide compound are formed. Ni
Si ₂ has a fluorite type crystal structure, and the crystal structure is
It is very similar to the diamond structure of single crystal silicon. Moreover, NiSi ₂ has a lattice constant of 5.406Å, which is the closest to the lattice constant of silicon, with respect to crystalline silicon of diamond structure having a lattice constant of 5.430Å. Therefore, NiSi ₂ is the best template for crystallization of the amorphous silicon film, and the crystallization of the amorphous silicon film is most promoted. Therefore, Ni is suitable as the catalyst element.

Further, in the method for manufacturing a semiconductor device of the present invention, the crystallinity of the crystalline silicon film crystallized by introducing the catalytic element is further improved, and the performance of the semiconductor device, particularly the current driving ability is further improved. As a way to improve
For the crystalline silicon film crystallized by the catalytic element,
Furthermore, it is effective to add a step of performing heat treatment in a high-temperature oxidizing atmosphere or a step of irradiating laser light. When heat treatment is performed at a high temperature (800 ° C. to 1100 ° C.) in an oxidizing atmosphere, supersaturated Si atoms generated by the oxidation action are supplied to the silicon film, and the supersaturated Si atoms are
Crystal defects (particularly dangling bonds: dangling bonds) in the silicon film are introduced into the silicon film, whereby the defects can be eliminated. However, this method cannot use an inexpensive glass substrate. From this point of view, in the method for manufacturing a semiconductor device of the present invention, it is more effective to increase the crystallinity by using the method of irradiating laser light.

When a crystalline silicon film obtained by the method for manufacturing a semiconductor device of the present invention is irradiated with a laser beam, crystal grains are changed due to a difference in melting point between the crystalline silicon film and the amorphous silicon film. The boundaries and minute residual amorphous silicon regions (uncrystallized regions) are intensively crystallized. In the crystalline silicon film formed by the usual solid phase growth method,
Since the crystal structure is in a twin state, the inside of the crystal remains as twin defects even after irradiation with strong light. On the contrary,
The crystalline silicon film crystallized by introducing the catalytic element is formed of columnar crystals, and the inside is in a single crystal state. A crystalline silicon film of high quality close to that of the above is obtained, and its effectiveness is very high from the viewpoint of crystallinity.

Further, in this case, since the silicon film which originally has crystallinity is irradiated with laser, unlike the method in which the amorphous silicon film is directly irradiated with laser to be crystallized,
The effects of variations in laser irradiation are greatly reduced,
The problem of crystal uniformity does not occur.

However, in the method for manufacturing a semiconductor device of the present invention, it is desirable that the step of irradiating the laser beam as described above be performed before the second heat treatment for gettering the catalytic element. When a crystalline silicon film obtained by solid-phase crystallization by introducing a catalytic element is irradiated with laser light, the existing form of the catalytic element changes.

Specifically, the remaining catalyst element is aggregated / re-aggregated as a silicide by the irradiation of laser light. The gettering step of moving the catalytic element from the active region and stopping the movement of the catalytic element in the state where the concentration gradient is formed at the junction as in the present invention is performed by the crystalline state of the crystalline silicon film in the region to be the channel region. It is desirable to perform after complete completion, and ideal gettering can be performed. When the process for promoting crystallinity is performed after the gettering of the catalyst element, the catalyst element remaining after the gettering and solid-dissolved is re-aggregated to silicidize, which adversely affects the semiconductor device. There is a fear.

Specific examples using the method for manufacturing a semiconductor device of the present invention will be described below. (Embodiment 1) In Embodiment 1, a process of manufacturing an N-type TFT used for a driver circuit, a pixel portion or a thin film integrated circuit of an active matrix type liquid crystal display device on a glass substrate will be described.

FIGS. 1A to 1G are cross-sectional views for explaining each step of the method for manufacturing the N-channel TFT of the first embodiment.

In order to manufacture the N-channel type TFT of the first embodiment, first, as shown in FIG. 1A, in order to prevent impurities from diffusing from the glass substrate 101 in a subsequent step, the glass substrate 101 101, for example, a plasma CV
By the D method, the base film 102 made of silicon oxide and having a film thickness of about 300 to 500 nm is formed. Next, an intrinsic (I-type) amorphous silicon film (a-S) having a thickness of 20 to 80 nm, for example 40 nm, is formed by using the plasma CVD method.
i film) 103 is formed. In the first embodiment, the glass substrate 101 has a size of 320 mm × 400 mm and a thickness of 0.7 m.
m non-annealed glass substrate of Code 1737 manufactured by Corning Co., Ltd., a parallel plate type plasma CVD apparatus is used as the plasma CVD apparatus, and the heating temperature is 30
At 0 ° C., SiH ₄ gas and H ₂ gas were used as the material gas. Further, the range of 10~200mW / cm ³ power density of the RF power supplied to the CVD electrode, for example, as 80 mW / cm ^3, was deposited a-Si film 103.

Next, a small amount of nickel 105 is added on the surface of the a-Si film 103. The addition of nickel 105
The solution in which nickel is dissolved is held on the a-Si film 103, and the nickel solution is uniformly spread on the substrate 101 by a spinner and dried. In the first embodiment,
Using nickel acetate as a solute and water as a solvent, the nickel concentration in the solution was adjusted to 10 ppm. The concentration of the added nickel was determined by total reflection X-ray fluorescence analysis (TR
XRF) method, 5 × 10 ¹² atoms
It was about / cm ³ .

Next, the a-Si film 103 to which a small amount of nickel 105 has been added is heat-treated in an inert gas atmosphere, for example, a nitrogen gas atmosphere. In this heat treatment, hydrogen contained in the a-Si film 103 is first desorbed during the temperature rise, and then, as a high temperature condition,
The a-Si film 103 was crystallized. Specifically, the first
As the heat treatment of the step, the annealing treatment is performed at a temperature condition of 450 ° C. to 520 ° C. for a treatment time of 1 to 2 hours, and the heat treatment of the second step is 520 ° C.
Annealing treatment is performed at a temperature of 570 ° C. for a treatment time of 2 to 8 hours. In Example 1, after heat treatment was performed at a temperature of 500 ° C. for 1 hour, 550 ° C.
The heat treatment was carried out for 4 hours under the temperature conditions of. In this heat treatment, nickel added to the surface of the a-Si film 103 diffuses into the a-Si film 103, and silicidation occurs.
The Si film 103 is crystallized to become a crystalline silicon film 103 ′.

Then, as shown in FIG. 1B, the crystalline silicon film 103 'is recrystallized by irradiating the crystalline silicon film 103' with a laser beam 107 to improve its crystallinity. Let As the pulsed laser beam at this time, a XeCl excimer laser (wavelength 308 nm, pulse width 40 nsec) was used in Example 1. The irradiation conditions of the laser beam 107 are as follows:
It is heated to 0 to 450 ° C., for example 400 ° C., and the energy density is 250 to 450 mJ / cm ³ , for example 350 mJ.
The irradiation conditions were such that irradiation was performed at / cm ³ . The beam size of the laser beam 107 is 150 on the surface of the substrate 101.
A beam spot was formed into an elongated shape of mm × 1 mm, and the beam spot was sequentially scanned in a direction perpendicular to the longitudinal direction with a step width of 0.05 mm. As a result, the laser beam 107 is irradiated 20 times in total on any one point of the crystalline silicon film 103 ′. By repeatedly irradiating the laser beam 107 as described above, the crystalline silicon film 103 ′ obtained by the solid-phase crystallization is reduced in crystal defects due to the melting and solidification process by the irradiation of the laser beam 107, and thus the higher crystallinity It becomes a crystalline silicon film 103 'of high quality.

After that, unnecessary portions of the crystalline silicon film 103 'are removed by etching to separate the elements. Through these steps, as shown in FIG. 1C, in a later step, an island-shaped crystalline silicon film 108 to be the active region (source / drain region, channel region) of the TFT is formed.

Next, as shown in FIG. 1D, 20 to 20 are formed so as to cover the crystalline silicon film 108 to be the active region.
A silicon oxide film 109 which is a gate insulating film is formed to have a film thickness of 150 nm, for example, 100 nm. In the first embodiment, TEOS is used to form the silicon oxide film 109.
(Tetra Ethoxy Ortho Silic
ate) as a raw material and the substrate temperature is set to 150 in the presence of oxygen.
To 600 ° C., preferably 300 to 450 ° C., and decomposed and deposited by the RF plasma CVD method. Alternatively, the substrate temperature is 350 to 600 ° C., preferably 400 to 550, in the presence of ozone gas using TEOS as a raw material.
The silicon oxide film 109 may be formed by heating at 0 ° C. and using a low pressure CVD method or a normal pressure CVD method.

Subsequently, a refractory metal is deposited by a sputtering method and is patterned to form a gate electrode 110 located at a predetermined portion on the crystalline silicon film 108. As the refractory metal, tantalum (Ta), tungsten (W), molybdenum (M
It is desirable to use o) or the like. In the present Example 1, Ta containing a slight amount of nitrogen was used to form a film having a film thickness of 300 to 600 nm, for example, 450 nm.

Subsequently, using the ion doping method, the crystalline silicon film 108 is formed using the gate electrode 110 as a mask.
Of a low concentration of impurities (phosphorus) 112 in the region that becomes the active region of
Inject. In the first embodiment, phosphine (PH ₃ ) is used as a doping gas for doping phosphorus, and the accelerating voltage is 60 to 90 as the doping condition.
kV, for example, 80 kV, and the dose amount is 1 × 10 ¹² to
It was set to 1 × 10 ¹⁴ cm ⁻² .

By this step, the region 108a of the crystalline silicon film 108 which is masked by the gate electrode 110 and to which phosphorus is not implanted becomes the channel region 113 of the TFT through the subsequent steps.

Next, as shown in FIG. 1E, a photoresist that covers the gate electrode 110 once is provided on the gate electrode 110 to form a doping mask 116.
After that, using an ion doping method, an impurity (phosphorus) 117 is implanted into a region to be an active region using the doping mask 116 as a mask. In this case, a phosphine (P
H ₃ ) and the accelerating voltage is 6 as the doping condition.
0 to 90 kV, for example, 80 kV, and the dose amount is 1 ×
10 ¹⁵ to 8 × 10 ¹⁵ cm ^-2 , for example, 2 × 10 ¹⁵ cm ^-2
And By this step, the region 108b of the crystalline silicon film 108, which is not masked by the doping mask 116 and into which the impurity (phosphorus) 117 is implanted at a high concentration, becomes the source / drain region 118 of the TFT in a later step. In addition, the region 10 where the high-concentration impurity (phosphorus) 117 is not introduced by being masked by the doping mask 116
8c is formed between the region 08a and the region 108c. This region 108c becomes the LDD region 114 in which phosphorus is introduced at a low concentration through the subsequent steps.

After removing the doping mask 116, heat treatment is performed in an inert gas atmosphere, for example, a nitrogen gas atmosphere. In Example 1, in a nitrogen gas atmosphere, the temperature condition of 400 ° C. to 550 ° C. was 30 minutes to 2 minutes.
Processed over time. This heating condition is 450-
More preferably, the temperature range of 52 ° C. is 30 minutes to 2 hours. In this heat treatment, it is desirable that the rate of temperature rise up to the temperature of heat treatment and the rate of temperature decrease from the temperature of heat treatment be at least 5 ° C / minute or more. In Example 1, the heating temperature was set to 500 ° C., and the heat treatment was performed for 1 hour, and
The temperature is raised from the preheated state of about ℃ to the heating temperature of 500 ℃ in 30 minutes (temperature rising rate of 10 ℃ / min), and after the heat treatment is completed, the heating temperature (500 ℃) to 200 ℃
Until the temperature dropped in 30 minutes.

By performing this heat treatment step, the crystalline silicon film 1 is formed by the phosphorus 117 which is highly doped in the region 108b of the crystalline silicon film 108.
The nickel remaining in the area 108a of FIG.
As indicated by the arrow 122 in (f), the area 108a is moved to the areas 108b and 108c. Further, in this heat treatment, the nickel concentration in the region 108a and the nickel concentration in the regions 108b and 108c doped with phosphorus at a high concentration that serves as a gettering sink do not reach the segregated state of thermal equilibrium, so that the region 108a And area 108
Nickel is intensively gettered in the region near the joint with c. As a result, a nickel concentration gradient as shown in FIG. 6 is obtained in the region 108a that becomes the channel region and the region 108c that becomes the LDD region. In this heat treatment, the region 1 after the heat treatment
The concentration of nickel remaining in the vicinity of the junction with the region 108c at 08a is 1 × 10 ¹⁶ atoms / cm ³
It is reduced to the extent. Further, the nickel remaining in the region 108a exists in the state of a solid solution as interstitial nickel, not in the silicide state, in the vicinity of the junction with the region 108c.

In Example 1, a non-annealed glass substrate of Corning Code 1737 having a size of 320 mm × 400 mm and a thickness of 0.7 mm is used as the glass substrate 101, but the heat treatment causes warping, bending, cracking, etc. Did not occur. Furthermore, in the experiments of the present inventors, even when using a large-sized glass substrate of another meter size, the above heat treatment does not cause warpage, bending, cracking, or the like, and it can be used. I'm confirming.

Further, in the present Example 1, in the core tube having a cross-sectional shape substantially similar to the plane shape of the substrate 101 as shown in FIG. The heat treatment was performed using a furnace in which the space between and was minimized. The core tube is the glass substrate size 320 × 400 m used in the first embodiment.
It is formed in a rectangular cross-sectional shape slightly larger than m, and the size of the space inside the core tube for housing the substrate is 400 mm × 480 mm. The number of substrates to be charged in the core tube is 20 in order to perform one heat treatment at the same time. Then, nitrogen gas is supplied from above the core tube, diffused between the substrates, and each substrate can be uniformly heated in the plane. In FIG. 8, a quartz tube (core tube) 703 is
It is heated to 520 ° C. by a heater provided outside the quartz tube 703, and at a home position 707 below the quartz tube 703, it is preheated to 200 ° C. Then, as indicated by an arrow 704, the quartz board 702 charged with the substrate 701 enters the quartz tube 703 and is heated, and the entire quartz board 702 is completely inserted into the annealing zone 708. The heat treatment of the substrate 701 is started. For cooling, the quartz board 702 is used in the home position 7 which is a residual heat zone.
It is done by taking it down to 07. By using such a device, it is possible to increase the temperature rising / falling speed, and it is possible to keep the temperature distribution in the substrate during temperature rising / falling substantially constant, and even for a large glass substrate of a meter size, It is possible to realize stable processing without cracking or warping.

Also, by this heat treatment, nickel which is a catalytic element is gettered. In addition to this action, impurities (phosphorus) implanted by ion implantation are activated and deteriorated by the introduction of impurities. The improved crystallinity is improved. The source / drain region 118 thus obtained has a sheet resistance value of 0.8 to 1.5 kΩ.
/ □, and the sheet resistance value of the LDD region 114 is 30
Was about 100 kΩ. In addition, the gate insulating film 109 is fired at the same time as the above heat treatment, so that the gate insulating film 109 itself has bulk characteristics and crystalline silicon film 1.
08, it is possible to improve the interface characteristics at the interface between the gate insulating film 108 and the gate insulating film 109.

Next, as shown in FIG.
A silicon oxide film or a silicon nitride film having a thickness of about m is formed to form the interlayer insulating film 124. When a silicon oxide film is formed as the interlayer insulating film 124, by using TEOS as a raw material, a plasma CVD method in the presence of oxygen, or a low pressure CVD method or a normal pressure CVD method in the presence of ozone, A good silicon oxide film having excellent coverage is formed. Further, when a silicon nitride film is formed as the interlayer insulating film 124, it is formed by using a plasma CVD method using SiH ₄ and NH ₃ as source gases. This silicon nitride film can supply hydrogen atoms to the interface between the crystalline silicon film 108 serving as the active region and the gate insulating film 109, and reduce dangling bonds that deteriorate the TFT characteristics.

Next, contact holes reaching these regions are formed in the portions of the interlayer insulating film 124 corresponding to the source / drain regions 118 on the crystalline silicon film 108. The source / drain region 11 of the TFT is formed in the contact hole formed in the interlayer insulating film 124 by a metal material, for example, a two-layer film of titanium nitride and aluminum.
The electrodes / wirings 125 electrically connected to 8 are formed.
The titanium nitride film is provided as a barrier film for preventing aluminum from diffusing into the semiconductor layer. Also,
When this TFT is used for pixel switching of a liquid crystal display device, a pixel electrode made of a transparent electrode film such as ITO may be used for the drain electrode. Further, in this case, the other source electrode constitutes a source bus line, an electric signal such as a video signal is supplied through the source bus line, and based on the gate signal of the gate bus line, The necessary charge is written in the pixel electrode.

Finally, in a steam atmosphere of 1 atm, 350
Annealing is performed for 1 hour under the temperature condition of ° C to complete the desired TFT 126. In addition, this TFT 12
A protective film such as a silicon nitride film may be further provided to protect 6.

As described above, the TFT manufactured through the steps described in the first embodiment has a field effect mobility of 250 cm ² / V.
s, threshold voltage is about 1.5 V, and very high performance is obtained, and TFT obtained by the conventional manufacturing method.
There was no abnormal increase in the leak current during the off operation of the TFT, which was frequently observed in 1., and a very low value of 1 pA or less per unit W was stably shown. This value has no difference even when compared with the conventional TFT manufactured without using the catalyst element, and the manufacturing yield could be greatly improved.

Further, the TFT of the present Example 1 showed almost no deterioration in characteristics even after repeated measurement, durability test by bias and temperature stress, and it was very much compared with the TFT manufactured by the conventional method. Highly reliable.

When the active matrix substrate for liquid crystal display using the TFT of Example 1 was actually evaluated for lighting,
It was possible to obtain a liquid crystal panel of high display quality with a high contrast ratio, in which display unevenness was significantly smaller than that using a TFT manufactured by a conventional method, pixel defects due to TFT leakage were extremely small.

The TFT of the first embodiment described above is used.
Although the manufacturing process has been described for the pixel electrode of the active matrix substrate, the TFT of the first embodiment can be applied to a thin film integrated circuit or the like. In that case, a contact hole is also formed on the gate electrode. It may be formed and a required wiring may be provided. (Embodiment 2) In Embodiment 2, as in Embodiment 1 above, an N-type TF used for a driver circuit, a pixel portion, and a thin film integrated circuit of an active matrix type liquid crystal display device.
A process of producing T on the glass substrate will be described.

2 (a) to 2 (h) are cross-sectional views for explaining each step of the method for manufacturing the N-channel TFT of the second embodiment.

To manufacture the N-channel TFT of the second embodiment, first, as shown in FIG. 2A, in order to prevent impurities from diffusing from the glass substrate 201 in a subsequent step, the glass substrate 201 201, for example, a plasma CV
By the D method, the base film 202 made of a silicon oxide film having a film thickness of about 300 to 500 nm is formed. next,
An intrinsic (I-type) amorphous silicon film (a-S) having a thickness of 20 to 80 nm, for example 40 nm, is formed by using the plasma CVD method.
i film) 203 is formed.

Next, a small amount of nickel 205 is added on the surface of the a-Si film 203. The addition of nickel 205 is
The solution in which nickel was dissolved was held on the a-Si film 203, and the nickel solution was uniformly spread on the substrate 201 by a spinner and dried. In Example 2, nickel acetate was used as the solute and water was used as the solvent, and the nickel concentration in the solution was adjusted to 10 ppm. The nickel concentration of the added nickel on the a-Si substrate 201 was about 5 × 10 ¹² atoms / cm ^{3 as} measured by the total reflection fluorescent X-ray analysis (TRXRF) method.

Next, the a-Si film 203 to which a small amount of nickel 205 has been added is heat-treated in an inert gas atmosphere, for example, a nitrogen gas atmosphere. This heat treatment is 52
As a temperature condition of 0 to 570 ° C., for example, 550 ° C., 2
The treatment time was -8 hours, for example, 4 hours.
By this annealing treatment, the a-Si film 203 is crystallized into a crystalline silicon film 203 '.

Next, as shown in FIG. 2B, the crystalline silicon film 203 'is recrystallized by irradiating the crystalline silicon film 203' with laser light 207 to improve its crystallinity. Let In this example 2, a XeCl excimer laser (wavelength 308 nm, pulse width 40 nsec) was used as the pulsed laser light at this time. The irradiation conditions of the laser light 207 are as follows:
0 to 450 ° C., for example, heated to 400 ° C., and energy density is 250 to 450 mJ / cm ³ , for example, 350 m
The irradiation conditions were irradiation at J / cm ³ . By repeatedly irradiating with the laser light 207 as described above, the crystalline silicon film 203 ′ obtained by the solid-phase crystallization is reduced in crystal defects due to the melting and solidification process by the irradiation of the laser light 207, and thus the crystallinity is higher. It becomes a high quality crystalline silicon film.

After that, unnecessary portions of the crystalline silicon film 203 'are removed by etching to separate the elements. After this step, as shown in FIG. 2C, an island-shaped crystalline silicon film 208 to be an active region (source / drain region. Channel region) of the TFT is formed by a subsequent process.

Next, as shown in FIG. 2D, 20 to 20 are formed so as to cover the crystalline silicon film 208 to be the active region.
A silicon oxide film 209 which is a gate insulating film is formed to a thickness of 150 nm, for example, 100 nm. In the second embodiment, TEOS is used to form the silicon oxide film 209.
(Tetra Ethoxy Ortho Silic
ate) as a raw material and the substrate temperature is set to 150 in the presence of oxygen.
To 600 ° C., preferably 300 to 450 ° C., and decomposed and deposited by the RF plasma CVD method. After the formation of the silicon oxide film 209, the bulk characteristics of the silicon oxide film 209 itself and the crystalline silicon film 208 and the silicon oxide film 20 are formed.
In order to improve the interfacial characteristics with the No. 9 film, annealing was performed in an inert gas atmosphere at a temperature condition of 500 to 600 ° C. for 1 to 4 hours.

Then, by a sputtering method, 40
Aluminum is formed into a film thickness of 0 to 800 nm, for example, 600 nm, and is patterned to form a gate electrode 210 located at a predetermined portion on the crystalline silicon film 208. Then, the surface of the gate electrode 210 made of aluminum is anodized to form an oxide layer 211 on the surface of the gate electrode 210. When the TFT manufactured in Example 2 is used as the pixel TFT of the active matrix substrate, the gate electrode 210 is formed on the same plane at the same time when the gate bus line is formed. Become. The anodic oxidation of the gate electrode 210 is obtained by first applying a constant current in an ethylene glycol solution containing tartaric acid in an amount of 1 to 5%, then increasing the voltage to 220 V, and maintaining the state for 1 hour. The thickness of the obtained oxide layer 211 was 300 nm. Note that since the oxide layer 211 has a thickness to form an offset gate electrode in a later ion doping step, the length of the offset gate electrode can be determined by the above anodic oxidation structure.

Subsequently, phosphorus 217 as an impurity is implanted by using the ion doping method. In this case, the gate electrode 210 formed on the silicon oxide film 209 and the oxide layer 211 around the gate electrode 210 serve as a mask, and the gate electrode 210
And, phosphorus 217 is not implanted into the crystalline silicon film 208 corresponding to the lower part of the oxide layer 211. In the second embodiment, phosphine (PH ₃ ) is used as the doping gas for doping phosphorus 217, and the accelerating voltage is 60 to 90 kV, for example, as the doping condition.
80 kV, dose amount 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm
^-2 , for example, 2 × 10 ¹⁵ cm ^-2 .

By this step, the crystalline silicon film 20 masked by the gate electrode 210 and into which the phosphorus 211 is not implanted.
The region 208a of No. 8 becomes a channel region of the TFT through the subsequent steps. In addition, the gate electrode 210 and the oxide layer 21
The region 208b of the crystalline silicon film 208 into which the phosphorus 217 is implanted without being masked to 1 is formed on the TFT through a subsequent process.
Source / drain regions. In addition, the oxide layer 211
In the region 208c corresponding to the lower part, the oxide layer 211 serves as a mask and phosphorus 217 is not implanted, and the state is similar to that of the region 208a, but the region 208c does not overlap with the gate electrode 210, and this region 208c is It becomes an offset region through the subsequent steps.

After forming each region in which impurities are introduced to each concentration, in this state, argon is introduced by the ion doping method. The doping gas is 1
An accelerating voltage of, for example, 80 k
V and the dose amount is 1 × 10 ¹⁵ to 1 × 10 ¹⁶ c
m ⁻² , for example, 2 × 10 ¹⁵ cm ⁻² . After this step is performed, the region 208b becomes a region containing argon in addition to phosphorus 217. The concentration of argon in the region 208b in this state is 2 × 10 ^{20 to} 5 × 10 ²⁰ atoms.
It was about / cm ³ .

Then, heat treatment is performed in an inert gas atmosphere, for example, in a nitrogen gas atmosphere. In Example 2, in a nitrogen gas atmosphere, a temperature condition of 400 to 550 ° C. was set to 3
The treatment was carried out for 0 minutes to 2 hours. It is more preferable that the heating condition is a temperature range of 450 to 520 ° C. and a heating time of 30 minutes to 2 hours. In this heat treatment, it is desirable that the rate of temperature rise up to the temperature of heat treatment and the rate of temperature decrease from the temperature of heat treatment be at least 5 ° C / minute or more. In Example 2, in reality, the heating temperature was set to 500 ° C., the heat treatment was performed for 1 hour, and the substrate was preheated to about 200 ° C. and then heated to 500 ° C. in 30 minutes (increase). Temperature rate 1
(0 ° C./min), and after the heat treatment was completed, the temperature was lowered from this heating temperature (500 ° C.) to 200 ° C. in 30 minutes.

By carrying out this heat treatment step, the nickel remaining in the region 208a due to the phosphorus and the argon which are highly doped in the region 208b are changed as shown by an arrow 222 in FIG. 2 (f). In area 2
Moved from 08a to region 208b. In addition, in this heat treatment, since the nickel concentration in the region 208a and the nickel concentration in the region 208b in which phosphorus and argon are introduced at a high concentration serving as a gettering sink do not reach the segregated state of thermal equilibrium, Regions 208b and 208
Nickel is intensively gettered in the region near the joint with c. As a result, a nickel concentration gradient as shown in FIG. 5 is obtained in the regions 208a and 208b208c.

Further, in the second embodiment, as compared with the first embodiment, the argon doped in the region 208b causes a larger interstitial strain, and the strain becomes a segregation trap for nickel. It is possible to getter nickel. As a result, the concentration of residual nickel in the vicinity of the junction with the region 208b in the region 208a after the heat treatment was reduced to 1 × 10 ¹⁶ atoms / cm ³ or less, which is less than or equal to the measurement lower limit in the measurement by SIMS. Further, the nickel remaining in the region 208a exists not as a silicide state but as a solid solution as interstitial nickel.

In Example 2, a non-annealed glass substrate of Corning Code 1737 having a size of 320 mm × 400 mm and a thickness of 0.7 mm is used as the glass substrate 201. However, the above heat treatment causes warpage, bending, cracking, or the like. Did not occur. Furthermore, in the experiments of the present inventors, even when using a large-sized glass substrate of another meter size, the above heat treatment does not cause warpage, bending, cracking, or the like, and it can be used. I'm confirming.

In the second embodiment, the substrate 101 as shown in FIG. 8 is placed in a core tube having a cross-sectional shape similar to that of the plane shape, and the substrate surface is oriented in the core direction to make the core tube and the substrate Heat treatment was performed using a furnace in which the space between and was placed first.

Next, as shown in FIG. 2 (g), laser light 223 is irradiated to anneal to activate the ion-implanted impurities, and at the same time, the crystallinity is deteriorated by the above-mentioned impurity introduction step. Improve the crystallinity of the damaged part. In the case of doping with argon, the crystallinity is largely destroyed, and it is difficult to sufficiently recover and activate the doping damage only by the heat treatment at 550 ° C. described above. Annealing process is added.

At this time, Xe is used as the laser beam 223.
Cl excimer laser (wavelength 308 nm, pulse width 40
nsec) and energy density of 150 to 400 m
J / cm ² , preferably 200 to 250 mJ / cm ² . The sheet resistance of the region 208b in which phosphorus, which is an N-type impurity, formed in this manner is 200 to 5
It was 00Ω / □.

Next, as shown in FIG.
A silicon oxide film or a silicon nitride film having a thickness of about m is formed to be an interlayer insulating film 224. When a silicon oxide film is formed as the interlayer insulating film 224, by using TEOS as a raw material, a plasma CVD method in the presence of oxygen, or a low pressure CVD method or a normal pressure CVD method in the presence of ozone is used. A good silicon oxide film having excellent coverage is formed. When a silicon nitride film is formed as the interlayer insulating film 224, it is formed by using a plasma CVD method using SiH ₄ and NH ₃ as source gases. This silicon nitride film can supply hydrogen atoms to the interface between the crystalline silicon film 208 and the silicon oxide film 209, which are active regions, and reduce dangling bonds that deteriorate the TFT characteristics.

Next, contact holes reaching these regions are formed in the interlayer insulating film 224 in the portions corresponding to the source / drain regions 208b on the crystalline silicon film 208 of the TFT. In the contact hole formed in the interlayer insulating film 224, an electrode / electrode electrically connected to the source / drain region 218 of the TFT is formed by a two-layer film of a metal material such as titanium nitride and aluminum.
The wiring 225 is formed. The titanium nitride film is provided as a barrier film for preventing aluminum from diffusing into the semiconductor layer. When this TFT is used for pixel switching of a liquid crystal display device, a pixel electrode made of a transparent electrode film such as ITO may be used as the drain electrode.

Finally, in a water vapor atmosphere of 1 atm, 350
Annealing is performed for 1 hour under the temperature condition of ° C to complete the desired TFT 226. In addition, this TFT 22
A protective film such as a silicon nitride film may be further provided to protect 6.

As described above, the TFT manufactured through the steps described in the second embodiment has a field effect mobility of about 250 cm ² / Vs and a threshold voltage of about 1.5 V, which is very similar to that of the first embodiment. High performance, no abnormal increase in leakage current during off operation of TFT, which was frequently observed in the TFT obtained by the conventional manufacturing method, and 1 pA per unit W
The following and stable low values were shown. This value has no difference as compared with the conventional TFT manufactured without using the catalytic element, and the manufacturing yield could be greatly improved. (Third Embodiment) In the third embodiment, a peripheral drive circuit of an active matrix type liquid crystal display device, an N-channel type TFT and a P-channel type TFT which form a general thin film integrated gap.
A process of forming a circuit having a CMOS structure in which and are complementary to each other on a glass substrate will be described.

FIG. 3 is a plan view showing the outline of the manufacturing process of the circuit structure of the third embodiment. 4 (a) to 4 (I) are explanatory diagrams for each step of a method for manufacturing a CMOS structure in which the N-channel TFT and the P-channel TFT of the third embodiment are configured in a complementary manner. FIG. 7 is a cross-sectional view taken along the line -A ′.

In manufacturing the CMOS structure of the third embodiment, first, as shown in FIG. 4A, the glass substrate 301 is used to prevent impurities from diffusing from the glass substrate 301 in the subsequent steps. A base film 302 made of a silicon oxide film and having a film thickness of about 300 to 500 nm is formed thereon by, for example, a sputtering method. Next, an intrinsic (I-type) amorphous silicon film (a-S) having a thickness of 20 to 80 nm, for example 40 nm, is formed by using the plasma CVD method.
i film) 303 is formed.

Next, after depositing an insulating thin film such as a silicon oxide film or a silicon nitride film over the entire surface of the a-Si film 303, patterning is performed to form a mask 304. In the third embodiment, T is formed on the a-Si film 302.
EOS (Tetra Ethoxy Ortho Si
A silicon oxide film was deposited by decomposing and depositing by using an RF plasma CVD method in the presence of oxygen. The thickness of the mask 304 is 100 to 400.
The thickness is preferably in the range of nm, and in the third embodiment, the thickness of this silicon oxide film is set to 150 nm. Through holes 304a are formed in the mask 304,
As shown in FIG. 4A, the through hole 304a forms a region 303a in which the a-Si film 303 is exposed in a slit shape, and the portion other than the region 303a is exposed by the mask 304 in the a-Si film 303. Not in a state. In this case, the line width L of each region 303a exposed by the a-Si film 303 is preferably formed in the range of 2 to 15 μm. In the third embodiment, the line width L of the region 303a is set to 10 μm. did.

Next, the a-Si film 303 and the mask 304.
Add a small amount of nickel on the surface of the. As the nickel to be added, a target of pure nickel (99.0% or more) was used and was added by the DC sputtering method. Specifically, the sputtering treatment was performed with the DC power set to an extremely low power of about 50 W and the substrate 301 rotated at a high speed of 2000 mm / min. In the third embodiment, as the gas used in this sputtering process,
Argon is used and the gas pressure during sputtering is 10P.
As a high pressure condition of a or higher, nickel was sputtered under an extremely low concentration condition.

The sputtered nickel 305 is
In FIG. 4A, a thin film is shown for the sake of clarity, but in reality, it is formed in a state of about a monoatomic layer or less. Actually, the DC power is 60
When sputtering was performed under the conditions of W and an argon gas pressure of 18 Pa, a-exposed in the region 303a was observed.
The concentration of nickel on the Si film 303 is 6 × 10 ¹³ ato.
It was about ms / cm ² (measured by TRIXRF).

Next, as shown in FIG. 4B, in a state where nickel is sputtered to a low concentration, under an inert gas atmosphere, for example, a nitrogen gas atmosphere, the heating temperature is set to 530 to 530.
Anneal for 11 hours at 600 ° C., for example 580 ° C.

At this time, in the region 303a where nickel is added on the surface of the a-Si film 303, a small amount of nickel 3
Crystallization occurs with 05 as a nucleus, and a region 303a in which crystal is grown with nickel as a nucleus is formed. Then, subsequently, in the peripheral area of the area 303a, as shown in FIG.
In each of (b), as indicated by an arrow 306, a crystal grows laterally (parallel to the substrate) from the region 303a, and the region 303b where the crystal grows in the lateral direction corresponds to a lower portion of the mask 304. Is formed.

Areas other than the areas 303a and 303b are
Although it will remain as an amorphous silicon film region as it is,
In practice, the region 303b of the crystalline silicon film that has grown in the lateral direction as described above collides with the region 303b of the crystalline silicon film that has grown from the adjacent other region 303a, and the crystal growth ends, and the crystal growth ends in both directions. A crystal boundary 303e is formed in a portion where the crystal-grown crystalline silicon films collide with each other.

In this case, the niches existing on the mask 304 are
Kell is masked by the mask 304,
Is not introduced into the a-Si film 303 and is introduced into the region 303a.
Of the a-Si film 303 only by the deposited nickel
Progresses. Crystalline crystals that have grown in such a lateral direction
The nickel concentration in the silicon film region 303b is 5 × 10 5. ¹⁷
~ 1 x 10¹⁸atoms / cm³The degree is
Nickel in the region 303a in which crystal growth has been added
The concentration is 1 × 10¹⁹atoms / cm³To the extent
It was Further, in the above crystal growth, an arrow 306 indicates
The length of crystal growth in the direction parallel to the substrate is
Are all amorphous regions, and the collision of crystal growth in the lateral direction
When there was no match, it was about 130 μm.

Next, as shown in FIG. 4C, the mask 3
After etching away 04, the laser beam 307 is irradiated to recrystallize the region 303b in which the crystal has grown in the lateral direction to form a higher quality crystalline silicon film.

As the laser beam 307 at this time, in the third embodiment, a XeCl excimer laser (wavelength 308n) is used.
m, pulse width 40 nsec.)
Energy density of 200 to 450 mJ / cm ³ , for example, 350 m by heating to 00 to 450 ° C., for example, 400 ° C.
The irradiation conditions were irradiation at J / cm ³ . The beam size of the laser light 307 is 15 on the surface of the substrate 301.
A beam spot having a long shape of 0 mm × 1 mm was formed, and the beam spot was sequentially scanned in a direction perpendicular to the long direction with a step width of 0.05 mm. As a result, an arbitrary point on the crystalline silicon film 303 is irradiated with the laser light 307 a total of 20 times. By repeatedly irradiating the laser light 307 as described above, crystal defects, minute amorphous regions, etc. remaining in the crystalline silicon film 303 obtained by solid-phase crystallization are preferentially dissolved. The entire silicon film is recrystallized by reflecting only the good crystallinity of the crystallized region, resulting in a higher quality crystalline silicon film.

Next, as shown in FIG. 4D, element isolation is performed by removing an unnecessary portion of the silicon film by using the region 303b of the crystalline silicon film in which the crystal is grown in the lateral direction. Then, a crystalline silicon film 308n to be an active region of the N-type TFT later and a crystalline silicon film 308p to be an active region of the P-type TFT later are formed.

Next, as shown in FIG. 4E, a film thickness of 20 to 150 nm, for example, 10 nm, is formed so as to cover the crystalline silicon films 308n and 308p to be the active regions, respectively.
Silicon oxide film 309 as a gate insulating film having a film thickness of 0 nm
To form a film. To form the silicon oxide film 309, in the third embodiment, TEOS (Tetra EthoxyOr) is used.
The substrate temperature is 150 to 600 ° C., preferably 300 to 600 ° C., in the presence of oxygen.
It was heated to 450 ° C. and decomposed and deposited by the RF plasma CVD method. Subsequently, a refractory metal is deposited on the silicon oxide film 309 by a sputtering method, and this is patterned to form gate electrodes 310n and 310p located at predetermined portions on the crystalline silicon film 303. Tantalum (Ta) and tungsten (W) are desirable as the refractory metal used to form the gate electrodes 310n and 310p. In the third embodiment, tungsten is used and has a thickness of 300 to 600 nm, for example, 450 nm.
The gate electrodes 310n and 310p are formed so that

Subsequently, phosphorus (P) 312 is implanted by using the ion doping method. In this case, the gate electrode 31
0n and 310p serve as masks, and gate electrodes 310n and 310n
310p and crystalline silicon films 308n and 30 underneath
Phosphorus 312 is not injected during 8p. In the third embodiment, phosphine (PH ₃ ) is used as a doping gas for doping phosphorus 312, and the doping condition is an acceleration voltage of 60 to 90 kV, for example, 80 kV.
V and the dose amount was 1 × 10 ¹² to 1 × 10 ¹⁴ cm ⁻² , for example, 2 × 10 ¹³ cm ⁻² .

By this step, the island-shaped silicon film 308 is formed.
n and 308p, gate electrodes 310n and 310p
The regions not covered with the regions become the regions 314n and 314p into which the low-concentration phosphorus 312 is implanted, and
The regions 313n and 313p, which are respectively masked by the n and 310p and into which the impurity 312 is not implanted, are formed in the T
It becomes the channel region of FT.

Next, as shown in FIG. 5A, a crystalline silicon film 308n, 30n is formed by a photolithography process.
Photoresists are provided to cover the gate electrodes 310n and 310p on the 8p once, respectively, and serve as a mask 316 for selective doping so that P-type impurities are not implanted.

Then, in this state, an impurity (phosphorus) 320 is further implanted into the active region by ion doping using the resist mask 316 as a mask. As the doping at this time, so-called through doping is applied, which is performed through the gate insulating film 309. In the third embodiment, as a doping gas for doping phosphorus 320,
Using phosphine (PH ₃ ), the accelerating voltage is 60 to 90 kV, for example, 80 kV, and the dose amount is 2 × 10 ¹⁵ to 8 × 10 ¹⁵ cm ⁻² , for example, 5 × 10 ¹⁵ cm ^−2. And

By this step, the N-type impurity region 318n in the N-channel TFT is formed. In the P-channel TFT, the regions serving as the source / drain regions are N-type impurity regions at this stage because they are doped with phosphorus. Further, phosphorus 320 is not implanted into the regions masked by the gate electrodes 310n and 310p and the resist mask 316. In the N-channel TFT, the gate electrode 310
region 314 covered by resist mask 316 outside n
n is a low concentration impurity (LD
D) area.

Next, after removing the photoresist 316 used as a mask for selectively doping phosphorus, as shown in FIG. 5B, a crystalline silicon to be an N-type TFT is formed by a photolithography process. A photoresist 319 is provided to cover the gate insulating film 309 on the film 308n and the gate electrode 310n to serve as a mask for selective doping so that P-type impurities are not implanted.

This mask 319, as shown in FIG.
It is provided so that a part of the active region 308n of the N-type TFT is exposed. The P-type TFT is completely exposed.

Then, in this state, the ion doping method is used.
Depending on the entire surface of the P-type TFT and a part of the N-type TFT
Implant boron. In the third embodiment, boron is implanted.
Diborane (B₂H₆)
Use 1 x 10¹⁶~ 5 x 10 ¹⁶cm^-2, For example, 2 × 1
0¹⁶cm^-2At a high dose of 40-80 kV, for example
For example, by applying an acceleration voltage of 65 kV
I went

In this step, in the P-type TFT, the region 321 where the gate electrode 310p is not provided.
As a result of so-called counter-doping being performed, boron is injected into the silicon, and phosphorus is canceled and the characteristics are inverted by the excess boron, so that the P-type impurity regions 321p and 32
1p '. Therefore, in the high-concentration phosphorus-doped region 318p and the low-concentration phosphorus-doped region 314p, the characteristics are both inverted to the P-type region by the implantation of boron, and become the high-concentration P-type impurity region. This region 321p becomes the source / drain region of the P-type TFT. In the N-type TFT, the region exposed from the resist mask 319 is doped with boron, and the region outside the TFT is counter-doped with boron to form a region 321n in which the characteristics are inverted to P-type. In this way, the N-channel TFT and the P-channel TFT can be formed on the same substrate.

Next, as shown in FIG. 5D, after removing the photoresist 319 provided as a mask for selective doping, high speed etching is performed in an inert gas atmosphere, for example, a nitrogen gas atmosphere. Apply thermal annealing treatment. The annealing temperature in this rapid thermal annealing is 6
The range of 00 to 750 ° C., the processing time is 1 second to 10 minutes, and more preferably the processing time is 1 to 5 minutes under the temperature condition of 620 to 700 ° C. The rate of temperature increase up to the rapid thermal annealing temperature is from the residual heat temperature of 500 ° C. or lower to at least 100 ° C./minute or higher, and
It is more preferable that the temperature is 200 ° C./minute or more. In Example 3, the residual heat temperature of 400 ° C. to the heating rate of 200 ° C.
The rapid thermal annealing treatment temperature is raised to 650 ° C./min, and 2
After annealing for about 10 minutes,
The temperature was lowered at 0 ° C / min. In the third embodiment, such a rapid thermal annealing process is performed by using a resistance heating furnace to provide a temperature gradient in the furnace and blowing a high temperature nitrogen gas onto the substrate surface at the annealing position in the furnace. went. Further, the temperature increase / decrease up to the annealing temperature was performed by controlling the speed of inserting the substrate into the furnace.

By performing this rapid thermal annealing step, the channel region 313 is formed by the phosphorus heavily doped in the source / drain regions and the boron doped in the regions 321n and 321p.
The nickel remaining in n and 313p is moved to the source / drain regions adjacent to the channel region in the directions indicated by arrows 322 in FIGS. 3 and 4H. In this rapid thermal annealing process, the channel regions 313n, 313p
Since the nickel concentration in the source and the drain concentration in the source / drain region where phosphorus is doped to a high concentration as the gettering sink does not reach the thermal equilibrium segregation state, the junction portion that joins the source / drain region in the channel region Nickel in the vicinity of is gettered intensively. As a result, a nickel concentration gradient as shown in FIG. 6 is obtained in the channel region and the source / drain regions.

Further, as compared with the above-described first embodiment, the source / drain regions of the P-type TFT are counter-doped with boron in addition to phosphorus, and gettering compared to the case where only phosphorus is doped. Efficiency is improved,
Acts as a stronger gettering sink. As a result, the concentration of nickel remaining in the vicinity of the junction with the source / drain region in the channel region of the P-type TFT after completion of the heat treatment is equal to or lower than the lower limit of measurement by SIMS,
It was reduced to 1 × 10 ¹⁶ atoms / cm ³ or less.
Further, the nickel remaining in this region is not in a silicide state but exists in a solid solution state as interstitial nickel.

In this rapid thermal annealing process, the source / drain regions and the LDD regions are activated at the same time, and the sheet resistance value of the N-type impurity region obtained after this heat treatment is 0.4 to 0.8 kΩ / □,
The sheet resistance value of the P-type impurity region is 1 to 1.5 kΩ / □
Met. Further, by the above heat treatment, baking treatment of the gate insulating film is performed at the same time, so that bulk characteristics of the silicon oxide film itself and interface characteristics between the crystalline silicon film and the silicon oxide film can be improved.

Next, as shown in FIG. 5D, a silicon oxide film having a film thickness of 900 nm is formed as an interlayer insulating film 324 by the plasma CVD method. Then, contact holes are formed in portions of the interlayer insulating film 324 corresponding to the source region and the drain region on the crystalline silicon film of each TFT. An electrode / wiring 32 electrically connected to the source / drain region of the TFT is formed in each contact hole formed in the interlayer insulating film 324 by a metal material, for example, a two-layer film of titanium nitride and aluminum.
5 is formed. Then, under a hydrogen atmosphere of 1 atm, 350
The N-channel TFT and the P-channel TFT are completed by annealing for 1 hour under the temperature condition of ° C. Furthermore, if necessary, N-type and P-type T
It is also possible to provide a contact hole on the gate electrode of the FT and connect the wiring. Further, in order to protect the N-type and P-type TFTs, a protective film made of a silicon nitride film or the like may be provided on the TFTs.

CMO manufactured through the steps described above
In S configuration circuit, the field effect mobility of each TFT, 250~300cm ² / Vs in the N-type TFT, the high value of 120~150cm ² / Vs in the P-type TFT obtained, the threshold voltage, N Very good characteristics of about 1 V for the p-type TFT and about -1.5 V for the p-type TFT were obtained. Moreover, there is no abnormal increase in the leak current during the OFF operation of the TFT, which frequently occurs in the TFT manufactured by the conventional method, and the leak current itself is 1 p per unit W.
A very low value of A or less was stably shown. This value is
There was no difference in comparison with the conventional TFT manufactured without using a catalytic element, and the manufacturing yield could be greatly improved.

Further, the TFT of the present Example 3 showed almost no deterioration in characteristics even after repeated measurements, durability tests by bias and temperature stress, and it was very much compared with the TFT manufactured by the conventional method. The circuit characteristics are highly reliable and stable.

Although the three embodiments based on the present invention have been specifically described above, the present invention is not limited to the above three embodiments, and various modifications based on the technical idea of the present invention are possible. It is possible.

For example, in the above three embodiments,
As a heat treatment for gettering nickel, a method of using a furnace core tube having an inner circumference of a shape substantially similar to the outer shape of the substrate was shown, but a resistive heating furnace (furnace furnace) having a normal shape is also used. It is possible to perform similar processing. Also, other RTA-like annealing methods such as a single wafer method can be used. When heat treatment is performed by rapid thermal annealing, a halogen lamp, UV
The same treatment can be performed by using a lamp heating method such as a lamp or an arc lamp.

As a method of introducing nickel,
The method of applying a solution of nickel salt on the surface of the amorphous silicon film was used. Before the amorphous silicon film was formed, nickel was introduced to the surface of the base film to form the amorphous silicon film. The crystal may be grown by diffusing nickel from the lower layer side. That is, crystal growth may be performed from the upper surface side or the lower surface side of the amorphous silicon film.

As the method of introducing nickel, various methods can be used in addition to the method of the above embodiment. For example, there is a method of using an SOG (spin on glass) material as a solvent for dissolving a nickel salt and diffusing it from a SiO ₂ film. In addition to the sputtering method described in the third embodiment, a method of forming a thin film by a vapor deposition method, a plating method, a method of directly introducing it by an ion doping method, or the like can be used.

Further, as a catalyst element for promoting crystallization, in addition to nickel, cobalt, iron, palladium, platinum,
The same effect can be obtained by using copper, gold, or the like.

Further, in order to obtain a gettering effect due to the introduction of nickel, nitrogen, arsenic, antimony, or bismuth can be used in addition to phosphorus which is a Group 5 B element. In addition, in the above-described Example 2, argon was used for doping. However, similar effects can be obtained by using cryptophane, xenon or the like instead of argon.

Further, in the above embodiment, a heating method by irradiation of excimer laser light which is a pulse laser is used as a method for further improving the crystallinity of the crystalline silicon film crystallized by nickel. The same processing can be performed by irradiating other laser light such as continuous wave Ar laser irradiation.

As a device to which the semiconductor device of the present invention is applied, in addition to an active matrix type substrate for liquid crystal display, for example, a contact type image sensor, a driver built-in thermal head, an organic EL or the like is used as a light emitting element. Even when applied to a driver-incorporated optical writing element or display element, a three-dimensional IC, or the like, these elements can achieve high performance such as high speed and high resolution.

Furthermore, the present invention is not limited to the MOS type transistors described in the above embodiments, but can be widely applied to a wide range of semiconductor processes such as bipolar transistors and electrostatic induction transistors made of crystalline semiconductor. it can.

[0219]

According to the semiconductor device and the method of manufacturing the same of the present invention, the second heat treatment for moving the catalytic element contained in the active region to the high-concentration impurity region includes the concentration and the high concentration of the catalytic element contained in the active region. The concentration of the catalyst element contained in the impurity region is set so as not to reach the segregated state of the thermal equilibrium state. The semiconductor device thus obtained is
A stable, high-performance semiconductor device with few characteristic variations such as an abnormal increase in leak current is provided.

Further, according to the present invention, a high-performance semiconductor device having a high degree of integration can be manufactured by a simple manufacturing process, the non-defective rate can be improved in the manufacturing process, and the cost can be reduced. In particular, when the semiconductor device of the present invention is applied to a liquid crystal display device, the switching characteristics of the pixel switching TFT required for the active matrix substrate are improved, and the high performance and high integration required for the TFT configuring the peripheral drive circuit section are achieved. And a driver monolithic active matrix substrate that constitutes an active matrix portion and a peripheral drive circuit portion on the same substrate can be realized, and the module can be made compact, high performance, and cost can be reduced.

[Brief description of drawings]

1A to 1G are cross-sectional views each illustrating a method of manufacturing a semiconductor device according to a first embodiment of the present invention.

FIGS. 2A to 2H are cross-sectional views each illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a plan view showing a semiconductor device according to a third embodiment of the present invention.

4A to 4E are cross-sectional views each illustrating a method for manufacturing a semiconductor device according to a third embodiment of the present invention, step by step.

5A to 5D are cross-sectional views each illustrating a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

6A shows a concentration gradient of a catalytic element from a channel region to a drain region of the semiconductor device of the present invention, and FIG. 6B shows a plan view of the semiconductor device of the present invention. ing.

7A is a graph showing a characteristic curve of a P-type TFT actually manufactured by the method for manufacturing a semiconductor device of the present invention, and FIG. 7B is a graph showing a uniform characteristic over the entire element region. It is a graph which shows the characteristic curve of the P-type TFT produced by the conventional method which contains a catalytic element in concentration.

8A is a schematic view showing a heat treatment apparatus for performing a second heat treatment in the present invention, FIG. 8B is a plan view of a main part thereof, and FIG. 8C is an operation explanatory view thereof. (D) is a plan view of a main part of a conventional heat treatment apparatus.

9A to 9C show band diagrams in a region extending from a channel region to a drain region in an N-type TFT, respectively.

[Explanation of symbols]

101, 201, 301 glass substrate 102, 202, 302 Base film 103, 203, 303 a-Si film 103 ', 203' crystalline silicon film 304 mask 105, 205, 305 Nickel 306 Crystal growth direction 107, 207, 307 Laser light 108, 208, 308 crystalline silicon film 109, 209, 309 Silicon oxide film 110, 210, 310 Gate electrode 211 oxide layer 112, 312 Phosphorus (low concentration) 113, 213, 313 Channel region 114, 314 LDD region 215 Offset area 116, 316 doping mask 117, 217, 317 phosphorus (high concentration) 118, 218, 318 Source / drain regions 219 Argon 320 Boron Source / drain region of 321 P-type TFT 122, 222, 322 Nickel gettering direction 223 laser light 124, 224, 324 Interlayer insulating film 125,225,325 electrode / wiring 126, 226, 326 N-channel TFT 327 P-channel TFT

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 2H092 JA25 JA28 JA46 KA04 KA10                       MA08 MA22 MA27 MA29 MA30                       NA21 NA25                 5F052 AA11 AA17 BA07 CA02 DA02                       EA16 FA06 FA19 HA06 JA01                 5F110 AA01 AA06 AA28 BB02 BB04                       BB10 BB11 CC02 DD02 DD13                       EE01 EE03 EE04 EE34 EE44                       FF02 FF29 FF30 FF32 GG02                       GG13 GG25 GG35 GG45 HJ01                       HJ02 HJ04 HJ12 HL01 HL03                       HL07 HL11 HM14 HM15 NN03                       NN04 NN23 NN24 NN35 PP01                       PP03 PP04 PP05 PP06 PP29                       PP34 PP35 PP36 QQ08 QQ23                       QQ28

Claims (39)

[Claims] 1. A semiconductor device in which a crystalline silicon film is formed as an active region on an insulating substrate, the active region having an active region and a high-concentration impurity region, A semiconductor device in which the active region contains a catalytic element that promotes crystallization of the amorphous silicon film, and the concentration of the catalytic element is low in the vicinity of the end of the active region. 2. The semiconductor device according to claim 1, wherein the concentration of the catalytic element contained in the active region is configured to continuously decrease from the central portion to the end portion of the active region. 3. A semiconductor device in which a crystalline silicon film is formed as an active region on an insulating substrate, the active region having an active region and a high-concentration impurity region, The active region contains a catalytic element that promotes crystallization of the amorphous silicon film, and the catalytic element does not precipitate as a silicide state in the vicinity of the end portion of the active region and becomes a solid solution state. A semiconductor device characterized by 4. The length of a region in which the catalytic element is in a solid solution state without being deposited as a silicide state in the active region is 2 μm from the end of the active region.
The semiconductor device according to claim 3, which is the above. 5. The average value of the concentration of the catalyst element contained in the high-concentration impurity region is higher than the average value of the concentration of the catalyst element contained in the active region.
4. The semiconductor device according to any one of 4 above. 6. The catalyst element contained in the high-concentration impurity region is in a solid solution state without being deposited as silicide in a crystalline silicon film containing a high concentration of impurities. 6. The semiconductor device according to any one of 5 to 5. 7. The low concentration impurity region is formed between the active region and the high concentration impurity region.
7. The semiconductor device according to any one of to 6. 8. The offset region according to claim 1, wherein an offset region containing an impurity having a similar concentration to that of the active region is formed between the active region and the high concentration impurity region. Semiconductor device. 9. The concentration of the catalytic element contained near the end of the active region is 1/10 or less of the concentration of the catalytic element contained near the center of the active region.
The semiconductor device according to any one of 1. 10. The concentration of the catalytic element contained in the vicinity of the end of the active region is 1 × 10 ¹⁵ to 1 × 10 ¹⁷ atoms /
The semiconductor device according to claim 1, which is within a range of cm ³ . 11. The catalyst element is Ni, Co, Fe,
The semiconductor device according to claim 1, wherein the semiconductor device is one kind or a plurality of kinds selected from Pd, Pt, Cu, and Au. 12. The catalyst element is at least Ni.
The semiconductor device according to claim 11, wherein the semiconductor device is included. 13. The high-concentration impurity region has P, A
The semiconductor device according to any one of claims 1 to 10, which contains one or more kinds of Group 5 B elements selected from s and Sb. 14. The semiconductor device according to claim 13, wherein the high-concentration impurity region contains at least P. 15. The semiconductor device according to claim 13, wherein the high-concentration impurity region further contains a Group 3 B element in addition to a Group 5 B element. 16. The semiconductor device according to claim 15, wherein the high-concentration impurity region contains P as an element selected from Group 5 B and B as an element selected from Group 3 B. 17. The semiconductor according to claim 1, wherein the high-concentration impurity region contains one or more kinds of Ar, Kr, and Xe as an element selected from rare gas elements. apparatus. 18. The semiconductor device according to claim 17, wherein the high-concentration impurity region contains at least Ar as an element selected from the rare gases. 19. A catalyst element introducing step of forming an amorphous silicon film on a substrate having an insulating surface and introducing a catalyst element which promotes crystallization of the amorphous silicon film on the amorphous silicon film, A crystallization step of crystallizing the amorphous silicon film into a crystalline silicon film by performing a first heat treatment for crystallizing the amorphous silicon film, and a part of the crystalline silicon film. An impurity introducing step of selectively introducing an element selected from Group 5B into the region to form a high-concentration impurity region, and introducing the catalyst element contained in the crystalline silicon film into the Group 5B element. A second heat treatment for moving the active region to a high-concentration impurity region by moving the catalytic element contained in the active region of the crystalline silicon film into which the group 5 B element is not introduced. And a second heat treatment of the moving step. A semiconductor device characterized in that the concentration of the catalytic element contained in the active region and the concentration of the catalytic element contained in the high-concentration impurity region are at least prevented from reaching a segregated state in a thermal equilibrium state. Method. 20. A catalytic element for forming an amorphous silicon film on a substrate having an insulating surface and introducing a catalytic element for promoting crystallization of the amorphous silicon film into a part of the amorphous silicon film. Introducing step and first heat treatment for crystallizing the amorphous silicon film are performed so as to be parallel to the substrate surface from a part of the region into which the catalytic element is introduced to the surrounding region. Crystallization step of crystallizing the amorphous silicon film into a crystalline silicon film in the horizontal direction, which is a horizontal direction, and a crystalline silicon film consisting only of the crystalline silicon film in the laterally grown region. A region forming step of forming a region of the crystalline silicon film, and an impurity introducing process of forming a high concentration impurity region by selectively introducing an element selected from Group 5B into a partial region of the crystalline silicon film, The Group 5 B element is introduced into the crystalline silicon film as the catalytic element. And a second heat treatment for moving the catalyst element contained in the region which becomes the active region without introducing the group 5 B element to the high-concentration impurity region. However, the second heat treatment of the transfer step is performed so that the concentration of the catalytic element contained in the active region and the concentration of the catalytic element contained in the high-concentration impurity region do not reach at least a segregated state in a thermal equilibrium state. A method for manufacturing a semiconductor device, comprising: 21. An element selected from Group 5B at a concentration lower than that of the high-concentration impurity region is provided between the high-concentration impurity region and the active region before or after performing the impurity introduction step. 21. The method of manufacturing a semiconductor device according to claim 19, further comprising the step of forming the introduced region. 22. The method further comprising a step of forming an offset region into which the Group 5 element is not introduced between the high concentration impurity region and the active region, before or after performing the impurity introducing process. 21. The method for manufacturing a semiconductor device according to 19 or 20. 23. The second heat treatment of the moving step is performed within a temperature range of a heating temperature of 400 ° C. to 550 ° C. for a treatment time of 30 minutes to 2 hours. Of manufacturing a semiconductor device of. 24. In the second heat treatment of the moving step, the substrate is heated at a heating rate of at least 5 ° C./minute or more until the substrate reaches a heat treatment temperature for performing the second heat treatment, The method for manufacturing a semiconductor device according to claim 23, wherein after the second heat treatment is completed, the temperature is decreased at least at 5 ° C./minute at a temperature decrease rate of the above. 25. In the second heat treatment of the moving step, the substrate surface of the insulating substrate is oriented in the core tube direction in a core tube having a cross-sectional shape substantially similar to the planar shape of the insulating substrate. 25. The method of manufacturing a semiconductor device according to claim 23, wherein a furnace is arranged so that the distance between the inner peripheral side surface of the furnace core tube and the substrate is minimized. 26. The planar shape of the substrate is rectangular, and the cross-sectional shape of the furnace core tube of the furnace is formed in a rectangular shape that is one size larger and substantially similar to the planar shape of the substrate. 26. The method for manufacturing a semiconductor device according to claim 25, wherein: 27. The second heat treatment of the moving step comprises
23. The method of manufacturing a semiconductor device according to claim 19, wherein the rapid thermal annealing treatment is performed within a temperature range of 00 to 750 [deg.] C. for a treatment time of 1 second to 10 minutes. 28. The rapid thermal annealing process is performed at 500.degree.
28. The method of manufacturing a semiconductor device according to claim 27, wherein the temperature is raised at a heating rate of 100 [deg.] C./minute or more from the following residual heat temperature to the annealing temperature for performing the rapid thermal annealing process. 29. The rapid thermal annealing treatment is performed by lamp irradiation using a tungsten-halogen lamp, xenon arc lamp, UV lamp, or the like, or a heating treatment by blowing a high temperature gas onto the substrate surface. 29. A method of manufacturing a semiconductor device according to 27 or 28. 30. The method further comprising the step of introducing an element selected from Group 3 B into at least a part of the high-concentration impurity region before or after performing the impurity introducing step.
23. A method for manufacturing a semiconductor device according to any one of 22 to 22. 31. The method according to claim 19, further comprising a step of introducing an element selected from rare gases into at least a part of the high-concentration impurity region when performing the impurity introducing step or before or after the impurity introducing step. A method of manufacturing a semiconductor device according to any one of the above. 32. The element selected from Group 5 B is
23. The method for manufacturing a semiconductor device according to claim 19, which is one or more kinds selected from P, As, and Sb. 33. The method of manufacturing a semiconductor device according to claim 32, wherein at least P is contained as an element selected from Group 5 B. 34. The method of manufacturing a semiconductor device according to claim 30, wherein P is used as an element selected from Group 5 B and B is used as an element selected from Group 3 B. 35. The element selected from the rare gases is
32. The method of manufacturing a semiconductor device according to claim 31, including one or more kinds selected from Ar, Kr, and Xe. 36. The method of manufacturing a semiconductor device according to claim 35, wherein the element selected from the rare gases contains at least Ar. 37. The catalyst element is Ni, Co, Fe,
37. The method for manufacturing a semiconductor device according to claim 19, which is one or more kinds selected from Pd, Pt, Cu, and Au. 38. At least Ni as the catalyst element
38. The method of manufacturing a semiconductor device according to claim 37, comprising: 39. The semiconductor according to claim 19, further comprising a step of irradiating the crystalline silicon film with laser light to enhance its crystallinity after performing the crystallization step. Device manufacturing method.