JP2003297601A - Chip resistor, circuit device having mounted chip resistor, and hybrid integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the mounting surface-area of a chip resistor 10, when mounting it on a circuit device 20 and a hybrid integrated circuit device 30, by simplifying the structure of the chip resistor 10. <P>SOLUTION: A resistance body 11 is formed on the surface of an insulating substrate 13 with the base material of the chip resistor 10, and electrode portions 12 connected electrically with the resistance body 11 are formed in both the end portions of the surface, whereon the resistance body 11 is formed. Since the resistance body 11 and the electrode portions 12 are formed on the one-side surface of the chip resistor 10, the structure of the chip resistor 10 can be simplified. Therefore, the mounting densities of the circuit device 20 and the hybrid integrated circuit device 30 can be improved. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip resistor and a device having the same mounted thereon, and more particularly to a chip resistor having a simplified structure and a device having the same mounted thereto.

[0002]

2. Description of the Related Art Referring to FIG. 8, a conventional chip resistor 5 is used.
0 will be described. FIG. 8A is a sectional view of the chip resistor 50. FIG. 8B is a sectional view showing a state in which the chip resistor 50 is mounted on the substrate 55.

Referring to FIG. 8A, a chip resistor 50
The configuration of will be described. The chip resistor 50 is an insulating substrate 53.
And a resistor 51 formed on the surface of the insulating substrate 53, and electrode portions 52 formed on both ends of the insulating substrate 53.

The insulating substrate 53 is a base of the chip resistor 50. As the material of the insulating substrate 53, a ceramic material having excellent mechanical strength, thermal conductivity, insulation and the like is used.

The resistor 51 is generally a mixture of a conductor and glass. As a method of forming the resistor on the surface of the insulating substrate 53, the resistor 51 is formed by applying a paste-like mixture of a conductor and glass to the insulating substrate 53 and baking at a high temperature.

The electrode portion 52 is electrically connected to the resistor 51 and has a function as an electrode of the chip resistor 50.
The electrode portion 52 is formed so as to cover both ends of the elongated insulating substrate 53. In general, the electrode part 52 has a three-layer structure, and in many cases, a silver-palladium layer, a Ni layer, and a solder plating layer are formed from the inside.

Referring to FIG. 8B, the chip resistor 50
The state in which is mounted on the substrate 55 will be described. The chip resistor 50 as described above is mounted on, for example, a conductive pattern 56 formed on a substrate 55 via a brazing material 57 such as solder. The side surface of the end portion of the chip resistor 50 is covered with the electrode portion 52. Therefore, when the chip resistor 50 is mounted on the substrate 55 via the brazing material 57, fillets made of the brazing material 57 are formed at both ends of the chip resistor 50.

[0008]

When the chip resistor as described above is mounted on the substrate, the fillet made of the brazing material has a role of maintaining the connection strength between the chip resistor and the mounting substrate. The device having the structure of resin sealing has the following problems.

First, the longitudinal end portion of the chip resistor 50 has the problem that the structure is complicated because the electrode portion 52 is formed near the side surface portion.

Secondly, when the chip resistor 50 is mounted on the substrate 55 via the brazing material 57, a fillet made of the brazing material 57 is formed at the end of the chip resistor 50. Therefore, the mounting area of the chip resistor 50 increases. Therefore, there is a problem that the packaging density of products such as a circuit device in which the chip resistor 50 is mounted is reduced. Furthermore, there is a problem that this large fillet has an unnecessarily large electric capacity, which reduces the transmission speed of electric signals.

The present invention has been made in view of the above problems, and a main object of the present invention is to provide a chip resistor having a simplified structure and a circuit device in which the chip resistor is mounted.
It is to provide a hybrid integrated circuit device.

[0012]

First, the present invention provides a chip resistor having an insulating substrate, a resistor formed on the surface of the insulating substrate, and electrode portions formed at both ends of the resistor. In the container, the electrode portion is formed only on the surface of the insulating substrate.

Secondly, the present invention provides a conductive pattern, a chip resistor mounted on the conductive pattern via a brazing material, and a back surface of the conductive pattern exposed to expose the conductive pattern and the chip resistor. In a circuit device having an insulating resin for sealing, the chip resistor is mounted on the conductive pattern with a surface on which a resistor and an electrode portion are formed as a lower surface.

Thirdly, the present invention is characterized in that the brazing material joins the electrode part and the conductive pattern.

Fourthly, the present invention is characterized in that the insulating resin adheres to the conductive pattern and the chip resistor to secure the connection strength between the chip resistor and the conductive pattern.

Fifthly, the present invention encloses a substrate, a conductive pattern formed on the surface of the substrate, a chip resistor mounted on the conductive pattern via a brazing material, and the chip resistor. In the hybrid integrated circuit device having an insulating resin for stopping, the chip resistor is mounted on the conductive pattern with the surface on which the resistor and the electrode portion are formed as the lower surface.

Sixth, the present invention is characterized in that the brazing material joins the electrode part and the conductive pattern.

Seventhly, the present invention is characterized in that the insulating resin adheres to the substrate, the conductive pattern and the chip resistor to secure the connection strength between the chip resistor and the conductive pattern. To do.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment of Chip Resistor 10) Referring to FIG. 1, the structure and the like of a chip resistor 10 of the present invention will be described. 1A is a sectional view of the chip resistor 10, and FIG. 1B is a sectional view showing a state in which the chip resistor 10 is mounted on the substrate 15.

First, the structure of the chip resistor 10 will be described with reference to FIG. The chip resistor 10 includes an insulating substrate 13 and a resistor 11 formed on the surface of the insulating substrate 13.
And electrode portions 12 formed on both ends of the resistor 11. The electrode portion 12 is formed only on the surface of the insulating substrate 13. Each of these components will be described below.

The insulating substrate 13 serves as a base of the chip resistor 10. As the material of the insulating substrate 13, a ceramic material having excellent mechanical strength, thermal conductivity, insulation, etc. is used.

The resistor 11 is a mixture of a conductor and glass. As a method of forming the resistor on the surface of the insulating substrate 13, a mixture of a paste-like conductor and glass is applied to the insulating substrate 13 and baked at a high temperature to form the resistor 1
1 is formed. Further, in order to protect the resistor 11 mechanically and electrically, a protective layer made of glass may be provided above the resistor 11.

The electrode portion 12 is electrically connected to the resistor 11 and has a function as an electrode of the chip resistor 10.
The electrode portion 12 is formed so as to cover only the surfaces of the insulating substrate 13 formed in the elongated shape near both ends. And
The electrode portion 12 generally has a three-layer structure, and for example, a silver palladium layer, a Ni layer, and a solder plating layer are formed from the insulating substrate 13 side. Here, the electrode portion 12 is formed only on the surface of the chip resistor 10 and is not formed on the side surface portion.

Referring to FIG. 1B, the chip resistor 10
The state in which is mounted on the substrate 15 will be described. Chip resistor 1
0 is mounted on the conductive pattern 16 formed on the substrate 15 through the brazing material 17 with the surface on which the resistor 11 is formed facing downward. In the conventional example, the fillet made of the brazing material 17 was formed at the end of the resistor 11,
Fillets made of brazing material are not formed here. The brazing material 17 joins the lower surface of the electrode portion 12 and the conductive pattern 17. Therefore, the chip resistor 10 is mounted on the substrate 15
The mounting area required for mounting is approximately the same as the planar size of the chip resistor 10.

The chip resistor 10 described above with reference to FIG.
The configuration of the circuit device 20 in which is mounted will be described. Figure 2
2A is a plan view of the circuit device 20, and FIG. 2B is a sectional view of FIG.

Referring to FIGS. 2 (A) and 2 (B),
The circuit device 20 has the following configuration. That is, the conductive pattern 21, the chip resistor 10 mounted on the conductive pattern 21 via the brazing material 25, and the insulating resin 24 that exposes the back surface of the conductive pattern and seals the conductive pattern and the chip resistor 10. The circuit device 20 is constituted by. Further, the chip resistor 10 is mounted on the conductive pattern 21 with the surface on which the resistor and the electrode portion are formed as the lower surface. Each of these components will be described below.

The conductive pattern 21 is made of metal such as copper,
The back surface is exposed and embedded in the insulating resin 24.
Here, the conductive pattern 20 forms the die pad 21A on which the semiconductor element 22 is mounted and the bonding pad 21B to which the metal thin wire 23 is connected.

The semiconductor element 22 is a circuit element mounted on the conductive pattern 21 together with the chip resistor 10 via a brazing material such as solder. As the circuit element mounted on the conductive pattern 21, the chip resistor 10 and the semiconductor element 22 are adopted here, but other circuit elements can also be adopted. For example, active elements such as ICs and passive elements such as capacitors can be generally adopted as circuit elements. The semiconductor element 22 is mounted face up, and the semiconductor element 22 and the conductive pattern 21 are mounted.
B is electrically connected via a thin metal wire 23.

The chip resistor 10 is mounted on the conductive pattern 21 via the brazing material 25 with the surface on which the resistor 11 is formed facing downward. In the conventional example, the fillet made of the brazing material 17 was formed at the end of the resistor 11,
Here, the fillet made of the brazing material 25 is not formed. The brazing material 25 is formed on the lower surface of the electrode portion 12 and the conductive pattern 2.
It is joined with 1. Therefore, the mounting area required to mount the chip resistor 10 on the conductive pattern 21 is approximately the same as the planar size of the chip resistor 10. Also,
Since the chip resistor 10 is mounted with the surface on which the resistor 11 is formed facing downward, the distance between the conductive pattern 21 and the resistor 11 can be shortened.

The insulating resin 24 exposes the back surface of the conductive pattern 21 and seals the entire surface. Here, the semiconductor element 22, the chip resistor 10, and the thin metal wire 23 are sealed. As the material of the insulating resin 12, a thermosetting resin formed by transfer molding or a thermoplastic resin formed by injection molding can be adopted. In this way, the entire insulating resin 24
By sealing with, it is possible to prevent the chip resistor 10 from separating from the conductive pattern 21.

The chip resistor 10 described above with reference to FIG.
The configuration of another circuit device 30 in which is mounted will be described. 3A is a plan view of the circuit device 30, and FIG.
3B is a sectional view of FIG. In FIG.
The circuit device of the type that does not require a mounting substrate has been described. Here, a circuit device 30 having a structure in which the conductive pattern 31 is formed on the mounting substrate 36 will be described.

Referring to FIGS. 3A and 3B,
The circuit device 30 has the following configuration. That is, the mounting substrate 36, the conductive pattern 31 formed on the mounting substrate 36, the chip resistor 10 mounted on the conductive pattern 31 via the brazing material 35, and the conductive pattern 31 and the chip resistor 10 are sealed. The circuit device 30 is configured with the insulating resin 34 that operates. The pad 37 is formed on the back surface of the mounting substrate 36, and is electrically connected to the conductive pattern 31 via the through hole 38. Here, the chip resistor 10 is mounted on the conductive pattern 31 with the surface on which the resistor and the electrode portion are formed as the lower surface. Each of these components will be described below.

The conductive pattern 31 is made of metal such as copper,
It is formed on the mounting substrate 36. Here, the conductive pattern 31 forms a die pad on which the semiconductor element 33 is mounted and a bonding pad to which the metal thin wire 33 is connected. Further, the conductive pattern 31 is electrically connected to a pad 37 formed on the back surface of the mounting board 36 via a through hole 38 provided in the mounting board 36.

The semiconductor element 32 is a circuit element mounted together with the chip resistor 10 on the conductive pattern 31 via a brazing material such as solder. As the circuit element mounted on the conductive pattern 31, the chip resistor 10 and the semiconductor element 32 are adopted here, but other circuit elements can also be adopted. For example, active elements such as ICs and passive elements such as capacitors can be generally adopted as circuit elements. The semiconductor element 32 is mounted face up, and the semiconductor element 32 and the conductive pattern 31 are mounted.
B is electrically connected via a thin metal wire 33.

The chip resistor 10 is mounted on the conductive pattern 31 via the brazing material 35 with the surface on which the resistor 11 is formed facing downward. In the conventional example, the fillet made of the brazing material 17 was formed at the end of the resistor 11,
Here, the fillet made of the brazing material 35 is not formed. The brazing material 35 is formed on the lower surface of the electrode portion 12 and the conductive pattern 3
It is joined with 1. Therefore, the mounting area required for mounting the chip resistor 10 on the conductive pattern 31 is approximately the same as the planar size of the chip resistor 10. Also,
Since the chip resistor 10 is mounted with the surface on which the resistor 11 is formed facing downward, the distance between the conductive pattern 31 and the resistor 11 can be shortened.

The insulating resin 34 is the semiconductor element 3 in this case.
2. The chip resistor 10 and the thin metal wire 33 are sealed.
As the material of the insulating resin 34, a thermosetting resin formed by transfer molding or a thermoplastic resin formed by injection molding can be adopted. In this way, by sealing the whole with the insulating resin 34, it is possible to prevent the chip resistor 10 from being separated from the conductive pattern 31. That is, the chip resistor 10 is bonded to the conductive pattern by the two components of the brazing material and the insulating resin.

The chip resistor 10 described above with reference to FIG.
The configuration of the hybrid integrated circuit device 40 in which is mounted will be described.
4A is a perspective view of the hybrid integrated circuit device 40, and FIG. 4B is a cross-sectional view of FIG. 2A.

Referring to FIGS. 4A and 4B,
The hybrid integrated circuit device 40 has the following configuration.
That is, the substrate 41, the conductive pattern 42 formed on the surface of the substrate 41, the chip resistor 10 mounted on the conductive pattern 42 via the brazing material 45, and the insulating property for sealing the chip resistor 10 and the like. Hybrid integrated circuit device 40 composed of resin 46
Is configured. Here, the chip resistor 10 is mounted on the conductive pattern 42 with the surface on which the resistor 11 and the electrode portion 12 are formed as the lower surface. Further, as other components, the hybrid integrated circuit device 40 has leads 44 which are input / output terminals of the hybrid integrated circuit device 40 and circuit elements other than the chip resistor 10. Each of these components will be described below.

The substrate 41 is made of a material having excellent thermal conductivity such as metal or ceramic. And the substrate 41
An insulating layer is formed on the upper surface of the conductive layer in order to improve withstand voltage, and a conductive pattern 42 is formed. Here, the conductive pattern 42
Is a die pad on which circuit elements are mounted and a thin metal wire 4
Bonding pads and the like to which 6 is connected are formed.

The semiconductor element 43 is a circuit element mounted on the conductive pattern 42 together with the chip resistor 10 via a brazing material such as solder. As the circuit element mounted on the conductive pattern 42, the chip resistor 10 and the semiconductor element 43 are adopted here, but other circuit elements can also be adopted. For example, active elements such as ICs and passive elements such as capacitors can be generally adopted as circuit elements. The semiconductor element 44 is mounted face up, and the semiconductor element 43 and the conductive pattern 42 are mounted.
Are electrically connected via a thin metal wire 46.

The chip resistor 10 is mounted on the conductive pattern 42 via the brazing material 45 with the surface on which the resistor 11 is formed facing downward. In the conventional example, the fillet made of the brazing material 17 was formed at the end of the resistor 11,
Here, the fillet made of the brazing material 45 is not formed. The brazing material 45 is formed on the lower surface of the electrode portion 12 and the conductive pattern 4.
It is joined with 2. Therefore, the mounting area required for mounting the chip resistor 10 on the conductive pattern 42 is approximately the same as the planar size of the chip resistor 10. Also,
Since the chip resistor 10 is mounted with the surface on which the resistor 11 is formed facing downward, the distance between the conductive pattern 42 and the resistor 11 can be shortened.

The insulating resin 46 seals the entire circuit formed on the substrate 41. Here, the semiconductor element 4
3, the chip resistor 10 and the thin metal wire 46 are sealed.
As the material of the insulating resin 46, a thermosetting resin formed by transfer molding or a thermoplastic resin formed by injection molding can be adopted. In this way, by sealing the whole with the insulating resin 46, it is possible to prevent the chip resistor 10 from being separated from the conductive pattern 42.

(Second Embodiment for Explaining Method of Manufacturing Chip Resistor 10) A method of manufacturing the chip resistor 10 and a method of mounting the same will be described with reference to FIGS. The chip resistor 10 is manufactured and mounted in the following process. That is, a step of forming the resistors 11 and the electrode portions so as to form a large number of chip resistors 10 on the insulating substrate 13, and a step of dividing the insulating substrate 13 into individual chip resistors 10. The chip resistor 10 is manufactured and mounted by the process of mounting the chip resistor 10 on the conductive pattern. Such steps will be described below.

First Step: See FIG. 5 In this step, a large-sized insulating substrate 13 is prepared, and resistors 11 and electrode portions 12 constituting a plurality of chip resistors 10 are formed on the surface thereof. . FIG. 5A is a plan view of the insulating substrate 13 having a large number of resistors 11 and electrode portions 12 formed on the surface. 5 (B) is shown in FIG. 5 (A).
FIG.

The insulating substrate 13 has mechanical strength, thermal conductivity,
A ceramic material having excellent insulating properties is used. The size of the insulating substrate 13 depends on the size of the chip resistor 10 to be manufactured, but is a size such that a large number of chip resistors 10 can be formed in a matrix. In addition, a groove M is formed in a portion corresponding to the boundary line of the chip resistor 10 to be formed so that the chip resistor 10 can be divided in a later step reliably. The groove M may be formed only on one side of the resistor formation side or the opposite side.

The resistor 11 is manufactured from a mixture of a conductor and glass. Specifically, as a method of forming the resistor on the surface of the insulating substrate 13, the resistor 11 is formed by applying a paste-like mixture of a conductor and glass to the insulating substrate 13 and baking at a high temperature. This resistor 11
Is adjusted to a predetermined resistance value by a laser trimming device or the like. Further, in order to protect the resistor 11 mechanically and electrically, a protective layer made of glass may be provided above the resistor 11.

The electrode portion 12 is electrically connected to the resistor 51 and has a function as an electrode of the chip resistor 50.
The electrode portion 52 is formed so as to cover the surface of the elongated insulating substrate 13 near both ends. The electrode portion 12 has a three-layer structure, and, for example, a silver-palladium layer, a Ni layer, and a solder plating layer are laminated from the insulating substrate 13 side.

Second Step: See FIG. 6 In this step, the individual chip resistors 10 are formed by dividing the insulating substrate 13 on the surface of which the resistor 11 and the electrode portion 12 are formed. 6A is a cross-sectional view showing a state in which the insulating substrate 13 is attached to the adhesive sheet 42, and FIG. 6B is a cross-sectional view of FIG. 6A.

In this step, specifically, stress is applied to the insulating substrate 13 from the front surface side and the back surface side so that the insulating substrate 13 can be divided by being easily broken at the groove M. it can. The divided chip resistors are generally stored in a paper reel.

An example of a specific dividing method will be described with reference to FIG. The insulating substrate 13 having the resistor 11 and the electrode portion 12 formed on the surface is attached to the adhesive sheet 42. Then, by applying the bending stress as described above to the insulating substrate 13, the insulating substrate 13 is divided into the individual chip resistors 10 along the division line D. When the adhesive sheet 42 is stretched after being divided, a gap is formed between the divided individual chip resistors 10. Thus, the supply state using the adhesive sheet is also applicable.

Referring to FIG. 6B, the insulating substrate 13 is
The surface on which the resistor 11 and the electrode portion 12 are formed is a lower surface and is attached to the adhesive sheet 42. Then, a groove M is formed at a position corresponding to a boundary line of each chip resistor 10 formed on the insulating substrate 13. And
Since the division is performed by applying pressure from the front and back of the insulating substrate 13, the individual chip resistors 10 can be easily divided. Although the adhesive sheet 42 is used in the above description, a UV sheet may be used instead of the adhesive sheet 42.

Third Step: See FIG. 7 In this step, the chip resistors 10 individually divided in the previous step.
Is a step of mounting in a circuit device or a hybrid integrated circuit device. FIG. 7A is a cross-sectional view showing a state in which the chip resistor 10 is mounted on the conductive pattern 21. FIG. 7 (B)
FIG. 6 is a cross-sectional view showing a state in which the chip resistor 10 is mounted on the conductive pattern 32 of the hybrid integrated circuit device 30.

Referring to FIG. 7A, the chip resistor 10
A process of mounting the on the conductive pattern 21 of the circuit device 20 will be described. First, on the surfaces of the conductive patterns 21B and 21C on which the chip resistor 10 of the conductive pattern 21 is mounted,
A brazing material 25 such as solder is applied. The position where the brazing material 25 is applied corresponds exactly to the position of the electrode portion 12 of the chip resistor 10. Furthermore, the area where the brazing material 25 is applied is equal to the area of the electrode portion 12 of the chip resistor 10.

Next, the chip resistor 10 is connected to the conductive pattern 2.
1 is mounted on the brazing material 25 coated on the surface of the metal 1. The chip resistor 10 is mounted on the conductive pattern 21 with the surface on which the resistor 11 and the electrode portion 12 are formed as the lower surface. The work of mounting the chip resistor 10 can be performed using a chip mounter or a die bonder using a vacuum collet.

Since the electrode portion 12 is formed only on the lower surface of the chip resistor 10, the brazing material 25 does not adhere to the side surface of the chip resistor 10. Specifically, the fillet made of a brazing material as in the conventional example is not formed on the side surface of the chip resistor 10. From this, the brazing material 25 is
The electrode portion 12 and the conductive pattern 21 are joined together.

In this step, semiconductor elements and the like are mounted on the conductive pattern 21 in addition to the chip resistor 10. The process for manufacturing the circuit device 20 includes the following process after this. That is, there are a step of sealing with an insulating resin, a step of separating the conductive pattern 21 by etching or the like, and a step of separating the individual circuit devices 20 by dicing. Through these steps, the circuit device 20 as shown in FIG. 2 is completed.

Next, with reference to FIG. 7B, a process of mounting the chip resistor 10 on the conductive pattern 32 of the hybrid integrated circuit device 30 will be described. First, a brazing material 35 such as solder is attached to a portion of the conductive pattern 32 where the chip resistor 10 is mounted.
Apply. The position where the brazing material 35 is applied corresponds exactly to the position of the electrode portion 12 of the chip resistor 10. Furthermore, the area to which the brazing material 35 is applied is determined by the chip resistor 10
The area is equal to the area of the electrode portion 12.

Next, the chip resistor 10 is connected to the conductive pattern 3
2 is mounted on the brazing material 35 applied on the surface. The chip resistor 10 is mounted on the conductive pattern 32 with the surface on which the resistor 11 and the electrode portion 12 are formed as the lower surface. The work of mounting the chip resistor 10 can be performed using a chip mounter or a die bonder using a vacuum collet.

Since the electrode portion 12 is formed only on the lower surface of the chip resistor 10, the brazing material 35 does not adhere to the side surface of the chip resistor 10. Specifically, the fillet made of a brazing material as in the conventional example is not formed on the side surface of the chip resistor 10. From this, the brazing material 35 is
The electrode portion 12 and the conductive pattern 32 are joined together.

In this step, semiconductor elements and the like are mounted on the conductive pattern 21 in addition to the chip resistor 10. The process for manufacturing the circuit device 20 includes the following process after this. That is, the conductive pattern 32 and the chip resistor 1
0 and the like are sealed with an insulating resin, and the lead 34 is cut into a desired length. Through these steps, the hybrid integrated circuit device 30 as shown in FIG. 4 is completed.

[0061]

According to the present invention, the following effects can be obtained.

First, in the chip resistor 10 of the present invention, the electrode portion 12 is formed only on the surface of the insulating substrate 53 on which the resistor 11 is formed. Therefore, a chip resistor having a simplified structure can be obtained as compared with the conventional example.

Secondly, in the circuit device 20 and the hybrid integrated circuit device 30 of the present invention, the chip resistor 10 having the electrode portion 12 formed only on the surface of the insulating substrate 53 on which the resistor 11 is formed is mounted. There is. Therefore, the distance between the resistor 11 and the conductive pattern can be shortened.

Thirdly, in the circuit device 20 and the hybrid integrated circuit device 30 of the present invention, the brazing material connecting the chip resistor 10 and the conductive pattern has the lower surface of the electrode portion of the chip resistor 10 and the conductive pattern. Connecting. That is, unlike the conventional example, a fillet made of a brazing material is not formed on the side surface of the chip resistor. Therefore, the mounting area of the chip resistor 10 can be reduced, and the mounting density of the entire device can be improved.

Fourth, when solder cream is used as the brazing material, the electrode structure is also formed on the side surface of the chip resistor in the conventional structure. If the timing is misaligned, the solder on one side pulls the chip resistor, causing a chip nigga. This phenomenon is called the tombstone phenomenon. In the chip resistor of the present invention, since the electrode is not formed on the side surface portion, the tombstone phenomenon can be prevented from occurring.

Fifth, in the present invention, since the fillet is not formed, there is an advantage that the electric capacity of this portion can be reduced.

[Brief description of drawings]

FIG. 1 is a sectional view (A) and a sectional view (B) illustrating a chip resistor of the present invention.

FIG. 2 is a plan view (A) and a sectional view (B) illustrating a circuit device in which a chip resistor of the present invention is mounted.

FIG. 3 is a plan view (A) and a sectional view (B) illustrating a circuit device in which a chip resistor of the present invention is mounted.

FIG. 4 is a perspective view (A) and a sectional view (B) illustrating a hybrid integrated circuit device in which a chip resistor of the present invention is mounted.

FIG. 5 is a plan view (A) and a sectional view (B) illustrating a method for manufacturing a chip resistor according to the present invention.

FIG. 6 is a plan view (A) and a sectional view (B) illustrating a method for manufacturing a chip resistor according to the present invention.

FIG. 7 is a sectional view (A) and a sectional view (B) illustrating a method for mounting a chip resistor according to the present invention.

FIG. 8 is a sectional view (A) and a sectional view (B) illustrating a conventional chip resistor and a mounting method thereof.

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Claims (7)

[Claims] 1. A chip resistor having an insulating substrate, a resistor formed on a surface of the insulating substrate, and electrode portions formed on both ends of the resistor, wherein the electrode portion is formed on the insulating substrate. A chip resistor characterized in that it is formed only on the surface of. 2. A conductive pattern, a chip resistor mounted on the conductive pattern via a brazing material, and an insulating resin which exposes the back surface of the conductive pattern and seals the conductive pattern and the chip resistor. A circuit device having: a chip device, wherein the chip resistor is mounted on the conductive pattern with a surface on which a resistor and an electrode portion are formed as a lower surface. 3. The circuit device according to claim 2, wherein the brazing material joins the electrode portion and the conductive pattern. 4. The circuit device according to claim 2, wherein the insulating resin adheres to the conductive pattern and the chip resistor to secure connection strength between the chip resistor and the conductive pattern. 5. A substrate, a conductive pattern formed on the surface of the substrate, a chip resistor mounted on the conductive pattern via a brazing material, and an insulating resin for sealing the chip resistor. In the hybrid integrated circuit device having the above-mentioned, the chip resistor is mounted on the conductive pattern with the surface on which the resistor and the electrode portion are formed as the lower surface. 6. The hybrid integrated circuit device according to claim 5, wherein the brazing material joins the electrode portion and the conductive pattern. 7. The connection strength between the chip resistor and the conductive pattern is secured by adhering the insulating resin to the substrate, the conductive pattern and the chip resistor. Hybrid integrated circuit device.