JP2004198747A - Liquid crystal display - Google Patents

Abstract

An object of the present invention is to easily and surely detect a defective product even when a slight shift occurs in electrical characteristics (voltage-current characteristics) of a TFT.
Kind Code: A1 A drive voltage application time, which is a voltage application time of a gate control signal for normal operation, and a voltage application time of a gate control signal for electrical characteristic inspection, for each TFT 25 provided on a liquid crystal panel 20. Since an image is displayed by switching a certain drive voltage application time (for example, 50 μsec and 30 μsec, respectively), when the electrical characteristics of the TFT 25 are defective, the brightness of the display image is changed every predetermined switching time (n-field period). Defective products due to slight shifts in the electrical characteristics of the TFT 25 can be easily and reliably confirmed, and it takes time with a large-scale device to operate both the device to be inspected and the device to be compared as a conventional device. This eliminates the need to compare the brightness of the displayed image.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a liquid crystal display device such as an active matrix type liquid crystal display device provided with an electric characteristic detecting circuit for detecting a deviation of electric characteristics such as voltage-current characteristics of a TFT (Thin Film Transistor).
[0002]
[Prior art]
The active matrix method, in which a plurality of pixel electrodes are arranged in a matrix on an insulating substrate and a video signal is independently applied to each pixel electrode, is used for display on a liquid crystal television, a mobile phone, a terminal display device of a computer, or the like. It has been put to practical use in equipment.
[0003]
FIG. 11 is a block diagram showing an example of a configuration of a main part of a conventional active matrix type liquid crystal display device.
[0004]
An active matrix liquid crystal display device 100 shown in FIG. 11 includes a liquid crystal display panel 200 provided with a display screen, a source driver 300 serving as a video signal line driving unit for supplying a video signal to the liquid crystal display panel 200, And a control IC 500 that supplies a synchronization control signal to the source driver 300 and the gate driver 400. .
[0005]
The control IC 500 includes a serial-parallel conversion circuit 501 to which a serial signal SI is input, and a CLG generation circuit 502 that generates a gate clock signal CLG according to a control signal from the serial-parallel conversion circuit 501. , Clock signal CLK and transfer signal TRS to source driver 300, and output start pulse signal SPG and gate clock signal CLG to gate driver 400.
[0006]
The source driver 300 receives an input sampling signal SP and a clock signal CLK from the control IC 500, synchronizes the input sampling signal SP with the clock signal CLK, and sequentially outputs sequentially delayed sampling signals; An RGB signal line 302 to which an RGB signal as each color component of a video signal is input via an RGB signal input terminal Sin, and a color signal of an RGB signal from the RGB signal line 302 based on a sampling signal from an H shift register 301 are selected. , A plurality of sampling switches (switches) 303 for sequentially outputting the respective color signals of the RGB signals by repeating the on / off operation, and each of the color signals of the RGB signals supplied from the RGB signal line 302 via the sampling SW 303 once. Multiple samplers to keep A plurality of transfer SWs (switches) 305 for simultaneously transferring the respective color signals of the RGB signals held in the respective sampling capacitors 304 by being turned on when a transfer signal TRS from the control IC 500 is applied; A plurality of transfer capacitors 306 for temporarily holding the respective color signals of the RGB signals transferred from the respective sampling capacitors 304 via the respective transfer SWs 305, and a plurality of the respective color signals of the RGB signals held in the respective transfer capacitors 306 by amplifying the respective signals. And a plurality of operational amplifiers 307 for outputting the video signal lines 204 respectively.
[0007]
Here, the sampling capacitor 304 and the transfer capacitor 306 are respectively connected between the output terminals of the sampling SW 303 and the transfer SW 305 and the ground (GND), and the respective color signals of the RGB signals are respectively supplied to the non-inverting input terminal ( +), And the inverted input terminal (−) and the output terminal of the operational amplifier 307 are short-circuited. The output terminal of each operational amplifier 307 is connected to each video signal line 204.
[0008]
The gate driver 400 synchronizes the input start pulse signal SPG from the control IC 500 with the gate clock signal CLG output from the control IC 500, and sequentially outputs a gate control signal line selection signal sequentially delayed. And a plurality of output buffers 402 to which a gate voltage VGH1 of an external supply voltage is applied via an external supply voltage terminal VGH. The output buffer 402 is an inverter circuit including a P-type MOS transistor 402a and an N-type MOS transistor 402b. The drain terminal and the gate terminal of P-type MOS transistor 402a are respectively connected to the drain terminal and the gate terminal of N-type MOS transistor 402b. Each drain terminal of the P-type MOS transistor 402a and the N-type MOS transistor 402b becomes an output terminal of the output buffer 402 and is connected to the gate control signal line 203. Each gate terminal of the P-type MOS transistor 402a and the N-type MOS transistor 402b is an input terminal of the output buffer 402. A gate control signal line selection signal output from the V shift register 401 is input to an input terminal of the output buffer 402. Source terminals of the P-type MOS transistor 402a and the N-type MOS transistor 402b are connected to the external supply voltage terminal VGH and the ground (GND), respectively.
[0009]
The output buffer 402 performs an on / off operation in response to a gate control signal line selection signal from the V shift register 401, and outputs a gate voltage VGH1 as a gate control signal to the gate control signal line 203 from an output terminal. The output buffer 402 is provided for each gate control signal line 203.
[0010]
The liquid crystal display panel 200 includes a transparent insulating substrate (hereinafter, referred to as an active matrix substrate) such as a glass plate having a plurality of pixel electrodes 201 arranged in a matrix, and is disposed to face the active matrix substrate. A transparent insulating substrate such as a glass plate provided with a film-like common (counter) electrode 202 (hereinafter, referred to as a counter substrate), and a liquid crystal between the active matrix substrate and the counter substrate. The layer LC is sandwiched.
[0011]
The active matrix substrate includes a plurality of gate control signal lines 203 (gate signal lines) functioning as scanning lines, and a plurality of video signal lines 204 (source signal lines) orthogonal to these gate control signal lines 203 and functioning as signal lines. ). A pixel electrode driving element 205 is disposed near a position orthogonal to each gate control signal line 203 and each video signal line 204. The gate terminal and the source terminal of the pixel electrode driving element 205 are connected to the gate control signal line 203 and the video signal line 204, respectively. The drain terminal which is the driving terminal of the pixel electrode driving element 205 is connected to the pixel electrode 201 is connected. Each picture element electrode 201 is provided in a region surrounded by each gate control signal line 203 and video signal line 204.
[0012]
As the pixel electrode driving element (hereinafter, referred to as TFT) 205, a thin film transistor (TFT: Thin Film Transistor) formed of amorphous silicon, an MIM (Metal Insulator Metal) element, or the like is used.
[0013]
In the liquid crystal display device illustrated in FIG. 11, with such a configuration, first, an RGB signal, which is each color component of a video signal, is input to an RGB signal line 302 provided in a source driver 300 via an RGB signal input terminal Sin. Is done. At the same time, the H shift register 301 receives the input sampling signal SP and the clock signal CLK, synchronizes the input sampling signal SP with the clock signal CLK, and outputs sequentially delayed sampling signals to the sampling SW (switch) 303. . At this time, each color signal of the video signal for one horizontal period on the RGB signal line 302 is sequentially sampled by each sampling SW 303 as a video signal to be displayed on the liquid crystal display panel 200, and each color component of this sampled video signal is The data is sequentially stored in the sampling capacitor 304.
[0014]
Next, before the sampling operation, each transfer SW 305 is turned on by the transfer signal TRS output from the control IC 500, and the video signal for one horizontal period is transmitted from each held sampling capacitor 304 to each transfer SW 305. The data is transferred to each transfer capacitor 306 via the respective transfer capacitors. Further, each video signal output voltage charged in each transfer capacitor 304 is amplified by each operational amplifier 307 and then transferred to each video signal line 204.
[0015]
On the other hand, the video signal for one horizontal period output to each video signal line 204 is given a predetermined gate control signal by a gate control signal sequentially output from the output buffer 402 of the gate driver 400 to each gate control signal line 203. A plurality of TFTs 205 in one horizontal line for one line (scanning) connected to the line 203 are simultaneously turned on, and each video signal voltage on the plurality of video signal lines 204 is applied to each pixel through the drain terminal of each TFT 205. The data is written to the electrodes 201 respectively.
[0016]
The output timing of the gate control signal output from the output buffer 402 of the gate driver 400 in this case will be described.
[0017]
FIG. 12 is a timing chart of each gate control signal output from each output buffer 402 of the gate driver 400 shown in FIG.
[0018]
As shown in FIG. 12, when the start pulse signal SPG output from the control IC 500 is input, the V shift register 401 of the gate driver 400 synchronizes with the gate clock signal CLG of a predetermined frequency output from the control IC 500. A gate control signal line selection signal is output to the output buffer 402, and a gate voltage VGH 1, which is a gate control signal, is output from the output buffer 402 to the gate control signal line 204 based on the gate control signal line selection signal. For example, for the gate control signal line 203 on the first line (first line) of the screen of the liquid crystal display panel 200, a gate control signal is output from the output buffer 402 corresponding to the gate control signal line 203 on the first line. The gate voltage VGH1 is output, and the first line of the screen of the liquid crystal display panel 200 is displayed by the gate control signal. Further, in synchronism with the gate clock signal CLG of the predetermined frequency, the output buffer corresponding to the gate control signal line 203 on the second line (second line) and the gate control signal line 203 on the second line A gate control signal is output from 402, and the second line of the screen of the liquid crystal display panel 200 is displayed by the gate control signal. The operation of outputting the gate control signal from the output buffer 402 is repeated at the cycle of the gate clock signal CLG of a predetermined frequency, and one screen in one vertical period is displayed. The gate voltage VGH1, which is a gate control signal output from the output buffer 402 to the gate control signal line 203, is VGH (HIGH) = 13V in a HIGH state, and VGH (LOW) = 0V (GND) in a LOW state.
[0019]
[Problems to be solved by the invention]
However, in the conventional liquid crystal display device 100, even when the period of the HIGH state of the gate voltage VGH1 is constant, if the electrical characteristics such as the voltage-current characteristics of the TFT 205 are defective, the signal level of the video signal is not accurate. May not be written to the picture element electrode 201 (insufficient charge).
[0020]
In the conventional method for testing the electrical characteristics of a TFT, in the liquid crystal display device 100, a video signal voltage applied to the liquid crystal layer LC is set to a fixed value in order to determine whether or not the pixel electrode 201 is insufficiently charged by the TFT. The luminance of the liquid crystal display device 100 to be inspected is determined based on the luminance of the liquid crystal display device 100 formed of TFTs having good electrical characteristics, and the luminance of the reference liquid crystal display device 100 and the luminance of the liquid crystal display device to be inspected are measured. By comparing the luminance of the TFT with 100, it is determined whether the TFT is good or defective.
[0021]
In this case, in order to compare with the liquid crystal display device 100 to be measured, the reference liquid crystal display device 100 formed of non-defective TFTs needs to display an image in order to confirm the luminance.
[0022]
This requires time to measure the luminance of the liquid crystal display device 100 to be inspected and the luminance of the reference liquid crystal display device 100 formed of non-defective TFTs to be compared, which is a major factor in reducing the processing speed. It has become. When comparing the reference liquid crystal display device 100 formed of non-defective TFTs with the liquid crystal display device 100 to be inspected, the size of the inspection device is increased and the non-defective TFTs formed of non-defective TFTs are used. In addition, a driving circuit for driving the liquid crystal display device 100 serving as a reference is also required, which leads to an increase in cost in testing the electrical characteristics of the TFT.
[0023]
In addition, after the liquid crystal display device 100 whose TFT electrical characteristics have been tested is shipped, the electrical characteristics of the TFT slightly shift due to static electricity or the like during the manufacturing process and transportation of various products using the liquid crystal display device 100. May be. In this case, according to the conventional method for testing the electrical characteristics of the TFT in the liquid crystal display device 100, if the electrical characteristics of the TFT are extremely shifted, it can be determined that the TFT is defective, but the electrical characteristics of the TFT are slightly reduced. If the shift is performed, it is difficult to determine that the product is defective, and the product may not be detected.
[0024]
In a conventional inspection method for judging the electrical characteristics of a TFT having the above-described problems, the present inventors examined the electrical characteristics of the TFT as follows.
[0025]
FIG. 13 is a timing chart of the video signal output voltage output from the operational amplifier 307 of the source driver 300 shown in FIG. 11, the gate voltage of the TFT synchronized with the gate clock signal CLG from the control IC 500, and the drain voltage.
[0026]
In FIG. 13, each signal waveform will be sequentially described.
[0027]
First, in the output signal waveform of the video signal output voltage from the operational amplifier 307 of the source driver 300, the period (a) of the video signal output voltage is the timing at which the video signal of the HIGH level voltage is written to the picture element electrode 201. The period (b) is a timing at which a video signal of a LOW level voltage is written to the pixel electrode 201.
[0028]
Further, the gate control signal output from the output buffer 402 of the gate driver 400 becomes a HIGH level voltage by the HIGH level voltage of the gate clock signals CLG (1) and (2), turning on the gate G of the TFT, and With the LOW level voltages of the clock signals CLG (1) and (2), the gate control signal output from the output buffer 402 of the gate driver 400 becomes a LOW level voltage, and turns off the gate G of the TFT. Here, the difference between the signal waveforms of the gate clock signals CLG (1) and (2) is that the HIGH level state period (ON period) is 50 μs and 30 μs, respectively.
[0029]
Next, the output signal waveform (a) of the drain D of the TFT shows the HIGH-level timing of the gate clock signal CLG (1) (the HIGH-level timing of the gate voltage) when the video signal output voltage is in the period (a). 5 shows a signal waveform when a video signal of a maximum voltage of 5 V output from the source driver 300 is written to the pixel electrode 201 via a normal TFT (non-defective product).
[0030]
Next, the output signal waveform (a ') of the drain D of the TFT indicates the HIGH-level timing of the gate clock signal CLG (2) (the HIGH-level timing of the gate voltage) when the video signal output voltage is in the period (a). 3) shows a signal waveform when a video signal having a maximum voltage of 5 V output from the source driver 300 is written to the pixel electrode 201 via a normal TFT (non-defective product).
[0031]
Next, the output signal waveform (b) of the drain D of the TFT indicates the HIGH-level timing of the gate clock signal CLG (1) (the HIGH-level timing of the gate voltage) when the video signal output voltage is in the period (b). 3 shows a signal waveform when a video signal of a minimum voltage of 1 V output from the source driver 300 is written to the pixel electrode 201 via a normal TFT (good product).
[0032]
Next, the output signal waveform (b ′) of the drain D of the TFT indicates the HIGH-level timing of the gate clock signal CLG (2) (the HIGH-level timing of the gate voltage) when the video signal output voltage is in the period (b). 3) shows a signal waveform when a video signal of a minimum voltage of 1 V output from the source driver 300 is written to the pixel electrode 201 via a normal TFT (non-defective product).
[0033]
Next, the output signal waveform (c) of the drain D of the TFT indicates the HIGH-level timing of the gate clock signal CLG (1) (the HIGH-level timing of the gate voltage) when the video signal output voltage is in the period (a). 5 shows a signal waveform when a video signal of a maximum voltage of 5 V output from the source driver 300 is written to the pixel electrode 201 via an abnormal TFT (defective product) whose electric characteristics are shifted.
[0034]
Next, the output signal waveform (c ′) of the drain D of the TFT indicates the HIGH-level timing of the gate clock signal CLG (2) (the HIGH-level timing of the gate voltage) when the video signal output voltage is in the period (a). 3) shows a signal waveform when a video signal having a maximum voltage of 5 V output from the source driver 300 is written to the pixel electrode 201 via an abnormal TFT (defective product) whose electrical characteristics are shifted.
[0035]
Here, the output signal waveform (c) of the drain D of the TFT indicates that a 4.8 V video signal is written to the pixel electrode 201 at the HIGH level timing of the gate clock signal CLG (1). The output signal waveform (c ′) of the drain D indicates that the 4.3 V video signal is written to the pixel electrode 201 at the HIGH level timing of the gate clock signal CLG (2).
[0036]
Next, the output signal waveform (d) of the drain D of the TFT shows the HIGH-level timing of the gate clock signal CLG (1) (the HIGH-level timing of the gate voltage) when the video signal output voltage is in the period (b). 3 shows a signal waveform when a video signal of a minimum voltage of 1 V output from the source driver 300 is written to the pixel electrode 201 via an abnormal TFT (defective product) having a deviated electrical characteristic.
[0037]
Next, the output signal waveform (d ′) of the drain D of the TFT indicates the HIGH-level timing of the gate clock signal CLG (2) (the HIGH-level timing of the gate voltage) when the video signal output voltage is in the period (b). 3) shows a signal waveform when a video signal of a minimum voltage of 1 V output from the source driver 300 is written to the picture element electrode 201 via an abnormal TFT (defective product) whose electric characteristics are shifted.
[0038]
FIG. 14 is a graph showing the relationship between the gate-source voltage VGS of the TFT and the source-drain current IDS.
[0039]
In FIG. 14, the solid characteristic curve shows a normal VGS-IDS characteristic of a non-defective TFT (TFTa), and the dotted characteristic curve shows an abnormal VGS-IDS characteristic of a defective TFT (TFTb).
[0040]
As shown in FIG. 14, when the gate potential (gate voltage VGH1 as a gate control signal) of a non-defective TFT (TFTa) shown by a solid characteristic curve is 13V and the maximum drain potential by a video signal is 5V, the gate-source The inter-voltage VGS is 13 V−5 V = 8 V, the IDS current is IDSa (the gate-source voltage VGS is 8 V, indicating the IDS current corresponding to the point A8 on the solid characteristic curve), and the TFTa is turned on. Within the period of the state, the current exceeds the minimum IDS current value IDSM (shown by a dashed line) at which the TFTa can sufficiently charge (write) the pixel electrode 201. The case where the IDS current becomes IDSa indicates the case of the output signal waveform (a) of the drain D of the TFT shown in FIG. 13, and the video signal of 5V output from the source driver 300 during the ON state of the TFTa. Is written to the picture element electrode 201.
[0041]
Even when the period of the HIGH level state of the gate control signal output from the output buffer 402 of the gate driver 400 (the gate-on period of the TFTa) is 30 μs, as shown in the output signal waveform (a ′) of the drain D of the TFT in FIG. Then, a video signal of a voltage of 5 V output from the source driver 300 can be written to the pixel electrode 201.
[0042]
The VGS-IDS characteristic of a non-defective TFT (TFTa) is shown by a solid-line characteristic curve in FIG. 14, and the gate potential (gate voltage VGH1 of the gate control signal) of TFTa is 13V and the minimum drain potential by the video signal is 1V. Then, the gate-source voltage VGS is 13V-1V = 12V, and the IDS current is IDSc (the gate-source voltage VGS is 12V, which corresponds to the IDS current corresponding to the point A12 on the solid characteristic curve. ), Which exceeds the current value IDSa when the video signal of the voltage 5V is written. The case where the IDS current becomes IDSc indicates the case of the output signal waveform (b) of the drain D of the TFT shown in FIG. 13, and the TFTa sufficiently charges (writes) the pixel electrode 201 during the ON state of the TFTa. The potential is higher than the minimum possible IDS current IDSM, and the same potential as the video signal of 1 V output from the source driver 300 is written to the pixel electrode 201 during the ON state of the TFTa.
[0043]
Even when the period of the HIGH level state of the gate control signal output from the output buffer 402 of the gate driver 400 (the gate-on period of the TFTa) is 30 μs, the output signal waveform (b ′) of the drain D of the TFT in FIG. Then, a video signal of a voltage of 1 V output from the source driver 300 can be written to the pixel electrode 201.
[0044]
Therefore, in the image displayed on the liquid crystal panel 200 of the active matrix type liquid crystal display device 100, a positive video signal and a negative video signal are alternately written to the pixel electrode 201 for each line, or After writing a predetermined signal to all the picture element electrodes 201 of the screen, in the next screen, the polarity of the video signal of the line on which the positive video signal is written and the polarity of the video signal of the line on which the negative video signal is written are changed. Each is inverted and written to the picture element electrode 201. Therefore, in the liquid crystal layer LC corresponding to the picture element electrode 201 connected to the non-defective TFT (TFTa), the gate clock signal CLG (1) or (2) The voltage of 5V-1V = 4Vp-p is applied even when the period (gate-on time) of the HIGH level state of the gate control signal is 50 μs or 30 μs at the HIGH level timing of FIG. An image can be faithfully reproduced with respect to the signal voltage.
[0045]
On the other hand, in the case of a defective TFT (TFTb) in which the VGS-IDS characteristics shown by the dotted characteristic curve in FIG. 14 are not normal, the gate potential of the TFTb (gate voltage VGH1 of the gate control signal) is set to 13V and the maximum by the video signal. Assuming that the drain potential is 5 V, the gate-source voltage VGS is 13 V-5 V = 8 V, and the IDS current is IDSb (gate-source voltage VGS is 8 V, which corresponds to IDS current corresponding to B8 on the dotted characteristic curve). During the ON state of the TFTb, the TFTb sets the minimum IDS current value IDSM that can sufficiently charge (write) the video signal of 5 V output from the source driver 300 to the pixel electrode 201. It will fall below. In this case, the output signal waveform (c) of the drain D of the TFT shown in FIG. 13 is shown, and the source driver 300 sends the waveform during the ON state (50 μs) of the TFTb (the HIGH level period of the gate clock signal CLG). Only a voltage (for example, 4.8 V in FIG. 13) lower than the output video signal of 5 V can be written to the pixel electrode 201.
[0046]
Even when the period of the HIGH level state of the gate control signal output from the output buffer 402 of the gate driver 400 (the gate-on period of the TFTb) is 30 μs, as shown in the output signal waveform (C ′) of the drain D of the TFT in FIG. In addition, only a voltage (for example, 4.3 V in FIG. 13) lower than the video signal of 5 V output from the source driver 300 can be written to the pixel electrode 201.
[0047]
The VGS-IDS characteristic of the defective TFT (TFTb) is shown by the dotted characteristic curve in FIG. 14, and the gate potential (gate voltage VGH1 of the gate control signal) of the TFTb is set to 13V and the minimum drain potential 1V due to the video signal. In this case, the gate-source voltage VGS is 13V-1V = 12V, and the IDS current is IDSd (the gate-source voltage VGS is 12V and the IDS current corresponds to the point B12 on the dotted characteristic curve. ), And exceeds the minimum IDS current IDSM at which the TFTb can sufficiently charge the picture element electrode 201 with the video signal of 5V output from the source driver 300 during the ON state of the TFTb. For this reason, when the video signal of voltage 1V is output from the source driver 300 and the IDS current becomes IDSd, the same potential as the video signal of voltage 1V output from the source driver 300 during the ON state (50 μs) of the TFTb. Is sufficiently written in the pixel electrode 201.
[0048]
Even when the period of the HIGH level state of the gate control signal output from the output buffer 402 of the gate driver 400 (the gate-on period of the TFTa) is 30 μs, the gate potential (gate voltage VGH1 of the gate control signal) of the TFTb is set to 13V and the video signal. , The gate-source voltage VGS is 13V-1V = 12V, and the IDS current is IDSd (the gate-source voltage VGS is 12V and the IDS corresponding to the point B12 on the dotted characteristic curve is B12. 13 shows the current), and as shown in the output signal waveform (d ′) of the drain D of the TFT in FIG. 13, the video signal of the voltage 1 V output from the source driver 300 can be written to the pixel electrode 201. it can.
[0049]
As described above, in the liquid crystal display device 100 illustrated in FIG. 11, when the liquid crystal panel 200 includes the TFT 205 whose VGS-IDS characteristics are shifted, the negative video signal output voltage output from the source driver 300 is output to the liquid crystal panel 200. Although it is possible to normally write to the pixel electrode 201 via the TFT 205, the positive video signal output voltage output from the source driver 300 is normally written to the pixel electrode 201 via the TFT 205 of the liquid crystal panel 200. Can not do it. Therefore, an image displayed on the liquid crystal panel 200 of the liquid crystal display device 100 may not be able to be faithfully reproduced with respect to a video signal input to the source driver 300 of the liquid crystal display device 100.
[0050]
In the case of the liquid crystal display device 100 described above, the video signal output voltage applied to the liquid crystal layer LC corresponding to each pixel electrode 201 connected to each TFT 205 of the liquid crystal panel 200 has a positive polarity as an image for each line. After the video signal and the negative video signal are alternately applied, or after a predetermined signal is applied to the entire screen, in the next screen, the line to which the positive video signal is applied and the negative video signal The polarity of the video signal is inverted with respect to the line to which the signal is applied.
[0051]
Therefore, in the liquid crystal layer LC corresponding to the pixel electrode 201 connected to the defective TFT (TFTb), the gate clock signal CLG ( When the HIGH-level period (gate-on time) of the gate control signal is 50 μs or 30 μs at the high-level timing of 1) or (2), 4.8V-1V = 3.8Vp-p or 4 respectively. A video signal voltage of .3V-1V = 3.3Vp-p is applied.
[0052]
Therefore, the applied voltage to the liquid crystal layer LC of the liquid crystal panel 200 having the defective TFT (TFTb) is the applied voltage (5V-1V = 4Vp-p) to the liquid crystal layer LC of the liquid crystal panel 200 having the non-defective TFT (TFTa). ), And the image on the entire display screen of the liquid crystal panel 200 becomes lighter (in the case of normally white).
[0053]
As described above, when inspecting the liquid crystal display device 100 provided with the liquid crystal panel 200 having the defective TFT (TFTb), the gate control signal of the non-defective TFT (TFTa) does not change in the ON state in the ON state. By shortening the period (gate-on time) in the HIGH level state, the screen becomes thinner when the defective TFT (TFTb) is in the on state, and the brightness of the image on the display screen of the liquid crystal panel 200 is determined. Thereby, the non-defective or defective product of the liquid crystal display device 100 can be determined.
[0054]
The present invention solves such a problem, and an object of the present invention is to enable easy and reliable detection of a defective product even when there is a slight shift in the electrical characteristics (voltage-current characteristics) of the TFT. It is to provide a liquid crystal display device.
[0055]
[Means for Solving the Problems]
In the liquid crystal display device of the present invention, a plurality of picture element electrodes are provided near each intersection of a plurality of video signal lines and a plurality of control signal lines, and the drive timing of each picture element electrode driving element by a control signal In a liquid crystal display device which supplies an image signal to each picture element electrode for each display to display an image, a voltage application time of the control signal and a control signal for electrical characteristic inspection are applied to each picture element electrode driving element. And an image display control means for enabling image display by switching between the voltage application time and the voltage application time, thereby achieving the above object.
[0056]
Further, preferably, in the liquid crystal display device of the present invention, the image display control means,
Video signal line driving means for sequentially selecting video signal lines from a plurality of video signal lines and supplying a video signal, and control signal line driving means for sequentially selecting control signal lines from a plurality of control signal lines and supplying a control signal And a drive voltage application time for enabling switching between the voltage application time of the control signal of each of the picture element electrode driving elements supplied to the control signal line driving means and the voltage application time of the control signal for electrical characteristic inspection. Switching means.
[0057]
Still preferably, in a liquid crystal display device according to the present invention, the voltage application time of the control signal for electrical characteristic inspection is a voltage-current characteristic of a pixel electrode driving element determined to be normal, and a pixel electrode determined to be defective. It is set based on the voltage-current characteristics of the driving element.
[0058]
Still preferably, in a liquid crystal display device according to the present invention, the drive voltage application time switching means includes a switching timing control signal generating means for generating a switching timing control signal, and each of the picture element electrodes based on the switching timing control signal. A drive voltage application time setting means for alternately switching between the voltage application time of the control signal of the drive element and the voltage application time of the control signal for electrical characteristic inspection is provided.
[0059]
Still preferably, in a liquid crystal display device according to the present invention, the drive voltage application time setting unit has a switching circuit connected in series to one of the two resistors connected in parallel, and A circuit that controls the switching circuit in accordance with the signal to generate a voltage application time of the control signal of each of the picture element electrode driving elements and a voltage application time of the control signal for electrical characteristic inspection. I have.
[0060]
Still preferably, in the liquid crystal display device according to the present invention, the switching timing control signal generating means switches the switching timing control signal level at least every n (n is a natural number) field period or every n frame periods of screen display.
[0061]
More preferably, in the liquid crystal display device of the present invention, the switching timing control signal generating means switches the switching timing control signal level within one field of a screen display and at the same display line position for each field. .
[0062]
Still preferably, in a liquid crystal display device according to the present invention, the number of switching lines within one field of the screen display is one or more.
[0063]
Still preferably, in a liquid crystal display device according to the present invention, the switching direction of the switching timing control signal level at the same display line position is reversed every m (m is a natural number) fields.
[0064]
Still preferably, in a liquid crystal display device of the present invention, at least one of a voltage application time of the control signal and a set value of a voltage application time of the control signal for electrical characteristic inspection is variable.
[0065]
According to the above configuration, for each picture element electrode driving element, an image is displayed by switching between the voltage application time of the control signal for normal operation and the voltage application time of the control signal for electrical characteristic inspection. In the case of (1), it is possible to easily and surely confirm a defective product due to a slight shift (shift) of the electrical characteristics by changing the brightness of the displayed image according to the switching time or the switching position. It is no longer necessary to operate the apparatus and the reference apparatus to be compared together and take a long time to perform luminance comparison on a large-scale apparatus.
[0066]
The detection of the liquid crystal display device including the pixel electrode driving element having the deviated electrical characteristics is performed by changing the voltage application time of the control signal for normal operation (the driving voltage application time of the pixel electrode driving element) in the middle of the image display period. Is switched to the voltage application time of the control signal for dynamic characteristic inspection, and the determination is made based on the change in the luminance of the display screen. Therefore, unlike the conventional case, the luminance is not compared with a non-defective liquid crystal display device. There is no need to measure the brightness of the display screen. For this reason, the inspection work of the electrical characteristics of the pixel electrode driving element is simplified, and the operation efficiency is improved.
[0067]
In addition, the voltage application time of the control signal for normal operation and the voltage application time of the control signal for electrical characteristic inspection (two types of drive voltage application times) output to the control signal line are, for example, 50 μsec per frame. Since switching can be performed between 30 μsec, in a liquid crystal display device in which the electric characteristics of the pixel electrode driving elements are shifted, the display screen looks like flicker, and it is easy to determine the quality of the liquid crystal display device by checking the flicker. And it can be performed reliably.
[0068]
Further, the voltage application time of the control signal for normal operation and the voltage application time of the control signal for electrical characteristic inspection (two types of drive voltage application times) output to the control signal line are, for example, 50 μsec and 30 μsec in the middle of one screen. In a liquid crystal display device in which the electrical characteristics of the pixel electrode driving elements are shifted, it is easy and reliable to judge the quality of the electrical characteristics of the pixel electrode driving elements based on the luminance difference between the upper and lower portions of the screen. In addition, a defective liquid crystal display device can be reliably detected in a shorter time than the method of switching the drive voltage (control signal voltage) within the display period.
[0069]
Furthermore, the voltage application time of the control signal for normal operation and the voltage application time of the control signal for electrical characteristic inspection (two types of drive voltage application times) output to the control signal line are set to 50 μsec and 30 μsec, for example, in the middle of one screen. In addition to switching between 50 μsec and 30 μsec during the display period, the direction of switching between 50 μsec and 30 μsec is reversed, so that the pixel electrode driving element Even when there is a slight deviation in the electrical characteristics, it is possible to easily and reliably determine the quality of the liquid crystal display device.
[0070]
Furthermore, the voltage application time of the control signal for normal operation and the voltage application time of the control signal for electrical characteristic inspection (two types of drive voltage application times) are determined for each predetermined line (for example, three lines) on the display screen. , 50 μsec and 30 μsec, the brightness of the display changes every predetermined line within one screen in a liquid crystal display device in which the electric characteristics of the picture element electrode driving element are shifted, which is a horizontal stripe. It appears as a pattern, and the quality of the liquid crystal display device can be easily and reliably determined simply by performing a check test. Further, in this case, even when the electrical characteristics of the pixel electrode driving element are shifted only in a part of the display screen, the portion where the electrical characteristics are shifted appears as a striped pattern. It is possible to easily and reliably determine the quality of a part of the display screen of the liquid crystal display device in which the electric characteristics of the electrode driving elements are shifted.
[0071]
Further, the voltage application time of the control signal for normal operation and the voltage application time of the control signal for electrical characteristic inspection (two types of drive voltage application times) for each predetermined line (for example, three lines) are, for example, 50 μsec and 30 μsec. In addition to the switching between the switching directions, the switching direction (switching order) for switching between, for example, 50 μsec and 30 μsec is reversed in the display period, so that only a small part of the display screen (a few lines) In this case, it is possible to easily and surely detect the deviation of the electrical characteristics of the pixel electrode driving element, and it is possible to easily and surely determine the quality of the liquid crystal display device.
[0072]
Further, by changing at least one of the voltage application time of the control signal for normal operation and the voltage application time (two types of drive voltage application times) of the control signal for electrical characteristic inspection, the display luminance difference can be made clearer. Thus, the detection level of the defective electrical characteristic of the pixel electrode driving element can be changed satisfactorily, and the quality of the liquid crystal display device can be easily and reliably determined.
[0073]
Further, in addition to a normal driving method, a switching timing control signal generating means and a driving voltage switching means capable of controlling the switching timing of the driving voltage are incorporated in, for example, a control IC incorporating a control circuit of the liquid crystal display device. This makes it possible to easily and reliably detect the electrical characteristics of the picture element electrode driving element after being incorporated in a product as a liquid crystal display device, and to easily and reliably determine the quality of the liquid crystal display device.
[0074]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
FIG. 1 is a block diagram illustrating a configuration of a main part of the liquid crystal display device according to the first embodiment of the present invention.
[0075]
The liquid crystal display device 10 of the present invention shown in FIG. 1 includes a liquid crystal panel 20 as an image display means and an image for supplying one color signal of a video signal by sequentially selecting one video signal line 24 from a plurality of video signal lines 24. A source driver 30 serving as a signal line driving unit, a gate driver 40 serving as a control signal line driving unit that sequentially selects one gate control signal line 23 from a plurality of gate control signal lines 23 and supplies a gate control signal; It has a control IC 11 which is a control circuit including timing control signal generation means, and a drive voltage application time switching circuit 12 which is drive voltage application time setting means.
[0076]
The control IC 11 has a serial-parallel conversion circuit 51 to which a serial signal SI is input, and a CLG generation circuit 52 that generates a gate clock signal CLG according to a control signal from the serial-parallel conversion circuit 51. , The clock signal CLK and the transfer signal TRS to the source driver 30, the inverted pulse signal RP1 and the gate clock signal CLG to the drive voltage application time switching circuit 12, and the start pulse signal SPG to the gate driver 40. The serial / parallel conversion circuit 51 includes switching timing control signal generating means, and the switching timing control signal generating means generates an inverted pulse signal RP1 as a switching timing control signal.
[0077]
The drive voltage application time switching circuit 12 includes a monostable multivibrator 13 to which a gate clock signal CLG from the control IC 11 is input. The monostable multivibrator 13 has a High time from the rise of the gate clock signal CLG. Is connected to a CR circuit composed of a capacitor C1, resistors R1 and R2, and a control switch 14. The control switch 14 performs an on / off operation based on the inverted pulse signal RP1 from the control IC 11. The drive voltage application time switching circuit 12 outputs to the gate driver 40 a gate clock signal CLG in which the High time from the rise is set to a predetermined value.
[0078]
The source driver 30 receives an input sampling signal SP and a clock signal CLK from the control IC 11, synchronizes the input sampling signal SP with the clock signal CLK, and sequentially outputs a sequentially delayed sampling signal; An RGB signal line 32 to which an RGB signal, which is each color component of a video signal, is input via an RGB signal input terminal Sin, and each color signal of an RGB signal from the RGB signal line 32 is selected by a sampling signal from the H shift register 31. A plurality of sampling SWs (switches) 33 for sequentially outputting the respective color signals of the RGB signals by repeating the on / off operation, and once each color signal of the RGB signal supplied from the RGB signal line 32 via the sampling SW 33 Holding a plurality of sampling capacitors 34 When a transfer signal TRS from the control IC 11 is applied, a plurality of transfer switches (switches) 35 for simultaneously transferring the respective color signals of the RGB signals held in the respective sampling capacitors 34 and the transfer SWs 35 are turned on. A plurality of transfer capacitors 36 that temporarily hold the respective color signals of the RGB signals transferred from the respective sampling capacitors 34 via the respective sampling capacitors 34, and a plurality of video signal lines by amplifying the respective color signals of the RGB signals held by the respective transfer capacitors 36. 24, and a plurality of operational amplifiers 37 that output the respective operational amplifiers.
[0079]
Here, the sampling capacitor 34 and the transfer capacitor 36 are respectively connected between the output terminals of the sampling SW 33 and the transfer SW 35 and the ground (GND), and the respective color signals of the RGB signals are supplied to the non-inverting input terminal ( +), And the inverted input terminal (−) and the output terminal of the operational amplifier 307 are short-circuited. The output terminal of each operational amplifier 37 is connected to each video signal line 24.
[0080]
The gate driver 40 synchronizes the input start pulse signal SPG from the control IC 11 with the gate clock signal CLG output from the control IC 11, and sequentially outputs a gate control signal line selection signal that is sequentially delayed. And a plurality of output buffers 42 to which a gate voltage VGH of an external supply voltage is applied via an external supply voltage terminal. The output buffer 42 is, for example, an inverter circuit including a P-type MOS transistor 42a and an N-type MOS transistor 42b. The drain terminal and the gate terminal of the P-type MOS transistor 42a are respectively connected to the drain terminal and the gate terminal of the N-type MOS transistor 42b. Each drain terminal of the P-type MOS transistor 42a and the N-type MOS transistor 42b becomes an output terminal of the output buffer 42 and is connected to the gate control signal line 23. Each gate terminal of the P-type MOS transistor 42a and the N-type MOS transistor 42b becomes an input terminal of the output buffer 42. A gate control signal line selection signal output from the V shift register 41 is input to an input terminal of the output buffer 42. The source terminals of the P-type MOS transistor 42a and the N-type MOS transistor 42b are connected to an external supply voltage terminal (terminal to which the gate voltage VGH is input) and a ground (GND), respectively.
[0081]
The output buffer 42 performs an on / off operation in response to a gate control signal line selection signal from the V shift register 41, and outputs a gate voltage VGH, which is a gate control signal, to the gate control signal line 23 from an output terminal. The output buffer 42 is provided for each gate control signal line 23.
[0082]
The liquid crystal display panel 20 is provided with a transparent insulating substrate (hereinafter, referred to as an active matrix substrate) such as a glass plate having a plurality of picture element electrodes 21 arranged in a matrix, and opposed to the active matrix substrate. A transparent insulating substrate (hereinafter, referred to as a counter substrate) such as a glass plate provided with a film-like common (counter) electrode 22. A liquid crystal is provided between the active matrix substrate and the counter substrate. The layer LC is sandwiched.
[0083]
The active matrix substrate includes a plurality of gate control signal lines 23 (gate signal lines) functioning as scanning lines, and a plurality of video signal lines 24 (source signal lines) orthogonal to these gate control signal lines 23 and functioning as signal lines. ). A pixel electrode driving element 25 is arranged near a position orthogonal to each gate control signal line 23 and each video signal line 24. The gate terminal and the source terminal of the pixel electrode driving element 25 are connected to the gate control signal line 23 and the video signal line 24, respectively, and the drain terminal which is the driving terminal of the pixel electrode driving element 25 is connected to the pixel electrode 21. Each picture element electrode 21 is provided in a region surrounded by each gate control signal line 23 and video signal line 24.
[0084]
As the pixel electrode driving element (hereinafter, referred to as TFT) 25, a thin film transistor (TFT: Thin Film Transistor) formed of amorphous silicon, an MIM (Metal Insulator Metal) element, or the like is used.
[0085]
Further, in the liquid crystal display device 10 shown in FIG. 1, a driving voltage application time switching means is constituted by a control IC 11 and a driving voltage application time switching circuit 12, and the driving voltage application time switching means outputs the control voltage from the control IC 11. A drive voltage application time (gate-on period), which is a voltage application time of a gate control signal for normal operation of the TFT 25 supplied to the gate driver 40 based on the inverted pulse signal RP1 being a switching timing control signal, and an electrical characteristic test The drive voltage application time (gate-on period), which is the voltage application time of the gate control signal for use, can be switched at predetermined time intervals. The gate-on period corresponds to a period in which the gate control signal is in a HIGH level state.
[0086]
Further, the driving voltage application time switching means, the source driver 30 and the gate driver 40 constitute an image display control means. The image display control means applies a drive voltage application time (gate-on period) of a gate control signal for normal operation to the TFT 25 serving as each pixel electrode drive element in the liquid crystal panel 20 and a gate control for electrical characteristic inspection. The driving voltage application time (gate-on period) of the signal is switched at predetermined time intervals, and the gate control signal whose gate-on period is switched at predetermined time intervals is transmitted to the liquid crystal corresponding to each pixel electrode 21 of the liquid crystal panel 20. An image is displayed by applying to the layer LC. Here, the predetermined time interval is a time interval that can be visually confirmed. For example, the predetermined time interval is an n-field period of screen display (or an n-frame period: n is a natural number).
[0087]
The serial / parallel conversion circuit 51 of the control IC 11 includes a switching timing control signal generating means, and the switching timing control signal generating means generates an inverted pulse signal RP1 as a switching timing control signal.
[0088]
The drive voltage application time switching circuit 12 is arranged before the gate driver 40 to which the gate clock signal CLG for switching the gate-on period of the gate control signal at predetermined time intervals is input.
[0089]
The gate clock signal CLG output from the CLG generation circuit 52 of the control IC 11 is input to the drive voltage application time switching circuit 12 composed of the monostable multivibrator 13, and the gate clock signal CLG is generated by the time constant of the capacitor C1 and the resistor R2. The High time (timing) from the rise of the gate clock signal CLG is set so that the period of the HIGH level state becomes, for example, 50 μs.
[0090]
The control switch 14 is connected in series with the resistor R1, and a resistor R2 is connected in parallel with a series circuit of the control switch 14 and the resistor R1.
[0091]
When the control switch 14 is turned on by the inverted pulse signal RP1 output from the serial / parallel conversion circuit 51 of the control IC 11, a capacitor C1 connected to the monostable multivibrator 13, resistors R1 and R2, and a CR The time constant of the circuit is the product of the capacitor C1 and the resistance component (R1 × R2) / (R1 + R2). In this case, the gate clock signal CLG is set so that the period of the HIGH level state of the gate clock signal CLG becomes, for example, 30 μs. Is set to a High time (timing) from the rising edge of.
[0092]
Further, when the HIGH level voltage of the inversion pulse signal RP1 inverted every n-field period is input to the control terminal and the control switch 14 is turned on, the drive voltage application time switching circuit 12 switches the resistances R1 and R2 of the CR circuit. In this case, the time constant of the CR circuit is the product of the capacitor C1 and the resistance component (R1 × R2) / (R1 + R2), and the CLG terminal for the gate driver 40 is in the HIGH level state of the gate clock signal CLG. The gate clock signal CLG whose period is set to, for example, 30 μs is applied.
[0093]
When the LOW level voltage of the inversion pulse signal RP1 inverted every n-field period is input to the control terminal of the control switch 14 and the control switch 14 is turned off, the drive voltage generation circuit 12 turns on the resistor R2 and the capacitor C1 of the CR circuit. Are connected in series. In this case, the time constant of the CR circuit is R2 × C1, and the gate clock signal CLG is connected to the CLG terminal for the gate driver 40 in such a manner that the period of the HIGH level state of the gate clock signal CLG becomes, for example, 50 μs. The signal CLG is applied.
[0094]
As described above, the control switch 14 is continuously turned on / off at a predetermined time interval based on the inversion pulse signal RP1, so that the TFT 25 applied to the gate (G: control terminal) of each TFT 25 of the liquid crystal panel 20. The drive voltage application time (gate-on period) of the gate control signal for normal operation and the drive voltage application time (gate-on period) of the gate control signal for electrical characteristic inspection can be switched at predetermined time intervals. Here, for example, the gate-on time for normal operation is 50 μs, and the gate-on time for electrical characteristic inspection is 30 μs. The gate-on time for electrical characteristic inspection is a VGS (gate-source voltage) -IDS (source-drain current) characteristic, which is a voltage-current characteristic of a normal TFT 25, and a voltage-current characteristic of a defective TFT 25. It is set based on VGS (gate-source voltage) -IDS (source-drain current) characteristics.
[0095]
Next, the operation of the liquid crystal display device 10 of the present invention will be described.
[0096]
FIG. 2 is a diagram showing a drive timing of the gate driver 40 shown in FIG. 1 and an application distribution of a gate voltage application time for each display screen.
[0097]
As shown in FIGS. 1 and 2, when the start pulse signal SPG is input to the V shift register 41 of the gate driver 40, the V shift register 41 outputs the start pulse signal SPG to the gate clock from the drive voltage application time switching circuit 12. A selection pulse (gate control signal line selection signal) sequentially delayed in synchronization with the signal CLG is sequentially output, and the gate control signal line selection signal, which is a selection pulse, first outputs the first line of the liquid crystal panel 20. The operation is sequentially performed from the output buffer circuit 42 for the gate control signal line 23 to the output buffer circuit 42 for the gate control signal line 23 of the last line, and the gate voltage VGH is sequentially applied to the plurality of gate control signal lines 23 to apply 1 Display the screen.
[0098]
In this case, for example, in FIG. 2, up to the (n-1) th screen after the (n-1) field period, the inverted pulse signal RP1 is a LOW level voltage, and the gate voltage application time is 50 μs. That is, the inverted pulse signal RP1 is controlled by the serial signal SI input to the serial / parallel conversion circuit 51 of the control IC 11, and the LOW level / HIGH level is changed for each predetermined screen (field) based on the vertical synchronization signal VD. Can be switched. Since the input serial signal SI is initially set to the LOW level by the switching timing control signal generating means in the serial / parallel conversion circuit 51, the inverted pulse signal RP1 is output from the control IC 11 as a LOW level voltage, and The control switch 14 of the voltage application time switching circuit 12 is turned off. Thereby, the gate voltage VGH for normal operation, in which the period of the HIGH level state is 50 μs, is applied to the gate control signal line 23 by the time constant of the CR circuit including the resistor R2 and the capacitor C1 connected to the monostable multivibrator 13. Is done.
[0099]
Therefore, up to the (n-1) th screen, the gate voltage VGH whose HIGH level period is set to 50 μs is applied to the gate (control terminal) of the TFT 25 via the gate control signal line 23.
[0100]
Next, when the serial signal SI is switched, the inverted pulse signal RP1 output from the control IC 11 becomes LOW between the (n-1) th screen and the nth screen after the (n-1) field period of the display screen. It switches from the level voltage to the HIGH level voltage. As a result, the control switch 14 is turned on, the resistors R1 and R2 of the CR circuit connected to the monostable multivibrator 13 are connected in parallel, and the time constant of the CR circuit is determined by the capacitor C1 and the resistance component (R1 × R2 ) / (R1 + R2). As a result, when the control switch 14 is turned on and the resistors R1 and R2 are connected in parallel, the gate clock signal CLG whose HIGH-level period is set to 30 μs is applied to the CLG terminal for the gate driver 40. As a result, the gate voltage VGH for electrical characteristic inspection in which the HIGH level state period is 30 μs is applied to the gate control signal line 23.
[0101]
Therefore, from the nth screen, the period of the HIGH level state of the gate voltage VGH applied to the gate (control terminal) of the TFT 25 via the gate control signal line 23 is switched from 50 μs to 30 μs.
[0102]
On the premise of the above, a method of determining whether the liquid crystal display device 10 to be inspected is a non-defective product or a defective product based on the electrical characteristics of the TFT will be described with reference to FIGS.
[0103]
The feature of the driving method of the liquid crystal display device 10 of the present invention is that the inverted pulse signal RP1 is switched to a high level voltage from the n-th screen of the display screen, whereby the HIGH of the gate clock signal CLG applied to the CLG terminal of the gate driver 40. That is, the period of the level state switches from 50 μs to 30 μs. As a result, the gate voltage VGH in which the HIGH level state period (gate ON period) is switched from 50 μs to 30 μs is output from the output buffer 42 to the gate control signal line 23.
[0104]
By using the liquid crystal display device 10 using this driving method, in the non-defective liquid crystal display device 10 having a TFT with normal electric characteristics, the video signal output voltage of FIG. The video signal of the positive polarity shown in the period (a) of FIG. Thus, the same signal voltage as the video signal output voltage output from the source driver 30 is written to the pixel electrode 21 within the gate-on period of a non-defective TFT (TFTa).
[0105]
In addition, even when the negative video signal shown in the video signal output voltage period (b) of FIG. 13 is written to the pixel electrode 21, the VGS voltage of the gate-source voltage of the TFTa is 13V-1V = 12V. Since the ISD current of the source-drain current flows more than when a video signal with a positive polarity voltage of 5 V is written, the video signal with a voltage of 1 V output from the source driver 30 during the ON state of the TFTa is generated. You can write enough.
[0106]
Next, from the n-th screen of the screen display, the application time of the gate voltage to the TFTa is 30 μs. Therefore, the positive video signal shown in the video signal output voltage period (a) in FIG. During writing to the pixel electrode 201, the same signal voltage as the video signal voltage output from the source driver 30 is applied to the pixel electrode 201 within the ON period of the TFTa, as in the (n-1) th screen of the screen display. .
[0107]
Further, even when the negative video signal shown in the video signal output voltage period (b) of FIG. 13 is written to the picture element electrode 21, the voltage of 1 V output from the source driver 30 during the ON state of the TFTa. Video signals can be sufficiently written.
[0108]
Therefore, the entire screen of the liquid crystal display device 10 has a uniform display screen.
[0109]
On the other hand, a case will be described in which the liquid crystal display device 10 has the liquid crystal panel 200 having the defective TFT (TFTb) whose electrical characteristics have shifted.
[0110]
Up to the (n-1) th screen of the screen display, when the positive-polarity video signal shown in the video signal output voltage period (a) of FIG. As shown in the output signal waveform (c), the voltage written to the picture element electrode 21 is 4.8V. However, when the negative video signal shown in the video signal output voltage period (b) of FIG. 13 is written to the pixel electrode 21, the output signal waveform (d) of the drain D of the TFT in FIG. In addition, the current value of the ISD current for writing the video signal of 1 V output from the source driver 30 to the pixel electrode 21 while the TFTb is in the ON state is sufficiently larger than the minimum writable IDS current value IDSM. . As a result, the voltage value written to the liquid crystal layer LC corresponding to the picture element electrode 21 to which the defective TFTb is connected is 4.8V-1V = 3.8Vp-p, which is 5V-, which is the voltage value to be originally written. 1V = 4 Vp-p, and the image becomes slightly thinner up to the (n-1) screen of the display screen of the liquid crystal panel 20 than in the case where a potential of 4 Vp-p is written.
[0111]
Next, in the nth screen and thereafter, when writing the positive-polarity video signal shown in the video signal output voltage period (a) of FIG. 13 to the picture element electrode 21, the output signal waveform of the drain D of the TFT in FIG. As shown in C ′), the voltage written to the pixel electrode 201 is 4.3 V, for example.
[0112]
Further, when the negative video signal shown in the video signal output voltage period (b) of FIG. 13 is written to the pixel electrode 21, the liquid crystal layer corresponding to the pixel electrode 21 to which the defective TFTb is connected. The voltage value written to the LC is 4.3V-1V = 3.3Vp-p, which is considerably lower than the voltage value 3.8Vp-p written from the first line to the (n-1) th line.
[0113]
As a result, in the liquid crystal display device 10 provided with the liquid crystal panel 20 including the defective TFTb having a deviated electrical characteristic, the display screen is not displayed up to the (n-1) th screen and the nth screen and thereafter. In the liquid crystal display device 10 provided with a liquid crystal panel 20 made of a non-defective TFTa having normal electrical characteristics due to a difference in brightness, the (n-1) th screen display and the nth and subsequent screens are different. There is no difference in the brightness of the display screen.
[0114]
Therefore, the quality of the liquid crystal display device 10 can be easily and reliably determined by the difference in brightness of the display screen of the liquid crystal panel 20 based on the non-defective TFTa having normal electrical characteristics and the defective TFTb having deviated electrical characteristics. It can be carried out.
(Embodiment 2)
FIG. 3 is a block diagram illustrating a configuration of a main part of the liquid crystal display device according to the second embodiment of the present invention.
[0115]
The liquid crystal display device 10a of the present invention shown in FIG. 3 includes a liquid crystal panel 20 serving as an image display unit and an image for sequentially selecting one video signal line 24 from a plurality of video signal lines 24 and supplying each color signal of a video signal. A source driver 30 serving as a signal line driving unit, a gate driver 40 serving as a control signal line driving unit that sequentially selects one gate control signal line 23 from a plurality of gate control signal lines 23 and supplies a gate control signal, It has a control IC 11a which is a control circuit including a timing control signal generation means, and a drive voltage application time switching circuit 12 which is a drive voltage application time setting means.
[0116]
The control IC 11a includes a serial-parallel conversion circuit 51 to which the serial signal SI is input, a CLG generation circuit 52 that generates a gate clock signal CLG by a control signal from the serial-parallel conversion circuit 51, and a control signal from the serial-parallel conversion circuit 51. And an RP generation circuit 53 for generating an inverted pulse signal RP2 in response to the vertical synchronizing signal VD. The RP generating circuit 53 outputs an input sampling signal SP, a clock signal CLK and a transfer signal TRS to the source driver 30, and outputs an inverted pulse signal RP2 and a gate clock. The signal CLG is output to the drive voltage application time switching circuit 12, and the start pulse signal SPG is output to the gate driver 40.
[0117]
The drive voltage application time generation circuit 12, the liquid crystal panel 20, the source driver 30, and the gate driver 40 are the same as those of the liquid crystal display device 10 according to the first embodiment shown in FIG.
[0118]
Further, in the liquid crystal display device 10a shown in FIG. 3, a driving voltage application time switching means is constituted by a control IC 11a and a driving voltage application time switching circuit 12, and the driving voltage application time switching means outputs an output from the control IC 11a. A drive voltage application time (gate-on period) of a gate control signal for normal operation of the TFT 25 to be supplied to the gate driver 40 based on the inverted pulse signal RP2 which is a switching timing control signal, and a gate control signal for electrical characteristic inspection And the drive voltage application time (gate-on period) can be switched every frame period. The gate-on period corresponds to a period in which the gate control signal is in a HIGH level state.
[0119]
Further, the drive voltage application time switching means, the source driver 30 and the gate driver 40 constitute an image display control means. The image display control means controls the TFT 25 as each pixel electrode drive element for normal operation. The driving voltage application time (gate-on period) of the gate control signal and the driving voltage application time (gate-on period) of the gate control signal for electrical characteristic inspection are switched every frame period so that the gate-on period is one frame period. The gate control signal switched every time is applied to the liquid crystal layer LC corresponding to each pixel electrode 21 of the liquid crystal panel 20 to display an image.
[0120]
The control IC 11a has an RP generation circuit 53, and the serial / parallel conversion circuit 51 and the RP generation circuit 53 constitute a switching timing control signal generation unit. This switching timing control signal generating means generates an inverted pulse signal RP2 as a switching timing control signal.
[0121]
The RP generation circuit 53 receives the vertical synchronization signal VD and the control signal from the serial / parallel conversion circuit 51, and outputs an inverted pulse signal RP2 that is inverted every frame period. The inverted pulse signal RP2 is controlled by the serial signal SI input to the control IC 11a, and is output from the control IC 11a as a LOW level signal when a normal display is performed by the serial / parallel conversion circuit 51 in the control IC 11a.
[0122]
The drive voltage application time switching circuit 12 is configured before the gate driver 40 to which the gate clock signal CLG for switching the gate-on period of the gate control signal every frame period is input.
[0123]
The gate clock signal CLG output from the CLG generation circuit 52 of the control IC 11a is input to the drive voltage application time switching circuit 12 composed of the monostable multivibrator 13, and the gate clock signal CLG is generated by the time constant of the capacitor C1 and the resistor R2. The High time (timing) from the rise of the gate clock signal CLG is set so that the period of the HIGH level state becomes, for example, 50 μs.
[0124]
The control switch 14 is connected in series with the resistor R1, and a resistor R2 is connected in parallel with a series circuit of the control switch 14 and the resistor R1.
[0125]
When the control switch 14 is turned on by an inverted pulse signal RP2 output from the RP generation circuit 53 of the control IC 11a, a CR circuit including the capacitor C1, the resistors R1 and R2 connected to the monostable multivibrator 13, and the control switch 14 Is the product of the capacitor C1 and the resistance component (R1 × R2) / (R1 + R2). In this case, the period of the high level state of the gate clock signal CLG is set to, for example, 30 μs so that the period of the gate clock signal CLG becomes 30 μs. A High time (timing) from the rise is set. The control terminal of the control switch 14 is connected to an inverted pulse signal line from the control IC 11a.
[0126]
Further, when the HIGH level voltage of the inversion pulse signal RP2, which is inverted every n-field period, is input to the control terminal and the control switch 14 is turned on, the drive voltage application time switching circuit 12 turns on the resistors R1 and R2 of the CR circuit. In this case, the time constant of the CR circuit is the product of the capacitor C1 and the resistance component (R1 × R2) / (R1 + R2), and the CLG terminal for the gate driver 40 is in the HIGH level state of the gate clock signal CLG. The gate clock signal CLG whose period is set to, for example, 30 μs is applied.
[0127]
When the LOW level voltage of the inversion pulse signal RP2, which is inverted every frame period, is input to the control terminal of the control switch 14 and the control switch 14 is turned off, the drive voltage application time switching circuit 12 turns on the resistor R2 of the CR circuit. The capacitor C1 is connected in series. In this case, the time constant of the CR circuit is R2 × C1, and the period of the HIGH level state of the gate clock signal CLG at the CLG terminal for the gate driver 40 is, for example, 50 μs. The gate clock signal CLG is applied.
[0128]
As described above, the control switch 14 is continuously turned on / off at intervals of one frame period based on the inversion pulse signal RP2, so that the TFT 25 applied to the gate (G: control terminal) of each TFT 25 of the liquid crystal panel 20. The drive voltage application time (gate-on period) of the gate control signal for normal operation and the drive voltage application time (gate-on period) of the gate control signal for electrical characteristic inspection can be switched every frame period interval ( Here, for example, the gate-on time for normal operation is 50 μs, and the gate-on time for electrical characteristics inspection is 30 μs.)
[0129]
With the above configuration, when judging the electrical characteristics of each TFT 25 provided on the liquid crystal panel 20, the serial signal SI for performing the quality determination is input to the serial-parallel conversion circuit 51 and the serial-parallel conversion circuit 51 Thus, a control signal for generating a signal for testing the electrical characteristics of the TFT is output to the RP generation circuit 53. The vertical synchronizing signal VD is also input to the RP generation circuit 53, and an inversion pulse signal RP2 synchronizing with the vertical synchronizing signal VD and inverting the polarity every one frame period is supplied from the control IC 11a to the driving voltage application time switching circuit 12. Is output to the control switch 14.
[0130]
As a result, the control switch 12 is turned on / off every frame period of the vertical synchronization signal VD, so that the CLG terminal for the gate driver 40 has a drive voltage application time (during normal operation and electric characteristic inspection). For example, in this embodiment, the gate clock signals CLG set at 50 μs and 30 μs, respectively, are alternately applied during the HIGH level state. The gate clock signal CLG in which the drive voltage application time is set in the normal operation and the electrical characteristic test is output from the output buffer 42 via the V shift register 41 as a gate control signal voltage (gate voltage VGH). The signal is output to the gate of the TFT 25 connected to the line 23. The gate clock signal CLG applied to the CLG terminal for the gate driver 40 is a signal that is synchronized with the inverted pulse signal RP2 shown in FIG. 4 and has a polarity opposite to that of the inverted pulse signal RP2.
[0131]
Therefore, the gate voltage VGH in which the drive voltage application time (the period of the HIGH level state) of 50 μs and 30 μs for the normal operation and the electrical characteristic test, respectively, is applied to the TFT 25 connected to the gate control signal line 23. Then, in the liquid crystal display device 10 a having the defective TFT 25 whose electric characteristics are shifted, a luminance difference occurs in the image on the display screen of the liquid crystal panel 20. In this case, the driving voltage of the gate voltage VGH is changed every frame period. By switching the application time (the period of the HIGH level state) to 50 μs and 30 μs, the luminance difference of the image is recognized as flicker by the eyes of the inspector, and the quality of the liquid crystal display device 10a is easily and reliably determined. be able to.
(Embodiment 3)
FIG. 5 is a block diagram illustrating a configuration of a main part of a liquid crystal display device that is Embodiment 3 of the present invention.
[0132]
The liquid crystal display device 10b of the present invention shown in FIG. 5 includes a liquid crystal panel 20 serving as an image display unit and an image for sequentially selecting one image signal line 24 from a plurality of image signal lines 24 and supplying each color signal of the image signal. A source driver 30 serving as a signal line driving unit, a gate driver 40 serving as a control signal line driving unit that sequentially selects one gate control signal line 23 from a plurality of gate control signal lines 23 and supplies a gate control signal; It has a control IC 11b as a control circuit including a timing control signal generating means, and a drive voltage application time switching circuit 12 as drive voltage application time setting means.
[0133]
The control IC 11b includes a serial-parallel conversion circuit 51 to which the serial signal SI is input, a CLG generation circuit 52 that generates a gate clock signal CLG by a control signal from the serial-parallel conversion circuit 51, and a control signal from the serial-parallel conversion circuit 51. And an RP generation circuit 54 for generating an inverted pulse signal RP3 by the vertical synchronizing signal VD. The RP generating circuit 54 outputs the input sampling signal SP, the clock signal CLK and the transfer signal TRS to the source driver 30, and outputs the inverted pulse signal RP3 and the gate clock. The signal CLG is output to the drive voltage application time switching circuit 12, and the start pulse signal SPG is output to the gate driver 40.
[0134]
The drive voltage application time switching circuit 12, the liquid crystal panel 20, the source driver 30, and the gate driver 40 are the same as those of the liquid crystal display device 10 of the first embodiment shown in FIG.
[0135]
Further, in the liquid crystal display device 10b shown in FIG. 5, a driving voltage application time switching means is constituted by a control IC 11b and a driving voltage application time switching circuit 12, and the driving voltage application time switching means outputs an output from the control IC 11b. A drive voltage application time (gate-on period) of a gate control signal for normal operation of the TFT 25 to be supplied to the gate driver 40 based on the inverted pulse signal RP3, which is a switching timing control signal, and a gate control signal for electrical characteristic inspection Can be switched for each predetermined screen position. The gate-on period corresponds to a period in which the gate control signal is in a HIGH level state.
[0136]
Further, the drive voltage application time switching means, the source driver 30 and the gate driver 40 constitute an image display control means. The image display control means controls the TFT 25 as each pixel electrode drive element for normal operation. The drive voltage application time (gate-on period) of the gate control signal of (1) and the drive voltage application time (gate-on period) of the gate control signal for electrical characteristic inspection are switched for each predetermined screen position, and the gate-on period is changed to the predetermined screen position. The gate control signal switched every time is applied to the liquid crystal layer LC corresponding to each pixel electrode 21 of the liquid crystal panel 20 to display an image. Here, the predetermined screen position is a screen position that can be visually checked, for example, the same line (an intermediate line position shown in FIG. 6) in the middle of one screen (one field).
[0137]
The control IC 11b has an RP generation circuit 54, and the serial / parallel conversion circuit 51 and the RP generation circuit 54 constitute a switching timing control signal generation unit. This switching timing control signal generating means generates an inverted pulse signal RP3 as a switching timing control signal.
[0138]
The RP generation circuit 54 receives the vertical synchronizing signal VD and the control signal from the serial / parallel conversion circuit 51, and outputs an inversion pulse signal RP3 which is inverted at the same line position in the middle of one screen (one field). The inverted pulse signal RP3 is controlled by the serial signal SI input to the control IC 11b, and is output from the control IC 11b as a LOW level signal when a normal display is performed by the serial / parallel conversion circuit 51 in the control IC 11b.
[0139]
The drive voltage application time switching circuit 12 is configured before the gate driver 40 to which the gate clock signal CLG for switching the gate-on period of the gate control signal at the same line position in one screen (one field) is input.
[0140]
The gate clock signal CLG output from the CLG generation circuit 52 of the control IC 11b is input to the drive voltage application time switching circuit 12 composed of the monostable multivibrator 13, and the gate clock signal CLG is generated by the time constant of the capacitor C1 and the resistor R2. The High time from the rise of the gate clock signal CLG is set so that the period of the HIGH level state becomes, for example, 50 μs.
[0141]
The control switch 14 is connected in series with the resistor R1, and a resistor R2 is connected in parallel with a series circuit of the control switch 14 and the resistor R1.
[0142]
When the control switch 14 is turned on by the inverted pulse signal RP3 output from the RP generation circuit 54 of the control IC 11b, a CR circuit including the capacitor C1, the resistors R1 and R2 connected to the monostable multivibrator 13, and the control switch 14 Is the product of the capacitor C1 and the resistance component (R1 × R2) / (R1 + R2). In this case, the period of the high level state of the gate clock signal CLG is set to, for example, 30 μs so that the period of the gate clock signal CLG becomes 30 μs. A High time from the rise is set. The control terminal of the control switch 14 is connected to an inverted pulse signal line from the control IC 11b.
[0143]
Further, when the HIGH level voltage of the inversion pulse signal RP3, which is inverted at the same line position in the middle of one screen (one field), is input to the control terminal and the control switch 14 is turned on, the drive voltage application time switching circuit 12 turns on. The resistors R1 and R2 of the CR circuit are connected in parallel. In this case, the time constant of the CR circuit is the product of the capacitor C1 and the resistance component (R1 × R2) / (R1 + R2), and the gate is connected to the CLG terminal for the gate driver 40. The gate clock signal CLG whose period of the HIGH level state of the clock signal CLG is set to, for example, 30 μs is applied.
[0144]
The drive voltage application time switching circuit 12 inputs the LOW level voltage of the inversion pulse signal RP3, which is inverted for each line position in the middle of one screen (one field), to the control terminal of the control switch 14, and the control switch 14 is turned off. Then, the resistor R2 of the CR circuit and the capacitor C1 are connected in series. In this case, the time constant of the CR circuit is R2 × C1, and the period of the HIGH level state of the gate clock signal CLG is connected to the CLG terminal for the gate driver 40. For example, a gate clock signal CLG of 50 μs is applied.
[0145]
As described above, the control switch 14 is continuously turned on / off at the same line position interval in the middle of one screen (one field) based on the inversion pulse signal RP3, so that the gate (G: The drive voltage application time of the gate voltage VGH applied to the control terminal (normal operation) and the electrical characteristic inspection (gate-on time: 50 μs during normal operation and 30 μs during electrical characteristic inspection) is 1 Switching can be performed for each same line position in the middle of the screen (one field).
[0146]
In this manner, the inversion pulse signal RP3 is inverted at the same line position in the middle of one screen (one field), and the gate voltage application time (high-level period) of the gate voltage VGH output from the gate driver 40 becomes one. Switching from 50 μs to 30 μs at the same position in the middle of the screen (one field).
[0147]
With the above configuration, when judging the electrical characteristics of each TFT 25 provided on the liquid crystal panel 20, the serial signal SI for performing the quality determination is input to the serial-parallel conversion circuit 51 and the serial-parallel conversion circuit 51 Thus, a control signal for generating a signal for testing the electrical characteristics of the TFT 25 is output to the RP generation circuit 54. The vertical synchronizing signal VD is also input to the RP generation circuit 54, and the RP generation circuit 54 repeatedly outputs an inverted pulse signal RP3 whose polarity switches in the middle of one screen (one field) every field.
[0148]
As a result, the gate voltage application time of the gate voltage VGH (the period of the HIGH level state) is changed from 50 μs to 30 μs in synchronization with the inversion pulse signal RP3, and the liquid crystal display device 10b having the defective TFT 25 whose electric characteristics are deviated. In this case, a luminance difference occurs in the image on the display screen of the liquid crystal panel 20. In this case, the gate voltage application time is switched to either 50 μs or 30 μs at the same line position in the middle of one screen (one field). To judge the quality of the liquid crystal display device 10b easily and reliably by visually observing the difference in image brightness between the upper part of the display screen where the gate voltage application time is 50 μs and the lower part of the display screen where the gate voltage application time is 30 μs. Can be.
(Embodiment 4)
FIG. 7 is a block diagram illustrating a configuration of a main part of a liquid crystal display device that is Embodiment 4 of the present invention.
[0149]
The liquid crystal display device 10c of the present invention shown in FIG. 7 includes a liquid crystal panel 20 as an image display means and an image for sequentially selecting one image signal line 24 from a plurality of image signal lines 24 and supplying each color signal of the image signal. A source driver 30 serving as a signal line driving unit, a gate driver 40 serving as a control signal line driving unit that sequentially selects one gate control signal line 23 from a plurality of gate control signal lines 23 and supplies a gate control signal; It has a control IC 11c which is a control circuit including timing control signal generating means, and a drive voltage application time switching circuit 42 which is drive voltage application time setting means.
[0150]
The control IC 11c includes a serial-parallel conversion circuit 51 to which the serial signal SI is input, a CLG generation circuit 52 that generates a gate clock signal CLG based on a control signal from the serial-parallel conversion circuit 51, and a control signal from the serial-parallel conversion circuit 51. And a 1/6 frequency dividing circuit 55 for generating an inverted pulse signal RP4 by the gate clock signal CLG from the CLG generating circuit 52, and outputs the input sampling signal SP, the clock signal CLK and the transfer signal TRS to the source driver 30. Then, the inversion pulse signal RP4 and the gate clock signal CLG are output to the drive voltage application time switching circuit 12, and the start pulse signal SPG is output to the gate driver 40.
[0151]
The drive voltage application time switching circuit 12, the liquid crystal panel 20, the source driver 30, and the gate driver 40 are the same as those of the liquid crystal display device 10 of the first embodiment shown in FIG.
[0152]
Further, in the liquid crystal display device 10c shown in FIG. 7, a driving voltage application time switching means is constituted by the control IC 11c and the driving voltage application time switching circuit 12, and the driving voltage application time switching means outputs from the control IC 11c. A drive voltage application time (gate-on period) of a gate control signal for normal operation of the TFT 25 to be supplied to the source driver 40 based on the inverted pulse signal RP4 as a switching timing control signal, and a gate control signal for electrical characteristic inspection Can be switched for every predetermined line in one screen (one field). The gate-on period corresponds to a period in which the gate control signal is in a HIGH level state.
[0153]
Further, the drive voltage application time switching means, the source driver 30 and the gate driver 40 constitute an image display control means. The image display control means controls the gate of the TFT 25 with respect to the TFT 25 as each pixel electrode drive element. The drive voltage application time (gate-on period) at the time of normal operation of signals and at the time of electrical characteristic inspection is switched for each predetermined line in one screen (one field), and the gate-on period is changed for each predetermined line of one screen (one field). The switched gate control signal is applied to the liquid crystal layer LC corresponding to each pixel electrode 21 of the liquid crystal panel 20 to display an image. Here, every predetermined line in one screen (one field) is the number of lines that can be visually confirmed, for example, every three lines in one screen (one field) as shown in FIG.
[0154]
The control IC 11c has a 1/6 frequency dividing circuit 55, and the serial / parallel converting circuit 51 and the 1/6 frequency dividing circuit 55 constitute a switching timing control signal generating means. This switching timing control signal generating means generates an inverted pulse signal RP4 as a switching timing control signal.
[0155]
The 1/6 frequency dividing circuit 55 receives the gate clock signal CLG from the CLG generating circuit 52 and the control signal from the serial / parallel conversion circuit 51, and inverts a pulse every three lines in one screen (one field). Output RP4. The inverted pulse signal RP4 is controlled by a serial signal SI input to the control IC 11c, and is output from the control IC 11c as a LOW level signal when a normal display is performed by the serial / parallel conversion circuit 51 in the control IC 11c.
[0156]
The drive voltage application time switching circuit 42 is configured before the gate driver 40 to which the gate clock signal CLG that switches the gate-on period of the gate control signal at every three lines in one screen (one field) is input. .
[0157]
The gate clock signal CLG output from the CLG generation circuit 52 of the control IC 11c is input to the drive voltage application time switching circuit 12 composed of the monostable multivibrator 13, and the gate clock signal CLG is generated by the time constant of the capacitor C1 and the resistor R2. The High time (timing) from the rising of the gate clock signal CLG is set so that the period of the HIGH level state becomes, for example, 50 μs.
[0158]
The control switch 14 is connected in series with the resistor R1, and a resistor R2 is connected in parallel with a series circuit of the control switch 14 and the resistor R1.
[0159]
When the control switch 14 is turned on by the inverted pulse signal RP4 output from the 1/6 frequency dividing circuit 55 of the control IC 11c, the control switch 14 includes the capacitor C1, the resistors R1 and R2 connected to the monostable multivibrator 13, and the control switch 14. The time constant of the CR circuit is the product of the capacitor C1 and the resistance component (R1 × R2) / (R1 + R2). In this case, the period of the high-level state of the gate clock signal CLG is set to 30 μs, for example. A High time from the rise of the CLG is set. The control terminal of the control switch 14 is connected to an inverted pulse signal line from the control IC 11b.
[0160]
Further, when the HIGH level voltage of the inversion pulse signal RP4, which is inverted every three lines in one screen (one field), is input to the control terminal and the control switch 14 is turned on, the drive voltage application time switching circuit 12 turns on the CR circuit. In this case, the time constant of the CR circuit is the product of the capacitor C1 and the resistance component (R1 × R2) / (R1 + R2), and the gate clock signal is supplied to the CLG terminal for the gate driver 40. The gate clock signal CLG, which is set to a period of, for example, 30 μs during the HIGH level state of the CLG, is applied.
[0161]
When the LOW level voltage of the inversion pulse signal RP4, which is inverted every three lines in one screen (one field), is input to the control terminal of the control switch 14, the drive voltage application time switching circuit 12 turns off the control switch 14. The resistor R2 of the CR circuit and the capacitor C1 are connected in series. In this case, the time constant of the CR circuit is R2 × C1, and the period of the HIGH level state of the gate clock signal CLG is applied to the CLG terminal for the gate driver 40, for example. , 50 μs.
[0162]
As described above, the control switch 14 is continuously turned on / off at intervals of every three lines in one screen (one field) based on the inversion pulse signal RP4, so that the gate (G: The drive voltage application time (here, 50 μs during normal operation and 30 μs during electrical characteristic inspection) of the gate voltage VGH applied to the control terminal during normal operation and electrical characteristic inspection is one screen (1 Field), it is possible to switch every three lines.
[0163]
In this way, the inversion pulse signal RP4 is inverted every three lines in one screen (one field), and the gate voltage application time of the gate voltage VGH output from the gate driver 40 (the period of the HIGH level state) is one screen (the high level state). In one field), it switches from 50 μs to 30 μs every three lines.
[0164]
The inverted pulse signal RP4 is controlled by a serial signal SI input to the control IC 11c. The serial signal SI is output when the serial parallel conversion circuit 51 in the control IC 11c performs a normal display. Is set to be output from the control IC 11c as a LOW level signal. Then, the control switch 14 to which the inverted pulse signal RP4 of the LOW level signal is inputted is turned off, and the gate voltage signal CLG for setting the gate voltage application time of the gate voltage VGH to 50 μs from the drive voltage application time switching circuit 12 is applied. Output to the driver 40.
[0165]
With the above configuration, when judging the electrical characteristics of each TFT 25 provided on the liquid crystal panel 20, the serial signal SI for performing the quality determination is input to the serial-parallel conversion circuit 51 and the serial-parallel conversion circuit 51 Thus, a control signal for generating a signal for testing the electrical characteristics of the TFT 25 is output to the 1/6 frequency dividing circuit 55. The 1/6 frequency dividing circuit 55 also receives the gate clock signal CLG for the gate driver 40 from the CLG generating circuit 52. The inverted pulse signal RP4 obtained by dividing the gate clock CLG signal by 1/6 is supplied to the control IC 11c. Is input to the control terminal of the control switch 14.
[0166]
As a result, the drive voltage application time switching circuit 12 switches the drive voltage application time (here, 50 μs and 30 μs, respectively) during normal operation and electrical characteristic inspection for every three lines in one screen (one field). The clock signal CLG is output to the CLG terminal of the gate driver 40. This operation is repeatedly performed for each field.
[0167]
Therefore, based on the gate clock signal CLG input to the gate driver 40, the gate voltage application time (high-level period) of the gate voltage VGH output from the output buffer 42 is 50 μs in synchronization with the inversion pulse signal RP4. In the liquid crystal display device 10c having the defective TFTs 25 whose electric characteristics are shifted from that of the liquid crystal display device 10c, a luminance difference occurs for each predetermined line group on the display screen of the liquid crystal panel 20. In this case, for example, In one screen (one field), the gate voltage application time is switched to either 50 μs or 30 μs for every three lines, so that the brightness changes every three lines in one screen, and a horizontal stripe pattern appears on the display screen. Appear. As a result, the quality of the liquid crystal display device 10c in which the electrical characteristics of the TFT 25 are shifted can be determined by checking whether or not a horizontal stripe pattern on the display screen of the liquid crystal panel 20 appears. Can be.
(Embodiment 5)
FIG. 9 is a timing chart showing the drive timing of the gate driver and the application distribution of the gate voltage application time for each display screen in the liquid crystal display device according to the fifth embodiment of the present invention.
[0168]
FIG. 9 shows a comparison between the output timing of the gate voltage VGH of the gate driver 40 and the distribution of gate voltage application periods (50 μs and 30 μs) applied to one display screen in the liquid crystal display device according to the third embodiment shown in FIG. As described above, in the gate voltage application time within one screen from the fifth screen to the sixth screen and thereafter, the positions of the 50 μs application part for normal operation and the 30 μs application part for electrical characteristic inspection are set upside down. The output waveform level of the inverted pulse signal RP5 is set so as to be at the position. For example, the polarity of the inverted pulse signal RP5 after the m-th screen (m is a natural number: m = 6 in FIG. 9) is set to be opposite to the polarity of the inverted pulse signal RP5 up to the (m-1) -th screen. The gate voltage application time from the m-th screen is set to 30 μs, and the gate voltage application time to the (m−1) -th screen is set to 50 μs.
[0169]
Therefore, even if the shift of the electrical characteristics of the TFT 25 occurs only in the upper part of the display screen of the liquid crystal panel 20, before and after the predetermined screen, the gate voltage VGH of each TFT 25 during the normal operation and during the electrical characteristics is changed. By setting the distribution of the gate-on voltage application time (50 μs and 30 μs, respectively) to the display screen to be reversed in the upper or lower part of the display screen, a defective TFTb having a deviated electrical characteristic can be easily formed. In addition, the liquid crystal display device is detected accurately and the quality of the liquid crystal display device can be easily and reliably determined.
(Embodiment 6)
FIG. 10 is a block diagram illustrating a configuration of a main part of a liquid crystal display device that is Embodiment 6 of the present invention.
[0170]
As shown in FIG. 10, in FIGS. 1, 3, 5, and 7, for example, a monostable multi-unit of a drive voltage application time switching circuit 12 that sets a gate voltage application time (a period of a HIGH level state) of 30 μs is set. By setting the resistor R1 of the CR circuit connected to the vibrator 13 to a variable resistor VR1 as a variable resistor means, the gate voltage VGH, which is the drive voltage of the TFT 25 of the liquid crystal panel 20, at the time of normal operation and at the time of electrical characteristic inspection. One of the gate voltage application times can be extended to, for example, 40 μs or reduced to 20 μs. Thus, the liquid crystal display device according to the sixth embodiment shown in FIG. 10 can change the detection level of the deviation of the electrical characteristics of the TFT 25.
[0171]
Similarly, the resistor R2 of the CR circuit may be a variable resistor VR2, which is a variable resistor. In this case, the gate voltage VGH, which is the drive voltage of the TFT 25 of the liquid crystal panel 20, can be varied as much as 50 μs, which is the other of the gate voltage application times during the normal operation and the electrical characteristic test. This makes it possible to finely change the detection level of the deviation of the electrical characteristics of the TFT 25.
[0172]
As described above, according to the first to sixth embodiments of the present invention, for each TFT 25 of the liquid crystal panel 20, the gate voltage applied time during the normal operation of the gate voltage applied to the TFT 25 and during the electrical characteristic test (for example, Is switched between 50 μs during normal operation and 30 μs during electrical characteristic inspection), and an image is displayed on the display screen of the liquid crystal panel 20. Thus, in the case of a TFT having poor electrical characteristics, slight TFT electrical changes are caused by the brightness of the display image every predetermined switching time (eg, n-field period) or every predetermined display screen position (eg, the same line position). The shift in characteristics makes it possible to easily and reliably confirm defective liquid crystal display devices, and saves time with a large-scale device that displays both the inspection target device and the reference comparison target device as before. It is not necessary to compare the brightness of the display image of the liquid crystal display device.
[0173]
In the first to sixth embodiments, the switching timing control signal generating means and the driving voltage application time switching means capable of controlling the switching timing of the two types of driving voltage application time of the gate voltage are provided by the liquid crystal display devices 10, 10a, 10b, 10c and the like, the switching timing control signal generating means and the drive voltage application time switching means are provided outside the liquid crystal display device by the device electrical characteristic quality determination device (FIGS. 1, 3, 5, (It may be constituted by a control IC and a drive voltage switching circuit on the arrow A side in FIGS. 7 and 10).
[0174]
Further, by manually switching from outside, the driving voltage application time during the normal operation of the gate voltage of the TFT and during the electrical characteristic inspection may be switched.
[0175]
As described above, according to the present invention, for each pixel electrode driving element, an image is displayed by switching between the voltage application time of the control signal for normal operation and the voltage application time of the control signal for electrical characteristic inspection. Therefore, in the case of defective electrical characteristics of the pixel electrode driving element, defective products due to slight deviations in the electrical characteristics of the pixel electrode driving element may be determined by the brightness of the display image depending on the switching time or switching position. Also, it is possible to easily and surely check the brightness, and it is not necessary to operate the inspection target device and the reference comparison target device together and to compare the luminance with a large-scale device over time as in the related art.
[0176]
The detection of the liquid crystal display device in which the electrical characteristics of the pixel electrode driving element are shifted is performed during the display period (every n-field period) by applying the voltage of the control signal for normal operation (the driving voltage of the pixel electrode driving element). (The application time) is switched to the voltage application time of the control signal for electrical characteristic inspection, and the determination is made based on the change in the brightness of the display screen. Therefore, unlike the related art, the brightness is not compared with a non-defective liquid crystal display device. Also, there is no need to measure the brightness of the display screen of the liquid crystal display device. For this reason, the work of judging the quality of the element characteristics is simplified, and the work efficiency is improved.
[0177]
The voltage application time of the control signal for normal operation and the voltage application time of the control signal for electrical characteristic inspection (two types of drive voltage application times) output to the control signal line are, for example, 50 μs per frame. In the liquid crystal display device in which the electric characteristics of the picture element electrode driving element are shifted, the display screen looks like flicker. By checking the flicker, the quality of the liquid crystal display device is determined. Can be performed easily and reliably.
[0178]
Furthermore, the voltage application time of the control signal for normal operation output to the control signal line and the voltage application time of the control signal for electrical characteristic inspection (two types of drive voltage application times) are set in the middle of one screen, for example, Since the switching between 50 μs and 30 μs is performed, in a liquid crystal display device in which the electric characteristics of the pixel electrode driving element are shifted, the electric characteristic of the pixel electrode driving element is changed by the luminance difference between the upper part and the lower part of the display screen. It is possible to easily and surely determine whether or not the liquid crystal display device is defective, and it is possible to reliably detect a defective liquid crystal display device in a shorter time than in the method of switching the drive voltage application time (voltage application time) within the display period.
[0179]
Further, the voltage application time of the control signal for normal operation and the voltage application time of the control signal for electrical characteristic inspection (two types of drive voltage application times) output to the control signal line are set in the middle of one screen, for example. In addition to switching between 50 μs and 30 μs, the voltage application time of the control signal for normal operation and the voltage application time of the control signal for electrical characteristic inspection during the image display period are respectively set between 50 μs and 30 μs. By switching in the opposite direction, it is easy to judge the quality of the liquid crystal display device even when there is a slight shift in the electrical characteristics of the pixel electrode driving element in a part (for example, upper or lower) of the image display screen. It can be done reliably.
[0180]
Further, the voltage application time of the control signal for normal operation and the voltage application time of the control signal for electrical characteristic inspection (two types of drive voltage application times) are determined for each predetermined line (for example, three lines) on the display screen. For example, in order to switch between 50 μs and 30 μs, in a liquid crystal display device in which the electric characteristics of the pixel electrode driving elements are shifted, the brightness of the display changes every predetermined line within one screen, and the horizontal stripes are formed. It is possible to easily and reliably determine whether or not the electrical characteristics of the pixel electrode driving element are good by simply performing a confirmation inspection. Further, in this case, even when the electrical characteristics of the pixel electrode driving elements are shifted only in a part of the display screen, the portions where the electrical characteristics of the pixel electrode driving elements are shifted are striped. Therefore, the quality of a part of the display screen of the liquid crystal display device in which the electric characteristics of the pixel electrode driving element are shifted can be easily and reliably determined.
[0181]
Further, the voltage application time of the control signal for normal operation and the voltage application time of the control signal for electrical characteristic inspection (two types of drive voltage application times) for each predetermined line (for example, three lines) are, for example, 50 μs. In addition to switching between 30 μs, for example, by changing the switching direction (switching order) between 50 μs and 30 μs during the image display period, only a small part of the display screen ( It is possible to easily and surely detect the deviation of the electrical characteristics of the pixel electrode driving elements (several lines), and it is possible to easily and reliably determine the quality of the liquid crystal display device.
[0182]
Further, by changing at least one of the voltage application time of the control signal for normal operation and the voltage application time (two types of drive voltage application times) of the control signal for electrical characteristic inspection, the luminance difference of the image display can be improved. Can be satisfactorily changed so that the detection level of the electrical characteristic failure of the pixel electrode driving element can be changed so as to be clearer.
[0183]
Further, a switching timing control signal generating means and a driving voltage application time switching means capable of controlling the switching timing of the above two driving voltage application times in addition to a normal driving method in, for example, a control IC incorporating a control circuit of the liquid crystal display device. With the built-in, it is possible to easily and reliably detect the quality of the electrical characteristics of the picture element electrode drive element after being incorporated into a product as a liquid crystal display, and easily and reliably determine the quality of the liquid crystal display. It can be carried out.
[0184]
【The invention's effect】
The liquid crystal display device of the present invention displays an image by switching between the voltage application time of the control signal for normal operation and the voltage application time of the control signal for electrical characteristic inspection for each pixel electrode driving element. When the electrical characteristics of the pixel electrode driving element are poor, the electrical characteristics (voltage-current characteristics) of the pixel electrode driving element are slightly reduced by the brightness of the display image depending on the switching time or switching position. Defective products due to misalignment can be easily and reliably checked, and the luminance of the display image is increased over a long period of time with a large-scale device by operating both the inspection target device and the reference comparison device as in the past. There is no need to make comparisons.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a main part of a liquid crystal display device according to a first embodiment of the present invention.
FIG. 2 is a diagram showing a drive timing of the gate driver shown in FIG. 1 and an application distribution of a gate voltage application time for each one display screen.
FIG. 3 is a block diagram illustrating a configuration of a main part of a liquid crystal display device according to a second embodiment of the present invention.
4 is a diagram showing driving timing of the gate driver shown in FIG. 3 and an application distribution of a gate voltage application time for each screen of display.
FIG. 5 is a block diagram illustrating a configuration of a main part of a liquid crystal display device according to a third embodiment of the present invention.
6 is a diagram showing a drive timing of the gate driver shown in FIG. 5 and an application distribution of a gate voltage application time for each one display screen.
FIG. 7 is a block diagram illustrating a configuration of a main part of a liquid crystal display device according to a fourth embodiment of the present invention.
8 is a diagram showing a drive timing of the gate driver shown in FIG. 7 and an application distribution of a gate voltage application time for each display screen.
FIG. 9 is a diagram showing a drive timing of a gate driver and an application distribution of a gate voltage application time for each display screen in a liquid crystal display device according to a fifth embodiment of the present invention.
FIG. 10 is a block diagram illustrating a configuration of a main part of a liquid crystal display device according to a sixth embodiment of the present invention.
FIG. 11 is a block diagram showing an example of a configuration of a main part of a conventional active matrix type liquid crystal display device.
12 is a timing chart of each gate control signal from the gate driver shown in FIG.
13 is a timing chart of the gate voltage and the drain voltage of the TFT synchronized with the video signal output voltage and the gate clock signal of the source driver shown in FIG.
FIG. 14 is a graph showing a relationship between a gate-source voltage VGS and a source-drain current IDS of a TFT.
[Explanation of symbols]
10 Liquid crystal display device
10a Liquid crystal display device
10b Liquid crystal display device
10c Liquid crystal display device
11 Control IC
11a Control IC
11b Control IC
11c Control IC
12 Drive voltage application time switching circuit
13 Monostable multivibrator
14 Control switch
20 LCD panel
21 Picture element electrode
23 Gate control signal line
24 Video signal line
25 TFT
30 Source Driver
31 H shift register
32 RGB signal lines
33 Sampling SW
34 sampling capacitor
35 Transfer SW
36 Transfer Capacitor
37 Operational Amplifier
40 gate driver
41 V shift register
42 output buffer
42a P-type MOS transistor
42b N-type MOS transistor
51 Serial / parallel conversion circuit
52 CLG generation circuit
53 RP generation circuit
54 RP generation circuit
55 1/6 frequency divider
100 liquid crystal display
200 LCD panel
300 source driver
400 gate driver
500 control IC

Claims (10)

A pixel electrode is provided near each intersection of a plurality of video signal lines and a plurality of control signal lines, and a video signal is applied to each pixel electrode at each drive timing of each pixel electrode drive element by a control signal. In a liquid crystal display device that supplies and displays an image,
A liquid crystal display device having image display control means for switching between the voltage application time of the control signal and the voltage application time of the control signal for electrical characteristic inspection to each of the picture element electrode driving elements to enable image display. The image display control means,
Video signal line driving means for sequentially selecting a video signal line from a plurality of video signal lines and supplying a video signal,
Control signal line driving means for sequentially selecting a control signal line from a plurality of control signal lines and supplying a control signal,
Drive voltage application time switching means for switching between a voltage application time of the control signal of each of the picture element electrode driving elements supplied to the control signal line driving means and a voltage application time of the control signal for electrical characteristic inspection The liquid crystal display device according to claim 1, comprising: The voltage application time of the control signal for electrical characteristic inspection is set based on the voltage-current characteristic of the pixel electrode driving element determined to be normal and the voltage-current characteristic of the pixel electrode driving element determined to be defective. The liquid crystal display device according to claim 1, wherein: The drive voltage application time switching means,
Switching timing control signal generating means for generating a switching timing control signal;
Driving voltage application time setting means for alternately switching between the voltage application time of the control signal of each of the picture element electrode driving elements and the voltage application time of the control signal for electrical characteristic inspection based on the switching timing control signal. The liquid crystal display device according to claim 2, comprising: The drive voltage application time setting means has a switching circuit connected in series to one of the two resistors connected in parallel, and controls the switching circuit in accordance with the switching timing control signal, The liquid crystal display device according to claim 4, further comprising a circuit for generating a voltage application time of the control signal of each picture element electrode driving element and a voltage application time of the control signal for electrical characteristic inspection. 5. The liquid crystal display device according to claim 4, wherein the switching timing control signal generator switches the switching timing control signal level at least every n (n is a natural number) field period or every n frame periods of the screen display. 5. The liquid crystal display device according to claim 4, wherein the switching timing control signal generating means switches the switching timing control signal level within one field of a screen display and at the same display line position for each field. 8. The liquid crystal display device according to claim 7, wherein a switching line position in one field of the screen display is one or a plurality of positions. 9. The liquid crystal display device according to claim 7, wherein the switching direction of the switching timing control signal level at the same display line position is a reverse direction for every m (m is a natural number) fields. The liquid crystal display device according to any one of claims 1 to 9, wherein at least one of a voltage application time of the control signal and a set value of a voltage application time of the control signal for electrical characteristic inspection is variable.

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