JP2004227724A - Semiconductor memory device and data reading method - Google Patents

Abstract

An object of the present invention is to improve the read margin by canceling the influence of threshold variation of a gain transistor.
A dummy transistor (dT11) is arranged near a gain transistor (T11) connected to a memory cell to be accessed, thereby driving a bit line (BL) used as a reference to reduce the potential or current of the bit line. Use as a reference signal for read determination cancels out the influence of threshold variation of the gain transistor. Further, by supplying a signal from the dummy cell having the same structure as the memory cell of the memory unit to the dummy transistor, the characteristic variation occurring between the chips of the memory element, between the wafers, and between the lots is canceled.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to a reference potential generation technique for reading data.
[0002]
[Prior art]
With the miniaturization of semiconductor processing dimensions, instead of directly driving a bit line with a memory cell, a weak signal generated from a small memory cell is once received by the gate of an FET as a gain transistor, and the bit line is then applied to the bit line by the FET. Has attracted attention.
[0003]
Since such a gain-type memory is excellent in scalability, application to a DRAM or FeRAM is being studied. However, a similar method can be applied to other memories such as a flash memory and a magnetic memory (MRAM).
For example, in the following document, the present applicant has proposed a semiconductor memory device in which a plurality of ferroelectric capacitors are shared by one gain FET, and there is almost no area overhead due to installation of a gain circuit.
[Patent Document 1] JP-A-2002-197857
[0004]
FIG. 9 shows an example of a semiconductor memory device as this gain type memory.
The memory unit MU includes a plurality of ferroelectric capacitors C1, C2,... Cn connected to the common node electrode NE. Each of the capacitors C, C2,... Cn is a memory cell that stores different data.
The gain transistor T1 is an N-channel MOS-FET in a depletion state, and its gate is connected to the common node electrode NE. Further, one of the source / drain is connected to a power supply line such as Vcc or ground, and the other is connected to a bit line BL via a read switch T2 formed by an FET.
The gate of the read switch T2 is connected to the read word line WLr.
A write switch T3 of an FET is provided. The gate of the write switch T3 is connected to the write word line WLw. One of the source / drain is connected to the common node electrode NE, and the other is connected to the bit line BL. ing.
[0005]
One end of each of the capacitors C1, C2,... Cn is connected to the common node electrode NE. The other ends are connected to plate lines PL1, PL2,... PLn, respectively.
[0006]
When one bit is stored in one memory cell in such a gain-type memory, reading thereof requires some reference means for data determination.
An example of a conventional reference method will be described with reference to FIG.
[0007]
FIG. 10 shows a memory array in which the memory units MU as shown in FIG. 9 are repeatedly arranged in the bit line BL direction and the word line WL direction.
Each of the memory units MU11, MU12,... Has, for example, four ferroelectric capacitors C1 to C4.
[0008]
Each memory unit arranged in the word line WL direction shares a read word line WLr and a write word line WLw.
For example, in the memory units MU11, MU12, MU13, and MU14, the read word line WLr1 is connected to the gate of the read switch T2 of each of the memory units (MU11 to MU14), and the write word line WLw1 is connected to each of the memory units (MU11 to MU11). MU14) is connected to the gate of the write switch T3.
A voltage is applied to each word line WL by a word line drive circuit (not shown) according to an address to be accessed and write / read.
[0009]
Each memory unit arranged in the direction of the bit line BL shares the bit line BL.
For example, a bit line BL1 is connected to the memory units MU11 and MU21 via a read switch T2 and a write switch T3.
Each of the bit lines BL (BL1, BL2,...) Is applied with a voltage by the sense amplifier 2 (2-1, 2-2,...) At the time of writing, and a potential is detected at the time of reading.
[0010]
As shown in FIG. 9, each of the capacitors C1 to C4 in the memory unit MU is connected to the plate line PL.
For example, in the memory units MU11, MU12, MU13, and MU14, the capacitors C1 to C4 are connected to plate lines PL11 to PL14, respectively.
A predetermined voltage is applied to each plate line PL by a plate line driving circuit (not shown).
[0011]
Further, reference potential generating circuit 1 for generating reference potential Vref is provided. The generated reference potential Vref is supplied to each of the sense amplifiers 2-1, 2-2,... As a reference signal.
The sense amplifier 2 (2-1, 2-2,...) Is a circuit that compares the potential of the bit line BL to be read with the reference potential Vref to determine a read value.
[0012]
In such a gain type memory, data reading is performed as follows.
For example, when reading data from the capacitor C1 of the memory unit MU11, the plate line PL11 is driven with the plate lines PL12 to PL14 fixed at 0V. Then, a signal corresponding to the polarization direction of the ferroelectric film forming the capacitor C1 is applied to the gate of the gain transistor T1.
Further, by selecting and turning on the read word line WLr1, the read switch T2 is turned on, and the gain transistor T1 is connected to the bit line BL1. As a result, the gain transistor T1 drives the bit line BL1, which has been equalized in advance to the Vcc potential, toward the ground. The driving capability depends on the gate potential, and varies depending on the storage state of the cell capacitor C1, that is, the polarization direction of the ferroelectric film. Therefore, the bit line potential changes depending on the storage state. The sense amplifier 2-1 compares the potential of the bit line BL1 with the reference potential Vref to determine the storage state of the cell capacitor C1, that is, whether the read value is "1" or "0". it can.
[0013]
In such a gain-type memory, the selected capacitor does not need to directly drive the bit line BL when reading data. Therefore, a large signal can be obtained even with a small capacitor, which is suitable for miniaturization.
[0014]
[Problems to be solved by the invention]
Usually, as shown in FIG. 10, a fixed potential generated by the reference potential generating circuit 1 outside the cell array is used as the reference potential Vref.
However, in that case, the following problem occurs.
[0015]
The threshold value of the gain transistor T1 has a distribution of a width of about several tens mV in the chip due to various factors in the manufacturing process.
Further, when the variation between the different chips in the wafer is included, the width is about 100 mV, and when the variation between the wafers and the lot is also included, the distribution width is 200 to 300 mV.
Accordingly, the driving capability of the bit line BL of the gain transistor T1 greatly varies, and even if the reference potential Vref is accurately generated, the read margin is significantly degraded.
[0016]
Further, the signal itself from the memory cell also varies among chips, between chips, between wafers, and between lots, and furthermore, the signal level also has a temperature dependency, so that each of them causes a deterioration of a read margin.
Further, when the memory unit MU to be accessed changes due to the difference in the ROW address of the memory cell to be accessed, and when the distance between the sense amplifier 2 and the gain transistor T1 changes, the amount of voltage drop due to the bit line resistance changes. The input potential fluctuates.
In addition, depending on a storage element used for a memory cell, a signal may have access number dependence depending on fatigue. Further, the read signal level may change depending on the elapsed time from the writing, that is, the data holding time. All of these also directly lead to deterioration of the read margin.
[0017]
As described above, as long as the fixed potential or the fixed current is used as the reference potential Vref, it is inevitable that various variations in the potential or the current of the read bit line greatly deteriorate the read margin.
[0018]
[Means for Solving the Problems]
Therefore, the present invention proposes a method of generating a reference potential or a reference current that effectively cancels out each of the above-mentioned causes of variation.
[0019]
Therefore, the semiconductor memory device of the present invention drives one or a plurality of memory cells for generating a read potential according to a stored value at a predetermined node, and drives a first bit line based on the read potential generated at the node. A semiconductor memory device including a memory array in which a plurality of memory units each having a gain transistor are arranged. A second bit line; reference driving means for driving the second bit line by a dummy transistor having the same size as the gain transistor based on a reference potential; the first bit line and the second bit line; Read current determining means for determining the value of data read from the memory unit by comparing both currents flowing through the bit lines, or both potentials of the first bit line and the second bit line. Is provided.
[0020]
The second bit line is provided corresponding to one or a plurality of the memory units, and the reference driving means is provided corresponding to the second bit line. The read value determination means drives the first bit line corresponding to the memory unit to be read by the gain transistor, and drives the second bit line by the reference drive means. Then, the value of the data is determined by comparing the current flowing through both bit lines or the potential of both bit lines.
[0021]
The semiconductor device further includes a dummy cell having the same structure as the memory cell, wherein the reference potential is set to a potential of a signal read from the dummy cell and supplied to a gate of the dummy transistor.
A short circuit that includes a plurality of the second bit lines and a plurality of reference drive units for driving the corresponding second bit lines, and short-circuits the gates of the plurality of dummy transistors included in each of the reference drive units; Means.
The short-circuit means short-circuits the same number or substantially the same number of the gate to which the signal of the first value read from the dummy cell is supplied and the gate to which the signal of the second value read from the dummy cell is supplied. I do.
[0022]
In addition, a plurality of the second bit lines and a plurality of the reference drive units are provided, and a synthesizing unit for synthesizing signals respectively applied to the plurality of second bit lines is further provided. The value of the data is determined according to the signal generated by the combining means.
The synthesizing means is provided with a reference signal having a first value given to the second bit line by the reference driving means and given to the other second bit line by another reference driving means. The same number or approximately the same number of reference signals having the second value are combined.
[0023]
The predetermined node is connected to a gate of the gain transistor, and a load capacitance of the first bit line driven by the gain transistor and a load capacitance of the second bit line driven by the dummy transistor are: The load capacitance of the node driven by the gain transistor is larger than that of the node.
Further, the first bit line is connected to a source of the gain transistor, and the second bit line is connected to a source of the dummy transistor.
Further, the memory cell includes any of a ferroelectric capacitor, a paraelectric capacitor, a magnetoresistive element, a chalcogenide resistive element, a MONOS transistor, and a stacked gate transistor.
The memory cell includes a ferroelectric capacitor having one electrode connected to an independent control line and the other electrode connected to a common node electrode. The gain transistor has a gate connected to the common node electrode. Field effect transistor.
[0024]
A data read method according to the present invention comprises: a memory cell for generating a read signal corresponding to a stored value at a predetermined node; and a gain cell for driving a first bit line based on the read signal generated at the node. This is a data reading method in a semiconductor memory device including a memory array in which a plurality of memory units having transistors are arranged. Driving a second bit line different from the first bit line according to the supplied reference potential by using a dummy transistor having the same size as the gain transistor; Determining a value of data read from the memory unit by comparing currents flowing through the two bit lines or potentials of the first bit line and the second bit line, respectively.
The data reading method according to the present invention further comprises: one or more memory cells for generating a read signal corresponding to a storage value at a predetermined node; and a gain transistor for driving a bit line based on the read signal generated at the node. Is a data reading method in a semiconductor memory device provided with a plurality of memory units having a plurality of memory units, each bit line corresponding to one or a plurality of the memory units. Then, the first bit line corresponding to the memory unit to be read is driven by the gain transistor, and the second bit line different from the first bit line is supplied to the supplied reference potential. And reading the data from the memory unit to be read by comparing the currents flowing through the first and second bit lines or the potentials of the first and second bit lines. Determining the value of the data.
[0025]
That is, in the present invention as described above, first, in order to cancel the influence of the variation in the threshold value of the gain transistor, a dummy transistor having the same size as the gain transistor of the read cell is provided in the vicinity or the like, and the bit line (second Bit line). In this way, a reference signal as a reference potential or a reference current is generated in the second bit line, and the read value is determined by directly or indirectly comparing the state of the reference signal with the state of the read bit line (first bit line). It is.
Specifically, the dummy transistor is provided in the same or adjacent cell array as the gain transistor connected to the memory cell to be accessed. Alternatively, a gain transistor and a dummy transistor may be arranged in a pair in each memory unit, and the memory units arranged in pairs in the vicinity may provide a reference potential to each other.
In general, the threshold value of a transistor (FET) has lot-to-lot and wafer-to-wafer dependence, and furthermore, there is strong inter-chip dependence within a wafer, and further location dependence within a chip. Therefore, there is almost no threshold difference between FETs arranged close to each other in the same chip.
Therefore, a dummy transistor is arranged near a gain transistor connected to a memory cell to be accessed, thereby driving a reference bit line and using the potential or current of the bit line for reference in read determination. This makes it possible to cancel out the influence of the variation in the threshold value of the gain transistor.
[0026]
Further, in order to cancel the variation and the temperature dependency of the signal generated from the memory cell, it is preferable to apply a read signal from the dummy cell having the same structure as the memory cell to the gate of the dummy transistor.
Further, in order to level out variations in signals from the dummy cells, the gate nodes of the plurality of dummy transistors are once short-circuited, and then the reference bit line is driven. Alternatively, the potentials or currents of the plurality of second bit lines are combined to generate a read determination potential or current.
In particular, a signal from a dummy cell in which a first value (for example, "1") is written and a second value (for example, "0") are written using one or more pairs of dummy transistors or reference bit lines. The same number of signals from the dummy cells may be short-circuited and applied to the gate of the dummy transistor, or a second bit line potential or current corresponding to the first value and another second bit line potential corresponding to the second value Alternatively, the leveling can be appropriately performed by combining the same number of currents.
[0027]
Furthermore, in order to cancel the dependence of the sense potential of the sense amplifier (read value determination means) on the distance between the memory cell and the sense amplifier, the dependence on the data holding time of the signal generated from the memory, and the dependence on the number of accesses, A dummy cell may be arranged for each row address, a dummy cell corresponding to the row address of the accessed memory cell may be accessed, and its read signal may be supplied to the dummy transistor.
[0028]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, first and second embodiments as a semiconductor memory device of the present invention will be described.
1 to 5 show the configuration of the first to fifth embodiments as a semiconductor memory device using a ferroelectric capacitor, and FIGS. 6 to 8 show the present invention. 5 shows another memory cell structure that can be employed.
In each figure, a word line is shown as a code including “WL” (for example, WLw1, WLr1, etc.), and a bit line is also shown as a code containing “BL”, and a plate line is also shown as a code containing “PL” Show.
For the word line WL and the plate line PL, a circuit section for driving those lines is not shown, but the word line WL is divided into an address which is accessed by a word line driving circuit (not shown) in a predetermined manner and a write / read operation. A corresponding voltage application is performed. A dummy word line (dWL) is also provided as a characteristic configuration of the embodiment, and the dummy word line dWL is also driven by a word line driving circuit.
The plate line PL (and the dummy plate line dPL) is applied with an address to be accessed in a predetermined manner by a plate line driving circuit (not shown) and a voltage application corresponding to writing / reading.
[0029]
<First embodiment>
This embodiment is a semiconductor memory device as a ferroelectric memory. FIG. 1 shows a configuration example.
As shown in FIG. 1, a plurality of memory units MU are repeatedly arranged in a bit line BL direction and a word line WL direction to form a memory array.
Each of the memory units MU11, MU12,... Has four ferroelectric capacitors C as an example. For example, the memory unit MU11 has capacitors C11 to C14. Of course, the number of capacitors in one memory unit MU is not limited to four. In particular, when the purpose is high integration, a larger number of capacitors are provided.
[0030]
Since the configuration inside each memory unit MU is the same, the configuration will be described using the memory unit MU11.
In the memory unit MU11, the plurality of ferroelectric capacitors C11 to C14 are memory cells each storing different data. One end of each of these capacitors C11 to C14 is connected to the common node electrode NE.
In addition, a gain transistor T11, a read switch T12, and a write switch T13 are provided by FETs.
The gain transistor T11 is an N-channel MOS-FET in a depletion state, and its gate is connected to the common node electrode NE. Further, one of the source / drain is connected to the ground (or a power supply line such as Vcc), and the other is connected to the bit line BL1 via a read switch T12 using an FET.
The gate of the read switch T12 is connected to the read word line WLr1.
The gate of the write switch T13 of the FET is connected to the write word line WLw1, and one of the source / drain is connected to the common node electrode NE and the other is connected to the bit line BL1.
The other ends of the capacitors C11 to C14 are connected to plate lines PL1, PL2, PL3, and PL4, respectively.
[0031]
The other memory units MU have the same internal configuration, but the connected word lines WL, bit lines BL, and plate lines PL are in accordance with the arrangement positions.
[0032]
In each memory unit arranged in the word line WL direction, the read word line WLr and the write word line WLw are alternately shared.
For example, in the memory units MU11 and MU13, the read word line WLr1 is connected to the gates of the read switches (T12 and the like) of these memory units MU11 and MU13, and the write word line WLw1 is connected to the write unit of each of the memory units MU11 and MU13. Connected to the gate of switch (T13 etc.).
Further, for example, in the memory units MU12 and MU14, the read word line WLr2 is connected to the gate of the read switch (T22 and the like) of each memory unit MU12 and MU14, and the write word line WLw2 is connected to the write of each memory unit MU12 and MU14. Connected to the gate of switch (T23 etc.).
[0033]
Each memory unit arranged in the direction of the bit line BL shares the bit line BL.
For example, a bit line BL1 is connected to the memory units MU11 and MU21 via a read switch T2 and a write switch T3.
Each of the bit lines BL (BL1, BL2,...) Is applied with a voltage by the sense amplifier 2 (2-1, 2-2,...) At the time of writing, and a potential is detected at the time of reading.
The sense amplifier 2 is a circuit that compares a potential of a bit line BL to be read with a reference signal and determines a read value.
[0034]
A dummy unit row 10 is provided in the word line direction in a memory array in which a plurality of memory units MU are arranged as described above.
In the dummy unit row 10, dummy units dU (dU1, dU2,...) Are formed corresponding to the respective bit lines BL1, BL2,.
In each dummy unit dU, there are provided dummy transistors dT11, dT21... Formed by FETs having the same structure and size as the gain transistors (T11, T21...) In the memory unit MU. are provided.
[0035]
Each gate of the dummy transistors dT11, dT21,... Is connected to the reference potential line Lref. Further, one of the source / drain is connected to ground (or a power supply line such as Vcc), and the other is connected to corresponding bit lines BL1, BL2,... Via dummy read switches dT12, dT22. It is connected.
A pair of dummy word lines dWL1 and dWL2 are arranged for dummy unit row 10, and the respective dummy units are connected alternately.
For example, in the dummy units dU1 and dU3, the gate of the dummy read switch (dT12 and the like) is connected to the dummy word line dWL1, and in the dummy units dU2 and dU4, the gate of the dummy read switch (dT22 and the like) is connected to the dummy word line dWL2. You.
[0036]
Further, reference potential generating circuit 1 for generating reference potential Vref is provided. The generated reference potential Vref is applied to the gates of the dummy transistors dT11, dT21,... Of each dummy unit dU via the reference potential line Lref.
The generated reference potential Vref is a potential set to an intermediate level of a signal generated at a node NE from a memory cell (capacitor C) holding data “1” and data “0”.
[0037]
In this example, as described above, a dummy unit dU having dummy transistors dT11, dT21,... Is arranged in a memory array in which a plurality of memory units MU are arranged.
Data reading in this case is performed as follows.
In this example, a plurality of sense amplifiers 2-1, 2-2,... Are arranged in the memory array. For each sense-up 2, a pair of memory unit MU and dummy unit dU are selected. It will be accessed.
[0038]
For example, a case is described in which data is read from the capacitor C11 of the memory unit MU11 and the capacitor C21 of the memory unit MU12.
In this case, the plate line PL11 is selected and driven to a high level. Then, different signals depending on the storage states of the capacitors C11 and C21 are applied to the gates of the respective gain transistors T11 and T21.
[0039]
When the read word line WLr1 and the dummy word line dWL2 are simultaneously turned on, the read switch T12 and the dummy read switch dT22 are turned on. Therefore, the gain transistor T11 drives the bit line BL1, and the dummy transistor dT21 is turned on. Drive the bit line BL2. Therefore, a read current according to the data of the capacitor C11 flows through the bit line BL1, and a reference current based on the reference potential Vref flows through the bit line BL2, so that the potentials of the two change.
This is compared and sensed by the sense amplifier 2-1 to determine the stored value of the memory cell (capacitor C11).
[0040]
Subsequently, both bit lines BL1 and BL2 are equalized, and then the read word line WLr2 and the dummy word line dWL1 are simultaneously turned on. Then, the read switch T22 and the dummy read switch dT12 are turned on, so that the gain transistor T21 drives the bit line BL2, and the dummy transistor dT11 drives the bit line BL1. Therefore, a read current according to the data of the capacitor C21 flows through the bit line BL2, and a reference current based on the reference potential Vref flows through the bit line BL1, and both potentials change.
This is compared and sensed by the sense amplifier 2-1 to determine the stored value of the memory cell (capacitor C21).
[0041]
As described above, in the case of the present example, when data is read from a memory unit on a certain bit line BL, a reference signal is obtained by the dummy unit dU on the other bit line BL corresponding to the same sense amplifier 2. Things.
Here, the gain transistors T11, T21,... And the dummy transistors dT11, dT21,... Exist in the same cell array and are located close to each other. Therefore, the difference between the threshold values is not affected by the variation between chips, between wafers, and between lots, and the effect of variation within a chip is extremely small. Therefore, these variations hardly affect the determination of the read value by the sense amplifier 2. That is, the read margin hardly deteriorates.
[0042]
In order to make the memory unit MU to be accessed and the dummy unit dU as close as possible, a plurality of dummy unit rows 10 may be provided in the same cell array, and the dummy unit row near the access unit may drive the reference bit line. .
[0043]
<Second embodiment>
FIG. 2 shows a configuration example of the second embodiment.
Although the first embodiment has a so-called folded bit line configuration, the second embodiment in FIG. 2 is an example of an open bit line configuration.
[0044]
Bit lines BL1-1 and BL1-2 are provided as bit lines for the sense amplifier 2-1 and bit lines BL2-1 and BL2-2 are provided as bit lines for the sense amplifier 2-2. , A pair of bit lines BL are formed in adjacent cell arrays with the sense amplifier 2 interposed therebetween.
[0045]
The illustrated memory units MU11, MU12, MU21, MU22 are memory units arranged on bit lines BL1-1, BL1-2, BL2-1, BL2-2, respectively.
Dummy units dU11, dU12, dU21, and dU22 are provided on the bit lines BL1-1, BL1-2, BL2-1, and BL2-2, respectively.
The configuration in each memory unit MU and the configuration in the dummy unit dU are the same as those in FIG.
The reference potential line Lref is provided as reference potential lines Lref1 and Lref2 for each cell array, and the reference potential generation circuit 1 applies the reference potential Vref.
[0046]
In the case of this configuration, the dummy unit dU for obtaining the reference signal corresponding to the memory unit MU to be accessed at the time of the read operation is arranged in the cell array adjacent to the sense amplifier 2.
[0047]
For example, when data is read from the capacitor C11 of the memory unit MU11, when the plate line PL11 is selected and driven to a high level, a different signal depending on the storage state of the capacitor C11 is applied to the gate of the gain transistor T11. You.
Here, by turning on the read word line WLr1 and the dummy word line dWL2 simultaneously, the gain transistor T11 drives the bit line BL1-1, and the dummy transistor dT21 drives the bit line BL1-2. Therefore, a read current according to the data of the capacitor C11 flows through the bit line BL1-1, and a reference current based on the reference potential Vref flows through the bit line BL1-2. , The stored value of the capacitor C11 is determined.
[0048]
When data is read from the capacitor C21 of the memory unit MU12,
The plate line PL21 is driven to a high level, and a different signal is applied to the gate of the gain transistor T21 depending on the storage state of the capacitor C21.
Here, by turning on the read word line WLr2 and the dummy word line dWL1 simultaneously, the gain transistor T21 drives the bit line BL1-2, and the dummy transistor dT11 drives the bit line BL1-1. Therefore, a read current according to the data of the capacitor C21 flows through the bit line BL1-2, and a reference current based on the reference potential Vref flows through the bit line BL1-1. , The stored value of the capacitor C21 is determined.
According to this embodiment, the same effect as that of the first embodiment can be obtained.
[0049]
<Third embodiment>
FIG. 3 shows the configuration of the third embodiment. This is an example of a configuration in which the dummy unit dU is provided in the memory unit MU.
[0050]
As in the case of FIG. 1, for example, in a pair of bit lines BL1 and BL2 corresponding to the sense amplifier 2-1, memory units MU11, MU21... Are arranged on the bit line BL1, and a memory is arranged on the bit line BL2. The units MU12, MU22,... Are arranged.
In each memory unit MU, a dummy unit dU (dU11, dU12, dU21, dU22) including a dummy transistor (dT11, dT21, etc.) and a dummy read switch (dT12, dT22, etc.) is provided. I have.
That is, the memory unit MU and the dummy unit dU are provided at a ratio of 1: 1.
The reference potential Vref is supplied by the reference potential generation circuit 1 to the gates of the dummy transistors (dT11, dT21, etc.) of each dummy unit dU, as in the above-described embodiments.
[0051]
The write word line WLw and the read word line WLr are alternately shared by the memory units MU arranged in the word line direction (memory units MU adjacent in the word line direction are connected to another word line WL). Is the same as that of FIG. 1, but the dummy word line dWL is not provided for the dummy unit dU in each memory unit MU, and the read word line WLr is shared as the dummy word line.
For example, the gate of the dummy read switch dT12 of the memory unit MU11 is connected to the read word line WLr2 corresponding to the adjacent memory unit (for example, MU12), and the gate of the dummy read switch dT22 of the memory unit MU12 is connected to the adjacent memory unit. The read word line WLr1 corresponding to (for example, MU11) is connected.
[0052]
In such a configuration, for example, a pair of memory units arranged on a pair of bit lines, for example, the memory units MU11 and MU12 are arranged adjacent to each other or very close to each other.
Then, at the time of read access to the memory cell, the respective dummy units dU operate in correspondence with each other.
[0053]
For example, a case is described in which data is read from the capacitor C11 of the memory unit MU11 and the capacitor C21 of the memory unit MU12.
In this case, the plate line PL11 is selected and driven to a high level. Then, different signals depending on the storage states of the capacitors C11 and C21 are applied to the gates of the respective gain transistors T11 and T21.
[0054]
Here, by turning on the read word line WLr1, the gain transistor T11 drives the bit line BL1, and the dummy transistor dT21 drives the bit line BL2. Therefore, a read current according to the data of the capacitor C11 flows through the bit line BL1, and a reference current based on the reference potential Vref flows through the bit line BL2, so that the potentials of the two change. This is compared and sensed by the sense amplifier 2-1 to determine the stored value of the memory cell (capacitor C11).
[0055]
Subsequently, both bit lines BL1 and BL2 are equalized, and then the read word line WLr2 is turned on. Then, the gain transistor T21 drives the bit line BL2, and the dummy transistor dT11 drives the bit line BL1. Therefore, a read current according to the data of the capacitor C21 flows through the bit line BL2, and a reference current based on the reference potential Vref flows through the bit line BL1, and both potentials change. This is compared and sensed by the sense amplifier 2-1 to determine the stored value of the memory cell (capacitor C21).
[0056]
In this example, the memory units MU paired as described above provide a reference potential to each other. The gain transistor and the dummy transistor (for example, T11 and dT21, or T21 and dT11) which operate simultaneously are located very close to each other, and the influence of the in-chip variation almost disappears, and the threshold difference is reduced. It becomes 10 mV or less. Therefore, the threshold variation of the gain transistor (T11 or the like) does not degrade the read margin.
[0057]
<Fourth embodiment>
Incidentally, in order to secure a sufficient read margin, it is important to adjust the reference voltage Vref applied to the gates of the dummy transistors dT11, dT21,.
Many memory elements, such as ferroelectric capacitors, have temperature dependence on the read signal level. In addition, since the characteristics of the memory element itself vary among chips, between chips, between wafers, and between lots, when the reference potential generation circuit 1 supplies the reference potential Vref as a fixed potential, the above variations all lead to margin deterioration.
[0058]
Considering this, it is desirable that the reference voltage Vref applied to the gates of the dummy transistors dT11, dT21,... Also has a function of canceling the above-described variation in the memory elements.
As a countermeasure, it is effective to use a dummy cell having the same structure as the memory cell as a means for generating the reference potential Vref, as seen in a normal DRAM or FeRAM which is not a gain type memory.
That is, if the reference potential Vref is generated using the dummy cell, the reference potential also has the characteristic variation and the temperature dependency between chips, wafers, and lots of the memory element, similarly to the read signal from the memory cell. Therefore, these are offset.
[0059]
However, as a result of the study, it has been clarified that the following two points need to be paid attention when combining the gain type memory and the dummy cell.
First, in a gain-type memory, a small signal from a very small memory element is amplified by a gain FET, so that the in-chip characteristic variation of the dummy cell itself becomes an important margin deterioration factor.
[0060]
Next, in a gain-type memory, the load capacitance driven by a memory cell is generally very small, and the parasitic capacitance of the memory cell itself greatly contributes to the overall load capacitance. Therefore, unlike a normal memory, the signal from the memory cell does not depend linearly on the size of the memory cell.
For example, in a ferroelectric memory, if the area is A, the polarization amount per unit area is P, the paraelectric component per unit area (parasitic capacitance of the cell) is Cs, and the load capacitance to be driven is Cb, the data is read from the memory cell. The signal S is
S = A · P / (A · Cs + Cb)
It is.
[0061]
In the case of a normal ferroelectric memory, the load capacitance Cb to be driven is sufficiently larger than “A · Cs”.
S = AP / Cb
That is, the signal S is substantially proportional to the area A. Therefore, an intermediate signal of "1" and "0" can be easily generated by adjusting the area of the dummy cell, and this method is almost used in actual products. However, in the gain type memory, on the contrary, Cb is very small.
S = AP / (ACs)
That is, the area dependency of the signal S is almost eliminated. Here, a simple one-capacitor connection type is taken as an example, but the same applies to a case where a memory unit is composed of a plurality of capacitors as in the above embodiment. That is, it is very difficult to adjust the signal level by changing the cell area in the gain type memory. For this reason, it is not appropriate to generate a reference potential using a memory cell in the same manner as a normal memory.
[0062]
Therefore, a fourth embodiment in which the dummy cell is used to generate the reference potential Vref in consideration of such points will be described with reference to FIG.
In FIG. 4, only MU11 to MU14 are shown as the memory units MU. However, the configuration of these memory units MU and memory units MU (not shown) (for example, the memory units MU21 to MU24 in FIG. The connection states of the memory unit MU and the word lines WL, bit lines BL, and plate lines PL are the same as in FIG. 1 described above.
In the example of FIG. 1, the dummy unit row 10 is shown. However, in the case of FIG. 4, the dummy unit row 10 has a configuration corresponding to each bit line BL1, BL2,. dU1, dU2, dU3, dU4,... are provided.
That is, each dummy unit dU is configured to have a dummy capacitor dC having the same size as the capacitor C of the memory unit MU.
[0063]
For example, the dummy unit dU1 will be described. The dummy unit dU1 has four dummy capacitors dC11 to dC14. These are capacitors having the same size as the capacitor C of the memory unit MU.
One end of each of the dummy capacitors dC11 to dC14 is connected to the common node electrode dNE.
Dummy plate lines dPL1 to dPL4 are provided, and the other ends of dummy capacitors dC11 to dC14 are connected to dummy plate lines dPL1 to dPL4, respectively.
Similarly, dummy capacitors dC are provided for the other dummy units dU2, dU3,. One end of each dummy capacitor dC is connected to the common node electrode dNE in the dummy unit dU, and the other end is connected to each of the dummy plate lines dPL1 to dPL4.
[0064]
In each dummy unit dU, dummy transistors dT11, dT21... Formed by FETs having the same structure and size as the gain transistors (T11, T21...) In the memory unit MU are provided. Are provided. Dummy read switches dT12, dT22,. Further, dummy write switches dT13, dT23... Are provided.
[0065]
In each dummy unit dU, each gate of each dummy transistor dT11, dT21,... Is connected to a common node electrode dNE. One of the source / drain is connected to ground (or a power line such as Vcc), and the other is connected to corresponding bit lines BL1, BL2,... Via dummy read switches dT12, dT22. It is connected.
[0066]
A pair of dummy read word lines dWLr1 and dWLr2 and a pair of dummy write word lines dWLw1 and dWLw2 are arranged for a dummy unit row in which such dummy units dU are arranged. Connected alternately.
For example, in the dummy units dU1 and dU3, the gate of the dummy read switch (such as dT12) is connected to the dummy read word line dWLr1, and the gate of the dummy write switch (such as dT13) is connected to the dummy write word line dWLw1.
On the other hand, in the dummy units dU2 and dU4, the gate of the dummy read switch (dT22 and the like) is connected to the dummy read word line dWLr2, and the gate of the dummy write switch (dT23 and the like) is connected to the dummy write word line dWLw2. .
[0067]
An equalizing transistor Teq for short-circuiting each common node electrode dNE is provided between dummy units dU arranged on a pair of bit lines (for example, bit lines BL1 and BL2) corresponding to the same sense amplifier 2.
For example, the equalizing transistor Teq1 is a switch for short-circuiting the common node electrodes dNE of the dummy units dU1 and dU2 in the bit lines BL1 and BL2, and the equalizing transistor Teq2 is a switch for each of the dummy units dU3 and dU4 in the bit lines BL3 and BL4. This is a switch for short-circuiting the common node electrode dNE.
The equalizing signal dEQ is supplied from the equalizing control section 11 to the gate of each equalizing transistor Teq.
[0068]
As described above, in the configuration of FIG. 4, the dummy unit dU has the same configuration as the memory unit MU including the capacitor size.
Then, a dummy unit pair that can be short-circuited by the equalizing transistor Teq is connected to the same bit line pair as the memory unit MU (a pair of bit lines corresponding to the same sense amplifier 2).
In the dummy unit pair, that is, two dummy units connected by the equalizing transistor Teq, data “0” is stored on one side and data “1” is stored on the other side in the dummy capacitor pair sharing the dummy plate line dPL with each other. Have been.
For example, in the dummy unit pair of the dummy units dU1 and dU2, the dummy capacitors dC11 and dC21 share the dummy plate line dPL1, but one of the dummy capacitor pair (dC11 and dC21) is “0” and the other is “1”. Is done.
Similarly, one of the other dummy capacitor pairs (dC12 and dC22, dC13 and dC23, dC14 and dC24) is "0" and the other is "1".
[0069]
In such a configuration, for example, data reading from the capacitor C11 of the memory unit MU11 and the capacitor C21 of the memory unit MU12 is performed as follows.
First, when the plate line PL11 is selected and set to the high level, different signals are applied to the gates of the gain transistors T11 and T21 according to the storage states of the capacitors C11 and C21.
At this time, the dummy plate line dPL1 is selected at the same time, and signals read from the dummy capacitors dC11 and dC21 are applied to the gates of the dummy transistors dT11 and dT21, respectively. At this time, one of the signals applied to the gates of the dummy transistors dT11 and dT21 is a signal corresponding to "0" and the other is a signal corresponding to "1".
[0070]
Here, the equalizing control unit 11 applies the equalizing control signal dEQ to the gate of the equalizing transistor Teq. Then, by turning on the equalizing transistor Teq1, the common node electrode dNE of the dummy unit dU1 and the common node electrode dNE of the dummy unit dU2 are short-circuited. That is, each gate node of the dummy transistors dT11 and dT21 is short-circuited.
As a result, an intermediate value of the cell signals “0” and “1” is applied to the gates of the dummy transistors dT11 and dT21.
[0071]
Here, by turning on the read word line WLr1 and the dummy read word line dWLr2 at the same time, the gain transistor T11 drives the bit line BL1, and the dummy transistor dT21 drives the bit line BL2. The read current and the reference current flow through BL2, and the potentials of both of them fluctuate. This is compared and sensed by the sense amplifier 2-1 to determine the stored value of the memory cell (capacitor C11).
[0072]
Further, after equalizing both bit lines BL1 and BL2, the read word line WLr2 and the dummy read word line dWLr1 are simultaneously turned on, so that the gain transistor T21 drives the bit line BL2 and the dummy transistor dT11 drives the bit line BL1. , And a read current and a reference current flow through each of the bit lines BL2 and BL1, and the potentials of both of them fluctuate. This is compared and sensed by the sense amplifier 2-1 to determine the stored value of the memory cell (capacitor C21).
[0073]
In other capacitor pairs (capacitor C12 and capacitor C22, capacitor C13 and capacitor C23, and capacitor C14 and capacitor C24), dummy capacitor pairs (dummy capacitor dC12 and dummy capacitor dC22, dummy capacitor dC13) in which data are stored complementarily, respectively. And the dummy capacitor dC23, and the dummy capacitor dC14 and the dummy capacitor dC24).
[0074]
In such a fourth embodiment, an intermediate reference potential between “0” and “1” can be accurately generated in the gain memory. In addition to the same effects as those of the first to third embodiments, furthermore, the temperature dependency of the memory cell itself and the deterioration of the margin due to the variation in the characteristics among chips, chips, wafers, and lots are also prevented. You can do it.
[0075]
In this example, the gates of the pair of dummy transistors (for example, dT11 and dT21) are short-circuited. However, it is desirable that the gates of a plurality of pairs of dummy transistors be short-circuited. That is, the same number or substantially the same number of short-circuits are made between the gate of the dummy transistor that has received the signal from the dummy capacitor storing “0” and the gate of the dummy transistor that has received the signal from the dummy capacitor storing “1”. In this case, the potential applied to the gate of each dummy transistor is leveled, and the variation in the reference potential itself due to the variation in the characteristics of the dummy capacitor dC can be significantly reduced.
[0076]
By the way, as described above, in a normal DRAM or FeRAM which is not a gain type memory, an example using a dummy cell as a means for generating the reference potential Vref has been proposed. In these, the reference potential Vref is set to an appropriate value by adjusting the area of the dummy capacitor. However, as described above, in the gain-type memory according to the present example, the adjustment of the area of the dummy capacitor dC has no significant advantage over the generation of the reference potential Vref. That is, in the gain type memory, it is difficult to set Vref to an appropriate value by adjusting the area of the dummy capacitor, and a method similar to that of a normal DRAM or FeRAM is not appropriate.
Therefore, as in the configuration example of FIG. 4, in a gain type memory, it is appropriate to adopt a reference potential generation method based on “0” and “1” synthesis. And a synergistic effect for realizing a highly reliable ultra-highly integrated memory.
[0077]
Further, in this embodiment, as in the first embodiment, a method of generating a reference potential is described by taking a so-called folded bit line configuration as an example, but the open bit line configuration as in the second embodiment is described. Needless to say, a similar method is effective.
[0078]
Also, in the gain type memory, by utilizing the fact that the area dependency is minute, the area of the ferroelectric capacitor as the dummy capacitor dC is made larger than that of the capacitor C as the normal memory cell, and the dummy capacitor The effect of variation in dC can be further reduced.
[0079]
<Fifth embodiment>
In the fourth embodiment, “0” and “1” synthesis is realized by shorting the gate node of the dummy transistor. Although this is a method of easily assembling an access sequence, it is necessary to embed the equalizing transistor Teq in a fine cell array in terms of layout, which is disadvantageous in that point.
On the other hand, the same effect can be obtained by generating reference potentials or reference currents of “0” and “1” on individual reference bit lines and combining them to generate an intermediate reference potential.
FIG. 5 shows a fifth embodiment of the present invention in which the data retention time of the read signal from the capacitor C (and the dummy capacitor dC) as a memory cell and the dependence on the number of times of rewriting are taken into consideration.
[0080]
In the example of FIG. 5, the memory units MU are arranged in the word line direction and the bit line direction, respectively, as in FIGS.
In this example, a pair of reference bit lines dBL1 and dBL2 are arranged, and each dummy unit dU is arranged on the reference bit lines dBL1 and dBL2.
Are arranged on the reference bit line dBL1, and the dummy units dU12, dU22... Are arranged on the reference bit line dBL2.
Each dummy unit dU has the same configuration as in the case of FIG. For example, the dummy unit dU11 has dummy capacitors dC11 to dC14, a dummy transistor dT11, a dummy read switch dT12, and a dummy write switch dT13.
[0081]
Each dummy unit dU shares the word line WL with the memory units MU arranged in the word line direction.
For example, in the dummy units dU11 and dU12, the read word line WLr1 connected to the gate of each of the read switches (T12 and the like) of the memory units MU11, MU12 and MU13 is connected to the gate of each of the dummy read switches dT12 and dT22.
For example, in the dummy units dU11 and dU12, the gate of each of the dummy write switches dT13 and dT23 has the write word line WLw1 connected to the gate of each of the write switches (T13 and the like) of the memory units MU11, MU12 and MU13. Connected.
[0082]
Each dummy unit dU shares the plate line PL with the memory units MU arranged in the word line direction.
For example, in the dummy units dU11 and dU12, plate lines PL11, PL12, PL13 and PL14 for the respective capacitors C of the memory units MU11, MU12 and MU13 are connected to the respective dummy capacitors dC.
[0083]
In this case, two dummy units dU arranged in the word line direction form a pair of dummy units.
In the two dummy units forming the dummy unit pair, data “0” is stored on one side and data “1” is stored on the other side in the dummy capacitor pair sharing the plate line PL with each other.
For example, in the dummy unit pair of the dummy units dU11 and dU12, the dummy capacitors dC11 and dC21 share the plate line PL11. One of the dummy capacitor pair (dC11 and dC21) is "0" and the other is "1". You.
Similarly, one of the other dummy capacitor pairs (dC12 and dC22, dC13 and dC23, dC14 and dC24) is "0" and the other is "1".
[0084]
Further, since each dummy capacitor dC shares the plate line PL with the capacitor C of the memory unit MU, a dummy capacitor pair is provided for each ROW address, and “0” is set on one side and “D” is set on the other side. 1 "is stored.
[0085]
The pair of reference bit lines dBL1 and dBL2 can be short-circuited by the equalizing transistor Teq2. When the equalizing transistor Teq1 is turned on, a combined signal of the reference bit lines dBL1 and dBL2 is supplied to the sense amplifiers 2-1, 2-2,....
[0086]
A read operation in such a configuration will be described by taking data read from a capacitor C connected to the plate line PL11, such as the capacitor C11 of the memory unit MU11, as an example.
When the plate line PL11 is selected and set to a high level, a different signal is applied to the gate of the gain transistor of each memory unit MU corresponding to the storage state of each cell capacitor connected thereto. For example, a signal from the capacitor C11 is applied to the gate of the gain transistor T11.
At this time, signals read from the dummy capacitors dC11 and dC21 are simultaneously applied to the gates of the dummy transistors dT11 and dT21. In this case, one of the signals applied to the gates of the dummy transistors dT11 and dT21 is a signal corresponding to “0”, and the other is a signal corresponding to “1”.
[0087]
Next, when the read word line WLr1 is turned on, each gain transistor (T11 and the like) of each of the memory units MU11, MU12, and MU13 drives the bit lines BL1, BL2, and BL3, respectively. Further, the dummy transistors dT11 and dT21 of the dummy units dU11 and dU12 drive the reference bit lines dBL1 and dBL2, respectively.
Here, when the equalizing control section 11 turns on the equalizing transistors Teq1 and Teq2 by the equalizing control signal dEQ to short-circuit the reference bit lines dBL1 and dBL2, the potentials of the two are combined and the short-circuited reference bit lines dBL1 and dBL2 are put on the shorted reference bit lines dBL1 and dBL2. A reference potential intermediate between "1" and "0" is generated. The current flowing through both is the sum of the read currents of "1" and "0".
This potential is distributed as a reference potential to the adjacent sense amplifier groups 2-1, 2-2, 2-3. Each of the sense amplifiers 2-1, 2-2, 2-3 compares the read potential of the bit line BL1, BL2, BL3 connected thereto with the reference potential distributed from the reference bit line pair dBL1, dBL2. The read value is determined.
In this way, the data of the memory cell such as the capacitor C11 is determined by the sense amplifier 2.
[0088]
In such an embodiment, the same effect as in the fourth embodiment can be obtained, and the read margin can be improved.
Further, according to this example, a dummy cell (dummy capacitor dC) is provided for each row address, and a dummy cell (dummy capacitor dC) corresponding to the row address of the accessed memory cell (capacitor C) is simultaneously accessed. Become. That is, each dummy capacitor dC is always accessed at the same time as the capacitor C row of the corresponding ROW address. Accordingly, the data retention time can be set to be equal to that of the corresponding capacitor C on the same row (on the same plate line PL), and the number of accesses is the same.
Further, the distance between the sense amplifier 2 and the gain transistor (T11 or the like) is equal to the distance between the sense amplifier 2 and the dummy transistor (dT11 or the like).
Therefore, the data retention dependency, the access count dependency, and the bit line voltage drop are all canceled out, and the effect of improving the read margin becomes more remarkable.
[0089]
Here, the reference signal is distributed as a voltage to each of the sense amplifiers 2-1, 2-2,..., But the current is mirrored to １ ／ and distributed as a reference current. A configuration in which the read determination is performed by comparing the current flowing through the bit line BL with the reference current may be employed.
[0090]
Although a pair of reference bit lines dBL1 and dBL2 are short-circuited here, a plurality of pairs of reference bit lines dBL may be further arranged at regular intervals for a fixed number of sense amplifiers 2 and short-circuited together. That is, the same or substantially the same number of reference bit line signals from which “0” data has been read and the number of reference bit line signals from which “1” data have been read are short-circuited. In this way, the reference potential or the current is leveled, and the variation in the reference potential or the reference current due to the variation in the characteristics of the dummy capacitor can be greatly reduced.
[0091]
Incidentally, such an arrangement of the dummy units is not appropriate for a normal non-gain type ferroelectric memory.
When the reference potential and the current are distributed from the reference bit line dBL to the plurality of sense amplifiers 2 as described above, the wiring pattern of the access bit line BL of the distribution destination is greatly different from that of the reference bit line dBL of the distribution source.
Therefore, some imbalance in load capacity cannot be avoided. Even if the imbalance is adjusted by adding a capacitor or the like to the bit line BL, it is difficult to achieve perfect balance, and it is necessary to adjust the value to the side with the larger load capacity. This is because, if it is attempted to drive it directly with the fine signal of the memory cell, on the contrary, a large margin deterioration is caused. This tendency is particularly remarkable in a case where a signal is generated on the bit line BL with a fixed amount of charge from a capacitor, such as a DRAM or a ferroelectric memory.
On the other hand, in the case of the gain type memory in which the bit line BL is driven by the gain transistor as in this example, the driving capability is much higher than the direct drive from the memory cell, so that the capacity of the bit line BL is larger than that of the normal memory. The influence of the imbalance of the bit line capacitance can be relatively reduced.
[0092]
In this case, it is desirable to set the bit line capacitance larger than the load capacitance of the gate node of the gain transistor (T11 or the like) directly driven by the memory cell.
Further, if an appropriate MOS capacitor or the like is connected to the bit line BL for adjusting the capacitance imbalance, more stable reading can be performed.
[0093]
Further, if the drain side of the gain transistor is connected to the power supply and the source side is connected to the bit line BL, the potential Vb of the bit line BL is independent of the bit line capacitance.
Vb = Vg-Vth
Converges to Vg is the signal level applied to the gate of the gain FET, and Vth is the threshold value of the gain transistor.
Therefore, it is hardly affected by the unbalance of the bit line capacitance.
[0094]
As described above, in the gain type memory, the influence of the imbalance of the bit line pattern can be significantly reduced, and the above-described dummy unit configuration can be effectively used.
However, if the distribution of the reference voltage and the reference current is performed to an excessively large number of sense amplifiers 2, the imbalance of the wiring length and the like cannot be ignored. Therefore, the distribution should be made in consideration of the trade-off between the area overhead due to the dummy unit and the imbalance of the bit line capacitance. Specifically, every four to 64 sense amplifiers, a column of the dummy unit pair, And a pair of reference bit lines dBL.
[0095]
It is desirable to further combine the potentials or currents of a plurality of pairs of reference bit lines dBL. For example, if 1024 sense amplifiers 2 are arranged in a cell array, reference bit line pairs are arranged every 32 sense amplifiers. At this time, 32 pairs of reference bit lines are inserted. If all of them are short-circuited, the potentials of a total of 64 reference bit lines are combined. At this time, the fluctuation range of the reference potential due to the characteristic variation of the dummy capacitor dC is reduced to (1/8) which is the square root of (1/64) as compared with the case where a single reference bit line is used. Is done. Therefore, it is more advantageous for improving the read margin.
[0096]
<Example of other gain type memory to which the present invention can be applied>
In each of the above embodiments, the case where the memory cell is formed of a ferroelectric capacitor is taken as an example. In this type of gain type memory, the load capacitance driven by the selected cell capacitor is governed by the characteristics of itself and the non-selected ferroelectric capacitor, which contain some weakly inverted ferroelectric components and The value also has temperature dependence. Therefore, as in the fourth and fifth embodiments, a dummy unit having the same structure as that of the memory unit is provided, the reference signal is generated by the dummy capacitor, and the dummy load is used as the driving load. Dependencies can also be offset.
[0097]
However, the application range of the present invention is not limited to a memory in which a memory cell is formed of a ferroelectric capacitor. A signal generated by a minute memory cell is given to the gate of a FET (gain transistor), and the FET is used to generate a bit line. The present invention can be applied to any gain type memory that reads data by driving the BL.
6 to 8 show examples of other gain memories to which the present invention can be applied. In each figure, the same reference numerals as those in FIG. 9 denote the gain transistor as T1, the read switch as T2, and the write switch as T3.
[0098]
FIG. 6 shows a DRAM in which the paraelectric capacitor C30 is a memory cell. The input signal to the node NE connected to the gate of the gain transistor T1 changes depending on the presence or absence of the charge stored in the capacitor C30.
Also in this case, since the parasitic capacitance of the memory cell itself accounts for a large proportion of the load capacitance, it is difficult to generate an appropriate reference potential Vref by adjusting the size. Further, there is a problem that the signal level changes depending on the data holding time. Therefore, it is very effective to adopt a configuration of the same method as in the above-described embodiment, obtain an intermediate reference signal by combining "1" and "0", or provide a dummy cell for each ROW address.
[0099]
In addition to the type in which the gate of the gain transistor is driven by the capacitor as described above, there is also a type in which a signal potential is applied to the gate of the gain transistor using a storage resistor element. An example is shown in FIG.
The resistance element R1 is a memory cell having a different resistance value according to the data storage state. On the other hand, the resistance element R2 is a reference resistance element having a fixed resistance value, and is formed of a MOS transistor operated in a linear region, a diffusion layer, a polysilicon layer, or the like.
The input signal Vg to the node NE connected to the gate of the gain transistor T1 is determined by the resistance division of the resistance elements R1 and R2. Assuming that their resistance values are r1 and r2,
Vg = Vcc · r1 / (r1 + r2)
It is.
In this example, the storage resistance element R1 is connected to the ground side and the reference resistance element R2 is connected to the Vcc side, but both may be interchanged.
[0100]
For example, a magnetic junction can be used for the resistance element R1. A magnetic junction is an element in which a tunnel barrier is sandwiched between a magnetic film that stores data by changing the spin direction and a magnetic film that fixes the spin direction. The resistance value changes according to the spin direction of the magnetic film for storage. Examples of a memory using the same are described in ISSCC (IEEE INTERNAL SOLID-STATE CIRCUITS CONFERENCE) 2000, article numbers 7.2 (R. Schuerlein, P. 128) and 7.3 (M. Durlam, P. 130). It has been described.
[0101]
Further, for example, a chalcogenide film resistor can be used for the resistance element R1. Since the resistivity of the chalcogenide film changes when the crystal state changes between polycrystalline and amorphous, the film may be sandwiched between electrodes to form a resistance element. An example of a memory using the same is described in ISSCC 2002, article number 12.4 (M. Gill, p. 202).
[0102]
In addition, a laminated gate transistor or a nitride film gate transistor can be used as the resistance element R1. These transistors are used as an EPROM, and the threshold value changes according to the storage state, so that the resistance value changes. If these are connected in series, independent data can be stored in each of them.
[0103]
In such an example of the resistance type memory, there is a problem that the temperature characteristic of the reference resistance element R2 is different from the temperature characteristic of the resistance storage element R1 as a memory cell. Therefore, it is difficult to obtain an appropriate reference potential Vref over a wide temperature range by the technique of adjusting the resistance value by adjusting the cell size. Further, there is a problem that the resistance value of the cell changes according to the data holding time, and the signal level changes. Therefore, the method of the present invention in which "1" and "0" are combined to obtain an intermediate reference signal, or a dummy cell is provided for each ROW address, is as effective as the case where a capacitor is used for a cell.
[0104]
Further, a constant current source may be used instead of the reference resistance element. An example is shown in FIG. An N-channel MOS (T30) operating as a constant current source is connected to the storage resistance element R1. The gate is supplied with a fixed potential as a constant current source so as to operate in a saturation region. At this time, the signal Vg applied to the node NE connected to the gate of the gain transistor T1 is as follows, assuming that the resistance value of R1 is r1 and the current flowing through T1 is i1.
Vg = Vcc− (r1 · i1)
It is.
Even in the case of such a memory, the method of the present invention in which "1" and "0" are combined to obtain an intermediate reference signal, or a dummy cell is provided for each ROW address, in order to cope with variations in the resistance value of the cell. Is valid.
[0105]
The embodiment and the example of the gain type memory to which the present invention can be applied have been described above, but the present invention can be further applied.
For example, in the above embodiment, a case has been assumed in which each memory cell stores one bit, that is, a binary value of “0” or “1”. However, the present invention can be similarly applied to a case where so-called multi-values are stored. For example, when each cell stores 2 bits, first to fourth four-level signals are given to the gate of the gain transistor in ascending order of level, and it is necessary to make a determination.
In this case as well, a dummy cell and a dummy transistor are used to generate a first reference potential from, for example, the synthesis of the second signal and the third signal, and the readout cell is used first to cause the read cell to operate in the first and second lower groups. Alternatively, it is determined which of the third and fourth upper groups belongs.
Next, a second reference potential is generated by combining the first signal and the second signal, and a third reference potential is generated by combining the third signal and the fourth signal. Then, level determination in the lower group is performed using the second reference potential, and level determination in the upper group is performed using the third reference potential. In this way, the read value of each cell can be uniquely determined.
[0106]
【The invention's effect】
As can be seen from the above description, according to the present invention, the following effects can be obtained.
In general, the threshold value of the gain transistor (FET) has lot-to-lot and wafer-to-wafer dependence, and also has a strong inter-chip dependence within the wafer and a location dependence within the chip. Therefore, there is almost no threshold difference between FETs arranged close to each other in the same chip. Therefore, as in the present invention, a dummy transistor of the same size is arranged near a gain transistor connected to a memory cell to be accessed, and the second bit line used as a reference is driven by the dummy transistor. If the potential or current of the second bit line is used as a reference signal for read determination, it is possible to cancel the influence of threshold variation of the gain transistor, and as a result, it is possible to greatly improve the read margin.
[0107]
Further, by supplying a signal from the dummy cell having the same structure as that of the memory cell of the memory unit to the dummy transistor, it is possible to cancel the characteristic variation occurring between chips, wafers, and lots of the memory element. Further, the same temperature dependence as the read signal from the memory cell occurs in the gate potential of the dummy transistor. Therefore, it is possible to prevent margin deterioration due to temperature dependency. This can also improve the read margin.
[0108]
Further, by short-circuiting the gate nodes of the plurality of dummy transistors once and then driving the bit line used as a reference, variations in the signal from the dummy cells within the chip, variations in the reference potential caused by variations in the remaining dummy transistors, etc. Variations on the reference current side can be reduced by statistical leveling.
A similar effect can also be achieved by combining the potentials or currents of a plurality of second bit lines and using them as a reference signal.
In particular, a signal from a dummy cell in which a first value (eg, “1”) is written using a pair or a plurality of pairs of dummy transistors or a plurality of second bit lines for reference, and a second value (eg, “ 0 ") is written to the gate of the dummy transistor by short-circuiting the signal from the dummy cell, or a bit line potential or current according to the first value and a bit line potential or current according to the second value. , The reference signal level intermediate between the reading of the first value and the reading of the second value can be accurately generated, and the leveling can be appropriately realized. Thereby, the read margin can be improved.
This is particularly effective in a gain-type memory in which it is difficult to generate an appropriate intermediate signal by adjusting the capacitor size.
If the area of the ferroelectric capacitor of the dummy cell is made larger than that of a normal memory cell, the influence of the variation of the dummy capacitor can be further reduced.
[0109]
Furthermore, by connecting the bit line to the source side of the gain transistor, the final bit line potential is determined only by the gain transistor, the threshold value, and the signal potential from the cell applied to its gate, and the influence of the bit line capacitance Not receive. Therefore, it is possible to reduce the influence of the difference in bit line capacitance due to the pattern difference between the second bit line used for reference and the first bit line for reading. Alternatively, by increasing the bit line capacitance itself, that is, by making the bit line capacitance larger than the capacitance of the node driven by the memory cell, the influence of the pattern difference can be relatively reduced.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of a configuration example according to a first embodiment of the present invention.
FIG. 2 is an explanatory diagram of a configuration example according to a second embodiment of the present invention.
FIG. 3 is an explanatory diagram of a configuration example according to a third embodiment of the present invention.
FIG. 4 is an explanatory diagram of a configuration example according to a fourth embodiment of the present invention.
FIG. 5 is an explanatory diagram of a configuration example according to a fifth embodiment of the present invention.
FIG. 6 is an explanatory diagram of an example of a gain type memory to which the present invention can be applied.
FIG. 7 is an explanatory diagram of an example of a gain type memory to which the present invention can be applied.
FIG. 8 is an explanatory diagram of an example of a gain type memory that can employ the present invention.
FIG. 9 is an explanatory diagram of a configuration of a gain type memory.
FIG. 10 is an explanatory diagram of a configuration of a gain memory that performs reading using a reference potential.
[Explanation of symbols]
1 Reference potential generation circuit, 2, 2-1, 2-2,... Sense amplifier, 10 dummy unit row, 11 Equalization control unit, MU, MU11, MU12,. .. Write word lines, WLr1, WLr2 ... Read word lines, BL, BL1, BL2 ... Bit lines, PL, PL11, PL12 ... Plate lines, T11, T21 Gain transistors, T12, T22 Read Switch, T13, T23 Write switch, dT11, dt12 Dummy transistor, dU, dU1, dU2 Dummy unit

Claims (13)

A memory unit having one or more memory cells for generating a read potential according to a stored value at a predetermined node and a gain transistor for driving a first bit line based on the read potential generated at the node, In a semiconductor memory device including a plurality of arranged memory arrays,
A second bit line;
Reference driving means for driving the second bit line by a dummy transistor having the same size as the gain transistor based on a reference potential;
Data read from the memory unit by comparing both currents flowing through the first bit line and the second bit line, respectively, or both potentials of the first bit line and the second bit line. Reading value determining means for determining the value of
A semiconductor memory device comprising: The second bit line is provided corresponding to one or a plurality of the memory units,
The reference driving means is provided corresponding to the second bit line,
The read value determination means drives the first bit line corresponding to the memory unit to be read by the gain transistor, and drives the second bit line by the reference drive means. 2. The semiconductor memory device according to claim 1, wherein the value of the data is determined by comparing a current flowing through both bit lines or a potential of both bit lines. Further comprising a dummy cell having the same structure as the memory cell,
2. The semiconductor memory device according to claim 1, wherein the reference potential is a potential of a signal read from the dummy cell and is supplied to a gate of the dummy transistor. Short-circuiting means including a plurality of the second bit lines and a plurality of reference driving means for driving the corresponding second bit lines, and short-circuiting gates of a plurality of dummy transistors included in each of the reference driving means. 4. The semiconductor memory device according to claim 3, comprising: The short-circuit means short-circuits the same number or substantially the same number of the gate to which the signal of the first value read from the dummy cell is supplied and the gate to which the signal of the second value read from the dummy cell is supplied. 5. The semiconductor memory device according to claim 4, wherein: A plurality of the second bit lines and the reference driving means are provided,
A synthesizing means for synthesizing signals respectively applied to the plurality of second bit lines;
2. The semiconductor memory device according to claim 1, wherein said read value determination means determines the value of said data in accordance with a signal generated by said synthesis means. The synthesizing means is provided with a reference signal having a first value provided to the second bit line by the reference driving means, and provided to another second bit line by another reference driving means. 7. The semiconductor memory device according to claim 6, wherein the same number or substantially the same number of reference signals having the second value are combined. The predetermined node is connected to a gate of the gain transistor,
The load capacity of the first bit line driven by the gain transistor and the load capacity of the second bit line driven by the dummy transistor are larger than the load capacity of the node driven by the gain transistor. The semiconductor memory device according to claim 1, wherein: The first bit line is connected to a source of the gain transistor,
2. The semiconductor memory device according to claim 1, wherein said second bit line is connected to a source of said dummy transistor. 2. The semiconductor memory device according to claim 1, wherein said memory cell includes one of a ferroelectric capacitor, a paraelectric capacitor, a magnetoresistive element, a chalcogenide resistive element, a MONOS transistor, and a stacked gate transistor. The memory cell includes a ferroelectric capacitor having one electrode connected to an independent control line and the other electrode connected to a common node electrode,
2. The semiconductor memory device according to claim 1, wherein said gain transistor comprises a field effect transistor having a gate connected to said common node electrode. A memory unit having one or more memory cells for generating a read signal corresponding to a stored value at a predetermined node, and a gain transistor for driving a first bit line based on the read signal generated at the node; A data reading method in a semiconductor memory device including a plurality of arranged memory arrays,
Driving a second bit line different from the first bit line according to a supplied reference potential by a dummy transistor having the same size as the gain transistor;
By comparing currents flowing through the first bit line and the second bit line, or potentials of the first bit line and the second bit line, data of data read from the memory unit is compared. Determining a value. A plurality of memory units having one or more memory cells for generating a read signal corresponding to a stored value at a predetermined node and a gain transistor for driving a bit line based on the read signal generated at the node are arranged. A data read method in a semiconductor memory device including a memory array, wherein each of the bit lines is provided corresponding to one or a plurality of the memory units;
A first bit line corresponding to the memory unit to be read is driven by the gain transistor, and a second bit line different from the first bit line is supplied according to a supplied reference potential. Driving,
Determining a value of data read from the memory unit to be read by comparing currents flowing through the first and second bit lines or potentials of the first and second bit lines; And a data reading method.

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