JP2005071237A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device of which the reinforcement of a protecting feature is realized. <P>SOLUTION: A low frequency clock detection circuit detects whether a first clock has a frequency lower than a fixed frequency and forcibly stops or invalidates an operation of an internal circuit of the semiconductor integrated circuit device. The low frequency clock detection circuit is constituted of: a first circuit which is supplied with a first clock and forms a first signal to be regarded as different waveforms on the basis of the first clock depending on whether the first clock has a frequency lower than the fixed frequency or the first clock has a frequency higher than the fixed frequency: and a second circuit which forms a low frequency clock detection signal on the basis of the first signal and the first clock. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a technology that is effective when used in a device equipped with a security circuit against unauthorized access, for example, mounted on an IC card or the like.

A low-frequency CLK detection circuit has been proposed as one of security circuits for IC card microcomputers and the like. That is, in order to prevent the analysis of the circuit operation by slowing down the operation of the internal circuit by lowering the frequency of the clock supplied from the external terminal, the low frequency CLK detection circuit is provided, It detects input and stops or disables internal circuit operation. As a low frequency CLK detection circuit, the clock signal is delayed for a predetermined time, and the low value is detected by comparing the delayed value with the undelayed CLK level, or input as a count-up type delay circuit. For example, the frequency may be detected by counting how many times the internal oscillation circuit oscillates with respect to the frequency. Japanese Patent Laid-Open No. 2001-52130 is an example of a circuit that determines whether or not the clock frequency is within a predetermined range.
JP 2001-52130 A

  In the clock frequency detection circuit as described above, it is merely determined whether or not the clock is in a predetermined frequency range. In such a clock detection circuit, since the determination output is an output signal including a DC high level or low level, there is a problem that an unauthorized attack such as reading confidential information in the internal circuit is likely to occur. That is, by observing the circuit while changing the clock frequency, as shown in FIG. 12, the node N1, which is a signal path through which the detection output of the clock frequency is transmitted, is specified. When the signal path is specified in this way, the security function is stopped by improperly accessing the probe or the like to supply a voltage at a level that brings it to a normal frequency state, causing the detection circuit to malfunction. In addition, confidential information can be extracted by operating an internal circuit with a low-frequency clock.

  An object of the present invention is to provide a semiconductor integrated circuit device that realizes enhancement of a protection function. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, a first clock is supplied as a low-frequency clock detection circuit that detects whether the frequency is lower than a certain frequency and forcibly stops or disables the operation of the internal circuit of the semiconductor integrated circuit device. A first circuit that forms a first signal that is considered to have a different waveform with respect to the first clock when the frequency is lower than the predetermined frequency and when the frequency is higher than the certain frequency, and the first signal and the first clock The second circuit for forming the low frequency clock detection signal based on the above.

  Since the first signal is a pulse signal regarded as a different waveform with reference to the first clock, it is difficult to specify a signal path through which the signal is transmitted, and in addition, the second circuit malfunctions. It becomes difficult.

  FIG. 1 is a block diagram showing an embodiment of a semiconductor integrated circuit device provided with a clock frequency detection circuit according to the present invention. The semiconductor integrated circuit device of this embodiment is composed of a first circuit and a second circuit. The first circuit includes the following circuits that detect the clock frequency. The clock CLK is delayed through the delay circuit DL1 and input to the CR delay circuit CR1 that performs frequency detection. The CR delay circuit CR1 of this embodiment outputs a pulse having a frequency corresponding to the clock nck1 (CLK) when the frequency of the delay signal nck1 of the delay circuit DL1 is lower than a predetermined frequency, and the frequency of the delay signal nck1 is When the frequency is higher than a predetermined frequency, a fixed potential such as a low level or a high level is output.

  In this embodiment, the exclusive OR circuit EX1 and the gate circuit G are provided so as to output a frequency detection signal in the form of a pulse signal regardless of whether the frequency of the clock CLK is lower or higher than a predetermined frequency. It is done. That is, the output signal nck2 of the CR delay circuit CR1 is supplied to one input of the exclusive OR circuit EX1. The delay signal nck1 is supplied to the other input of the exclusive OR circuit EX1. The output signal of the exclusive OR circuit EX1 and the delayed signal nck1 are output as a detection signal N1 through the gate circuit G1.

  Since the detection signal N1 is in the form of a pulse signal both when the frequency of the clock CLK is lower and higher than the predetermined frequency as described above, it is used together with the clock CLK for identification. The signal is transmitted to a detection circuit included in the second circuit. In this detection circuit, the detection signal N1 in the form of the pulse signal is decoded using the clock CLK. That is, the reset signal RST including the low frequency clock detection signal is generated when the frequency of the clock CLK is lower than the predetermined frequency, and the reset signal RST is not generated when the frequency of the clock CLK is higher than the predetermined frequency. As a result, in a signal processing circuit (not shown) included in the second circuit, when the reset signal RST is invalid, the internal circuit performs a predetermined signal processing operation corresponding to the clock CLK, and the signal is output when the reset signal RST is validated. The operation of the processing circuit is forcibly stopped or disabled.

  FIG. 2 shows a circuit diagram of an embodiment of the CR delay circuit of FIG. In the figure, the circuit symbols used in FIG. 1 and specific circuits corresponding thereto are shown for reference. A resistor R and a capacitor C are connected in series. Charging current is supplied from the power supply terminal VDD to the capacitor C through the resistor R from the P-channel MOSFET Q2. The capacitor C is provided with a discharge path constituted by an N-channel MOSFET Q1 connected in parallel with the capacitor C. The source of the MOSFET Q1 is connected to the circuit ground potential VSS, and the capacitor C performs the charging and discharging operations with reference to the circuit ground potential VSS. The voltage of the capacitor C is supplied to the input terminal of the inverter circuit IV2. The inverter circuit IV2 determines the voltage of the capacitor C using the logic threshold voltage as a reference voltage.

  In the CR delay circuit of this embodiment, when the frequency of the pulse supplied to the input terminal in is low, the P-channel MOSFET Q2 is turned on during the low level period, and the capacitor C is charged via the resistor R. . The capacitor C is charged up according to the time constant at this time. When the input voltage of the inverter circuit IV2 exceeds the logic threshold voltage by this charge-up operation, the output signal out of the inverter circuit IV2 changes from high level to low level.

  When the pulse supplied to the input terminal in changes to high level, the P-channel MOSFET Q2 is turned off and the N-channel MOSFET Q1 is turned on, so that the capacitor C is discharged. As a result of this discharging operation, when the voltage of the capacitor C decreases and the input voltage of the inverter circuit IV2 decreases below its logic threshold voltage, the output signal out of the inverter circuit IV2 changes from low level to high level. As described above, when the voltage of the capacitor C has a low frequency exceeding the logic threshold voltage of the inverter circuit IV2, a pulse having a frequency corresponding to the pulse supplied to the input terminal in is output.

  The frequency of the pulse supplied to the input terminal “in” becomes high, the P-channel MOSFET Q2 is turned on during the low level period, the capacitor C is charged through the resistor R, and the voltage of the capacitor C is The voltage rises according to a constant, but before reaching the logic threshold voltage of the inverter circuit IV2, the low-level period is switched to the high level period, the P-channel MOSFET Q2 is turned off, and the N-channel MOSFET Q1 is turned on. The discharge operation is performed. As a result, since the input voltage of the inverter circuit IV2 does not reach the logic threshold voltage, a high level output signal is steadily formed.

  FIG. 3 is a timing chart for explaining an example of the operation of the clock frequency detection circuit of FIG. FIG. 3A is a timing diagram when the frequency of the clock CLK is low, and FIG. 3B is a timing diagram when the frequency of the clock CLK is high. In FIG. 3A, the delay clock nck1 is delayed from the clock CLK by the delay time td of the delay circuit DL1. Since the output signal nck2 of the CR delay circuit CR1 has a low frequency as described above, it is delayed by the delay time tcr corresponding to the time constant. When the CR time constant circuit as shown in FIG. 2 is used, there is a frequency region in which the pulse width (pulse duty) becomes narrower than the delay signal nck1 corresponding to the frequency. The case where the frequency is low is taken as an example.

  The exclusive OR circuit EX1 forms a low level output signal nex when the levels of the two pulses nck1 and nck2 match, and a high level output signal nex when they do not match. The logic of the signal nex and the clock nck1 is taken by the gate circuit G. Specifically, a low level that is a coincident output of the signal nex when the clock nck1 is at a high level is output from the node N1. In other words, when the clock nck1 is at low level, the gate of the gate circuit G1 is closed and the node N1 is set to high level regardless of the signal nex.

  In this way, when the frequency of the clock CLK is low, a period in which the node N1 is at a low level corresponding to the cycle of the clock nck1 occurs. Such a pulse signal of the node N1 is transmitted to the detection circuit. The detection circuit determines the low level / high level of the node N1 using the edge of the clock CLK. In the figure, when the high level of the node N1 is first detected at the falling edge of the clock CLK, the reset signal RST is generated. This reset signal RST is held by a latch circuit or the like.

  In FIG. 3B, the delay clock nck1 is delayed by the delay time td of the delay circuit DL1 with respect to the clock CLK. Since the output signal nck2 of the CR delay circuit CR1 has a high frequency as described above, it is set to a fixed level such as a high level. The exclusive OR circuit EX1 forms a low level output signal nex when the levels of the two pulses nck1 and nck2 match, and a high level output signal nex when they do not match. Accordingly, since the level of nck2 is high as described above, a signal obtained by inverting the clock nck1 is output from the node N1.

  Thus, even when the frequency of the clock CLK is high, the node N1 is a pulse signal corresponding to the clock nck1. Such a pulse signal of the node N1 is transmitted to the detection circuit. The detection circuit performs the low level / high level determination using the edge of the clock CLK. In the figure, when the low level of the node N1 is detected at the high level / falling edge of the node N1 at the rising edge of the clock CLK, the reset signal RST is not generated. A delay circuit DL1 is provided for such level determination, and the delay time td here is set as a setup time for taking in the high level / low level of the node N1.

  The truth table 1 of the detection circuit of FIG. 1 is as follows.

Truth Table 1
┌───┬────┬─────┐
│CLK│N1 │RST │
├───┼────┼─────┤
│ ↑ │0 │ 1 │
│ ↑ │1 │ 0 │
│ ↓ │0 │ 0 │
│ ↓ │1 │ 1 │
└───┴────┴─────┘
↑ is rising edge ↓ is falling edge 0 is low level (logic 0)
1 is high level (logic 1)

  Note that the delay circuit DL1 can be omitted. That is, since the signal of the node N1 is delayed by the gate circuit G1 as described above, the delay time here is used for the setup time for taking in the high level / low level of the node N1 in the detection circuit. can do. Or the structure which provides the delay circuit etc. which set this setup by the detection circuit side may be sufficient.

  As described above, when the frequency of the clock CLK is higher than the detection threshold (detection frequency), the clock CLK itself (the delayed signal nck1 in the circuit of FIG. 1) is inverted and output from the node N1. When the clock CLK frequency is lower than the detection threshold (detection frequency), it is delayed by the CR delay circuit CR1. The delayed signal nck2 passes through the exclusive OR circuit EX1 and the gate circuit G1, so that the node N1 becomes high level (H) before the next edge of the clock CLK.

  That is, when the clock CLK frequency is lower than the detection threshold (detection frequency), H is always output at the edge of the clock CLK. By using this detection circuit as shown in the truth table 1, the reset signal RST becomes a high level (H) at the negative edge of the clock CLK, and the signal processing circuit (not shown) is reset. At the time of non-detection, the node N1 is ACed corresponding to the clock nck1. If the node N1, which is such a signal path, is forcibly fixed to either the high level or the low level, the reset signal RST always becomes the high level (H), and the reset is started.

  As in this embodiment, a fixed level (DC signal) of the signals on the signal path (node N1) leading to the detection circuit is combined with the exclusive OR circuit and the gate circuit G1 as described above to generate a pulse signal (AC Circuit), the DC signal among the detection signals formed by the CR delay circuit CR1 is made invisible. As a result, in an IC having a low frequency detection circuit, pulse signals (AC signals) having different patterns are generated when the clock CLK supplied to the low frequency detection circuit is within a predetermined frequency range and when the clock CLK is outside the predetermined frequency range. Maintaining confidentiality of internal information against illegal attacks from the outside by providing a first circuit that outputs and a second circuit that captures the output by the output of the first circuit and the clock CLK (may be different from the above) can do.

  That is, by making a signal with the clock CLK superimposed on the node N1 as an output to the detection circuit, it becomes possible to make a complete AC signal with low frequency detection, and it becomes difficult to specify the signal transmission path from the outside. Even in the case of an attack that supplies a fixed level to the node N1, the reset signal RST is issued, so that internal information can be prevented from being taken out. As a result, the security of the IC chip against external attacks is improved, so that it is easy to obtain security authentication, and the added value as an IC card microcomputer can be increased.

  By converting the output signal of an analog delay element such as a CR time constant circuit into an AC signal by the exclusive OR circuit and the gate circuit as described above, both high accuracy of delay time and high security can be achieved. The low frequency detection circuit is an indispensable circuit for prohibiting frequency input other than the operating frequency of the microprocessor or microcomputer in the IC and preventing malfunction. Therefore, it is not desirable that the threshold value of the frequency circuit varies depending on use conditions. As a result, it is desirable to use a delay circuit using analog elements such as a CR time constant circuit.

  FIG. 4 is a block diagram showing another embodiment of a semiconductor integrated circuit device having a clock frequency detection circuit according to the present invention. In this embodiment, two sets of circuits for detecting the low frequency of the first circuit of FIG. 1 are provided. That is, the low frequency detection unit including the CR delay circuit CR1, the exclusive OR circuit EX1, and the gate circuit G1 as in FIG. 1, the CR delay circuit CR2, the exclusive OR circuit EX2, and the gate having the same circuit configuration as the low frequency detection unit. A circuit G2 is provided. The newly provided CR delay circuit CR2 and exclusive OR circuit EX2 are supplied with the inverted signal nck3 of the delay signal nck1. This inverted signal nck3 is formed by an inverter circuit IV1 that receives the delay signal nck1. Detection signals N1 and N2 are formed by the circuits for detecting these two sets of low frequencies, respectively, and transmitted to the detection circuit included in the second circuit.

  FIG. 5 is a timing chart for explaining an example of the operation of the clock frequency detection circuit of FIG. In this embodiment, a low level pulse corresponding to the mismatch output of the exclusive OR circuit EX2 is output from the node N2 during the period when the clock CLK is low level by the newly provided frequency detection unit. In this way, by arranging the exclusive OR circuits EX1 and EX2 in parallel, it is possible to detect low frequency at both the positive edge and the negative edge of the clock CLK as compared with the circuit of the embodiment of FIG. Thus, security can be further improved. For example, an illegal attack performed by changing the pulse duty of the clock CLK can be prevented.

  FIG. 6 is a block diagram showing still another embodiment of a semiconductor integrated circuit device having a clock frequency detection circuit according to the present invention. In this embodiment, the exclusive OR circuits EX1 and EX2 of the first circuit of FIG. 4 are replaced with OR gate circuits G3 and G4, or the exclusive OR circuits EX1 and EX2 are omitted and the gate circuits G1 and EX2 are omitted. G2 is replaced with the above OR gate circuits G3 and G4. A configuration in which the detection logic is changed using such OR gate circuits G3 and G4 is also possible.

  FIG. 7 is a timing chart for explaining an example of the operation of the clock frequency detection circuit of FIG. By using the OR gate circuits G3 and G4 as described above, the pulses at the nodes N1 and N2 can be the same as those in the embodiment of FIG. Thus, even if the exclusive OR circuit is changed to an OR gate circuit, the same detection as in FIG. 4 is possible.

  The truth table 2 of the detection circuit of FIGS. 4 and 6 is as follows.

Truth Table 2
┌───┬───┬───┬───┐
│CLK│N1 │N2 │RST│
├───┼───┼───┼───┤
│ ↑ │0 │0 │1 │
│ ↑ │1 │1 │1 │
│ ↓ │0 │0 │1 │
│ ↓ │1 │1 │1 │
├───┼───┼───┼───┤
│ ↑ │0 │1 │1 │
│ ↑ │1 │0 │0 │
│ ↓ │0 │1 │0 │
│ ↓ │1 │0 │1 │
└───┴───┴───┴───┘
↑ is rising edge ↓ is falling edge 0 is low level (logic 0)
1 is high level (logic 1)

  FIG. 8 is a block diagram showing still another embodiment of a semiconductor integrated circuit device having a clock frequency detection circuit according to the present invention. In this embodiment, a random number generation circuit is mounted on a semiconductor integrated circuit device, encryption is input to a delay circuit section corresponding to the first circuit, and the AC signal + encryption is formed to detect the second circuit. To communicate. The detection circuit receives the encryption decompression supplied from the random number generation circuit, extracts the AC signal from the AC signal + encryption transmitted from the first circuit, and generates a reset signal. Thus, by converting the signal output to the node N1 into an AC signal and encrypting it, it is difficult to analyze the AC signal itself, and security can be improved. For example, some semiconductor integrated circuit devices for mounting an IC card include a random number generation circuit, and such a semiconductor integrated circuit device can share the random number generation circuit.

  FIG. 9 shows a specific block diagram of an embodiment of the clock frequency detection circuit of FIG. The random number signal formed by the random number generation circuit is output as a pulse train and supplied to the exclusive OR circuits EX3 and EX4. The other input of the exclusive OR circuit EX3 is supplied with the output signal N1 of the delay circuit section (frequency detection) as in the embodiment of FIG. 1, FIG. 4 or FIG. The exclusive OR signal EX3 generates a random number signal that inverts the output level of the node N1 when the random number of the pulse train is logic 1, and outputs the output signal of the node N1 as it is when the random number is logic 0. Let The exclusive OR circuit EX4 provided on the detection circuit side inverts the level of the AC signal when the random number consisting of the same pulse train is logic 1, and outputs the AC signal as it is when the random number is logic 0. In this way, only the AC signal corresponding to the node N1 is reproduced and transmitted to the detection circuit.

  Although not particularly limited, the node N1 of the exclusive OR circuit EX3 exists across the well of the analog part and the well of the digital part, and the two exclusive OR circuits EX3 and EX4 and the wiring connecting them are other than the node N1. Is present in the well of the digital part. With such a configuration, if the two exclusive OR circuits EX3 and EX4 and the wiring connecting them extend over the analog well and the digital well, the wiring is found and the pattern analysis is prevented. It will be beneficial.

  FIG. 10 is a block diagram showing an embodiment of an IC card on which the semiconductor integrated circuit device according to the present invention is mounted. In this embodiment, a signal processing circuit including an arithmetic circuit, a ROM (Read Only Memory), a RAM (Random Access Memory), a FLASH (Batch Erase Nonvolatile Memory), a peripheral circuit, A first power supply terminal for supplying power necessary for the operation of the semiconductor integrated circuit device; a second power supply terminal for supplying power lower than the first power supply terminal; and an internal circuit of the semiconductor integrated circuit device. A reset terminal for resetting, a clock terminal to which the first clock is supplied, an input / output terminal for inputting / outputting a signal to / from the outside of the semiconductor integrated circuit device, and a protection circuit as described above In addition to the frequency detection circuit (LFD), a high frequency detection circuit (HFD), a low voltage detection circuit (LVD), and a high voltage detection circuit (HVD) are provided. When a detection signal is formed by each of these detection circuits, a reset signal RST is formed to force the operation of various arithmetic circuits, ROM, RAM, FLASH, and peripheral circuits constituting the signal processing circuit. Stopped (reset) state.

  FIG. 11 shows an operating characteristic diagram of an IC card to which the present invention is applied. The IC card of this embodiment has an operation compensation range in which the operating frequency is higher than the frequency set by the low frequency detection circuit (LFD) and lower than the frequency set by the high frequency detection circuit (HFD). As the operation voltage, the region that is higher than the voltage set by the low voltage detection circuit (LVD) and lower than the voltage set by the high voltage detection circuit (HVD) is set as the operation compensation range. When such a clock having a frequency outside the operation compensation range of the IC card is supplied from the terminal CLK, or when a voltage outside the operation compensation range of the IC card is supplied from the power supply terminal, these circuits detect the above signal. The operations of the arithmetic circuit, the various memories such as ROM, RAM, and FLASH, and the peripheral circuits constituting the processing circuit are forcibly stopped (reset).

  Although the invention made by the inventor has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. For example, as described above, a circuit that converts a signal having a fixed level among frequency detection signals into a pulse signal using a clock can take various embodiments. The CR delay circuit may be configured such that a capacitor and a resistor are connected in parallel, a charging current is supplied by, for example, a P-channel MOSFET, and a discharging path is performed by a resistor connected in parallel. As described above, the circuit for detecting the predetermined frequency by the delay circuit can take various embodiments. The present invention can be widely used for semiconductor integrated circuit devices in which the protection function of the internal circuit is enhanced by frequency detection.

1 is a block diagram showing an embodiment of a semiconductor integrated circuit device provided with a clock frequency detection circuit according to the present invention. FIG. 2 is a circuit diagram showing an embodiment of the CR delay circuit of FIG. 1. FIG. 2 is a timing diagram for explaining an example of the operation of the clock frequency detection circuit of FIG. 1. It is a block diagram which shows another Example of the semiconductor integrated circuit device provided with the clock frequency detection circuit based on this invention. FIG. 5 is a timing chart for explaining an example of the operation of the clock frequency detection circuit of FIG. 4. It is a block diagram which shows another Example of the semiconductor integrated circuit device provided with the clock frequency detection circuit based on this invention. FIG. 7 is a timing chart for explaining an example of the operation of the clock frequency detection circuit of FIG. 6. It is a block diagram which shows another Example of the semiconductor integrated circuit device provided with the clock frequency detection circuit based on this invention. FIG. 9 is a specific block diagram illustrating an embodiment of the clock frequency detection circuit of FIG. 8. 1 is a block diagram showing an embodiment of an IC card on which a semiconductor integrated circuit device according to the present invention is mounted. It is an operating characteristic figure of IC card to which this invention is applied. 1 is a schematic block diagram of an IC chip studied prior to the present invention.

Explanation of symbols

  DL ... delay circuit, CR1, CR2 ... CR delay circuit (frequency detection), EX1 to EX4 ... exclusive OR circuit, G1 to G4 ... gate circuit, IV1, IV2 ... inverter circuit, Q1, Q2 ... MOSFET, R ... resistance , C: Capacitor.

Claims (10)

It has a low-frequency clock detection circuit that detects whether the frequency is lower than a certain frequency, and the operation of the internal circuit is forcibly stopped or invalidated based on the low-frequency clock detection signal formed by the low-frequency clock circuit. A semiconductor integrated circuit device comprising:
The low frequency clock detection circuit has a first circuit and a second circuit,
The first circuit is supplied with a first clock, and is considered to have a different waveform with respect to the first clock when the frequency is lower than the fixed frequency and when the frequency is higher than the fixed frequency. Output
The semiconductor integrated circuit device, wherein the second circuit outputs the low-frequency clock detection signal based on the first signal and the first clock. In claim 1,
When the condition for determining that the first clock is lower than the fixed frequency is satisfied based on the first signal and the first clock, the second circuit maintains the state and maintains the low frequency clock detection signal. Output a semiconductor integrated circuit device. In claim 1,
The semiconductor integrated circuit device according to claim 1, wherein the first signal has a different period when the first clock is lower than the fixed frequency and when the first clock is higher than the fixed frequency. In claim 1,
The semiconductor integrated circuit device according to claim 1, wherein the first signal has a different pulse duty when the first clock is lower than the fixed frequency and when the first clock is higher than the fixed frequency. In claim 2,
The first circuit includes:
A CR delay circuit for receiving the first clock;
In response to the delay output of the CR delay circuit, a DC level of a high level or a low level is output when the frequency is higher than the certain frequency, and a pulse signal having a frequency corresponding to the first clock is formed when the frequency is lower than the certain frequency. An inverter circuit to
A matching / mismatching circuit that receives a clock corresponding to the first clock and an output signal of the inverter circuit; and an OR circuit that receives an output signal of the matching / mismatching circuit and a clock corresponding to the first clock. A semiconductor integrated circuit device. In claim 5,
The CR delay circuit is connected in parallel with a capacitor, a resistance element in series with the capacitor, a first MOSFET of a first conductivity type that supplies a charging current to the capacitor through the resistance element, and the capacitor. A second MOSFET of a second conductivity type that allows a capacitor discharge current to flow,
The first clock is supplied to the gates of the first MOSFET and the second MOSFET to form a rising or falling delay signal of the first clock;
A semiconductor integrated circuit device, wherein a delay signal formed by the capacitor is supplied to an input terminal of the inverter circuit. In claim 2,
The semiconductor integrated circuit device, wherein the second circuit forms the low-frequency detection signal by determining the level of the first signal at the rise and fall of the first clock. In claim 2,
The semiconductor integrated circuit device includes: a first power supply terminal necessary for the operation of the semiconductor integrated circuit device; a second power supply terminal for supplying power lower than the first power supply terminal;
A reset terminal for resetting an internal circuit of the semiconductor integrated circuit device;
A clock terminal to which the first clock is supplied;
A semiconductor integrated circuit device having an input / output terminal for inputting / outputting a signal to / from the outside of the semiconductor integrated circuit device. In claim 1,
2. The semiconductor integrated circuit device according to claim 1, wherein the fixed frequency is set to a frequency at which it is determined that the probability of unauthorized access to an internal circuit of the semiconductor integrated circuit device is high. In claim 6,
The semiconductor integrated circuit device is mounted on an IC card.

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