JP2005298975A - タンタル層を形成する方法及びタンタル層を用いる装置 - Google Patents
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
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- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
- H10W20/045—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for deposition from the gaseous phase, e.g. for chemical vapour deposition [CVD]
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- B—PERFORMING OPERATIONS; TRANSPORTING
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Abstract
【解決手段】 本発明の方法は、第1の層(222、420)の第1の層領域(224、324、524)上に、及び第2の層(220)の第2の層領域上に配置されるタンタル層(230、330、430、530)を作り出すステップ(194)を含むタンタル構造を製造する方法であって、前記タンタル層が前記第1の層領域上の実質上bcc相のタンタル領域(234、334、434、534)であり、また前記タンタル層が前記第2の層領域上の非bcc相のタンタル領域(232、332、432、532)である方法。
【選択図】 図4
Description
222 第1の層
224 第1の層領域
230 タンタル層
232 非bcc相のタンタル領域
234 bcc相のタンタル領域
Claims (15)
- 第1の層(222、420)の第1の層領域(224、324、524)上に、及び第2の層(220)の第2の層領域上に配置されるタンタル層(230、330、430、530)を作り出すステップ(194)を含むタンタル構造を製造する方法であって、
前記タンタル層が前記第1の層領域上の実質上bcc相のタンタル領域(234、334、434、534)であり、また前記タンタル層が前記第2の層領域上の非bcc相のタンタル領域(232、332、432、532)である方法。 - 前記タンタル層を作り出すステップが、さらに、いずれも圧縮残留応力を有する実質上bcc相のタンタル領域と非bcc相のタンタル領域とを作り出すステップを含む請求項1に記載の方法。
- 前記タンタル層を作り出すステップが、さらに、前記実質上bcc相のタンタル領域及び前記非bcc相のタンタル領域が本質的に連続しているタンタル薄膜を形成するタンタル層を作り出すステップを含む請求項1に記載の方法。
- マスクを利用することなく、前記非bcc相のタンタル領域を選択的にエッチングするステップをさらに含む請求項1に記載の方法。
- 前記タンタル層を作り出すステップが、さらに、前記実質上bcc相のタンタル領域及び前記非bcc相のタンタル領域が抵抗率を有し、前記実質上bcc相のタンタル領域の前記抵抗率が、前記非bcc相のタンタル領域の前記抵抗率の約10分の1である前記タンタル層を作り出すステップを含む請求項1に記載の方法。
- 前記タンタル層を作り出すステップの前に、前記第1の層領域を洗浄するステップをさらに含む請求項1に記載の方法。
- 前記第2の層(348)を作り出すステップ、
基板と前記第1の層との間に配置される誘電体層(346)を作り出すステップ、
前記基板と前記第1の層との間に配置される抵抗器層(342)を作り出すステップ、
前記タンタル層上に配置されるチャンバ層(350)を作り出すステップ、
前記チャンバ層内に流体吐出チャンバ(352)を形成するステップ、
前記チャンバ層上に配置されるノズル層(360)を作り出すステップ、
前記チャンバ層内に形成されている流体吐出チャンバと流体連通する少なくとも1つのノズル(362)を形成するステップ
をさらに含む請求項1に記載の方法。 - 前記第1の層を作り出すステップであって、当該第1の層がbcc相のタンタルを形成する基板(420)である前記第1の層を作り出すステップ、
前記bcc相のタンタルを形成する基板上に非bcc相のタンタルを形成する層(425)を付着するステップをさらに含む請求項1に記載の方法。 - 前記第1の層を作り出すステップをさらに含み、当該第1の層が、ニオブ、アルミニウム、チタン、窒化タンタル、窒化アルミニウム、窒化ニオブ、窒化チタン、それらの混合物からなるグループより選択される材料を含む請求項1に記載の方法。
- 非bcc相のタンタル領域(232、332、432、532)に隣接した実質上bcc相のタンタル領域(234、334、434、534)を有するタンタル層を含む装置であって、
前記実質上bcc相のタンタル領域及び前記非bcc相のタンタル領域がそれぞれ圧縮残留応力を有する装置。 - 基板(320)と、
前記基板上に配置されているタンタル層(230、330、430、530)と、
前記基板と前記タンタル層の間に配置されているbcc相のタンタルを形成する領域(224、324、524)であって、前記タンタル層と接触しているbcc相のタンタルを形成する領域(224、324、524)とを含む装置であって、
前記タンタル層が前記bcc相のタンタルを形成する領域と接触している場所において、前記タンタル層が実質上bcc相のタンタル領域(234、334、434、534)を形成している装置。 - 前記タンタル層が前記bcc相のタンタルを形成する領域と接触していない場所において、前記タンタル層が非bcc相のタンタル層(232、332、432、532)を形成している請求項11に記載の装置。
- 基板(320)と、
前記基板の上方あるいは前記基板上に配置されているタンタル層(230、330、430、530)を作り出す手段とを備えている装置であって、
前記タンタル層が、少なくとも1つの非bcc相のタンタル領域(232、332、432、532)と隣接する少なくとも1つの実質上bcc相のタンタル領域(234、334、434、534)を有する装置。 - 犠牲層を選択的に除去し、自立式のタンタル層を形成する手段をさらに備えている請求項13に記載の装置。
- 前記少なくとも1つの非bcc相のタンタル領域を選択的にエッチングする手段をさらに備えている請求項13に記載の装置。
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/825,841 US7445810B2 (en) | 2004-04-15 | 2004-04-15 | Method of making a tantalum layer and apparatus using a tantalum layer |
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| Publication Number | Publication Date |
|---|---|
| JP2005298975A true JP2005298975A (ja) | 2005-10-27 |
| JP4533221B2 JP4533221B2 (ja) | 2010-09-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005116413A Expired - Fee Related JP4533221B2 (ja) | 2004-04-15 | 2005-04-14 | タンタル層を形成する方法及びタンタル層を用いる装置 |
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| Country | Link |
|---|---|
| US (1) | US7445810B2 (ja) |
| EP (1) | EP1587139A3 (ja) |
| JP (1) | JP4533221B2 (ja) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011187789A (ja) * | 2010-03-10 | 2011-09-22 | Seiko Epson Corp | 圧電アクチュエーターの製造方法 |
| CN111799372A (zh) * | 2020-05-15 | 2020-10-20 | 上海华力微电子有限公司 | Rram阻变结构的形成方法 |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008130982A (ja) * | 2006-11-24 | 2008-06-05 | Sumitomo Electric Ind Ltd | ウエハ収納容器内に設ける部材およびその製造方法 |
| WO2009084445A1 (ja) * | 2007-12-27 | 2009-07-09 | Canon Anelva Corporation | ドライエッチング方法、磁気抵抗効果素子とその製造方法及び製造装置 |
| FR2953068B1 (fr) * | 2009-11-24 | 2012-01-20 | Commissariat Energie Atomique | Dispositif d'affichage electronique a ecran electroluminescent, et son procede de fabrication |
| US9295153B2 (en) | 2012-11-14 | 2016-03-22 | Rohm And Haas Electronic Materials Llc | Method of manufacturing a patterned transparent conductor |
| US20150001720A1 (en) * | 2013-06-27 | 2015-01-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnect Structure and Method for Forming Interconnect Structure |
| TWI671211B (zh) * | 2014-11-19 | 2019-09-11 | 愛爾蘭商滿捷特科技公司 | 生存期獲得改善之噴墨噴嘴裝置 |
| US10532571B2 (en) * | 2015-03-12 | 2020-01-14 | Hewlett-Packard Development Company, L.P. | Printhead structure |
| WO2017111814A1 (en) * | 2015-12-26 | 2017-06-29 | Intel Corporation | Low resistance interconnect |
| US10801100B2 (en) * | 2018-09-11 | 2020-10-13 | Arizona Board Of Regents On Behalf Of Arizona State University | Multimodal microstructure material and methods of forming same |
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-
2004
- 2004-04-15 US US10/825,841 patent/US7445810B2/en not_active Expired - Fee Related
-
2005
- 2005-03-15 EP EP20050005621 patent/EP1587139A3/en not_active Withdrawn
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03248568A (ja) * | 1990-02-27 | 1991-11-06 | Fuji Xerox Co Ltd | 薄膜半導体装置 |
| JPH04318934A (ja) * | 1991-04-18 | 1992-11-10 | Sharp Corp | 金属薄膜及びその製造方法 |
| JPH07226507A (ja) * | 1994-02-10 | 1995-08-22 | Fujitsu Ltd | 半導体装置及びその製造方法 |
| JPH09213961A (ja) * | 1996-01-29 | 1997-08-15 | Seiko Epson Corp | 薄膜半導体装置及びその製造方法並びに電子機器及びその製造方法 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011187789A (ja) * | 2010-03-10 | 2011-09-22 | Seiko Epson Corp | 圧電アクチュエーターの製造方法 |
| US8966729B2 (en) | 2010-03-10 | 2015-03-03 | Seiko Epson Corporation | Method for manufacturing piezoelectric actuator |
| CN111799372A (zh) * | 2020-05-15 | 2020-10-20 | 上海华力微电子有限公司 | Rram阻变结构的形成方法 |
| CN111799372B (zh) * | 2020-05-15 | 2023-03-24 | 上海华力微电子有限公司 | Rram阻变结构的形成方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| EP1587139A3 (en) | 2006-05-24 |
| US7445810B2 (en) | 2008-11-04 |
| EP1587139A2 (en) | 2005-10-19 |
| US20050233159A1 (en) | 2005-10-20 |
| JP4533221B2 (ja) | 2010-09-01 |
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