JP2007102902A - Semiconductor memory device and inspection method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To screen a reliability failure due to a shortage of an SNM value in an initial inspection in an SRAM inspection.
Each end of a normal operation precharge circuit and a test precharge circuit is connected in parallel to each bit line of an SRAM bit line pair. The normal operation precharge circuit and the inspection precharge circuit are connected to the same power supply voltage. The normal operation precharge circuit connected to each bit line of the bit line pair is the same first activation signal, and the test precharge circuit connected to one bit line of the bit line pair is the second. The test precharge circuit connected to the other bit line of the bit line pair is activated by the third activation signal. At the time of inspection, before the read operation, the activation of the second or third activation signal precharges one bit line and the other bit line of the bit line pair to different precharge potentials.
[Selection] Figure 1 (a)

Description

  The present invention relates to a semiconductor memory device and an inspection method thereof, and more particularly to a circuit system of a static random access memory and a method of screening for a reliability failure thereof.

  2. Description of the Related Art In recent years, with increasing functionality of semiconductor integrated circuit devices, many static random access memories (hereinafter referred to as SRAM) are mounted on semiconductor integrated circuit devices because of their high speed and ease of control and system integration.

  However, when a transistor constituting an SRAM memory cell is contaminated by minute foreign matter generated in the manufacturing process, the semiconductor element containing the foreign matter does not perform a desired operation, and thus a predetermined characteristic cannot be obtained. It becomes defective. In order not to put a semiconductor element having such a characteristic defect on the market, the defective element is usually screened by inspection at the time of shipment.

  However, some of the above-mentioned characteristic failures due to foreign substances are determined to be defective in the initial state immediately after manufacturing, but in the case of contamination due to impurities, the characteristics gradually deteriorate under actual use conditions. There are things that lead to market failure. In particular, defects that occur after entering the market are highly disadvantageous to users due to the effects of defects because semiconductor elements are already incorporated in various devices, and it is essential to eliminate such market defects. .

Thus, various screening techniques for reducing the market failure rate have been proposed.
Hereinafter, a conventional screening method in the case where an insufficient read capability of the SRAM memory cell occurs will be described with reference to FIGS. 2, 3, 4A, and 4B (for example, Patent Document 1). reference).

  FIG. 2 shows an example of a simplified circuit configuration of a general SRAM, and FIG. 3 shows an example of operation waveforms of main signals. FIG. 4A shows an example of the word line selection signal WL, the sense amplifier activation signal SA, and the potential waveforms BL and XBL of the bit line pair when data is read from the SRAM memory cell. b) is an enlarged waveform diagram of the potential waveforms BL and XBL of the bit line pair when the sense amplifier is activated. In FIG. 4B, A in the figure indicates the operation timing during the normal operation, and B indicates the operation timing during the screening test.

  In these figures, 103 is a memory cell, 104 is a sense amplifier, PRC is a precharge activation signal, WL is a word line activation signal, SA is a sense amplifier activation signal (hereinafter also referred to as SA signal), and BL is positive. Logic side bit line, XBL is negative logic side bit line, SN is positive logic side memory cell internal node, XSN is negative logic side memory cell internal node, and Q11 to Q17 are transistors.

  When the SA signal is activated at the timing A, in the case of a normal cell with sufficient read current capability, the read potential difference VNA from this normal cell is sensed as shown by the solid line in FIG. The sense amplifier 104 can detect data from the memory cell that is higher than the detection level VSA of the amplifier 104.

  On the other hand, when the SA signal is activated at the timing A, the read potential VMA from the abnormal cell is detected by the sense amplifier 104 in the case of an abnormal cell whose read current capability is reduced due to a foreign substance or the like in the process. When it is smaller (not shown), reading cannot be performed and the abnormal cell is detected as defective. However, when VNA> VMA> VSA, as shown by the alternate long and short dash line in FIG. Then, normal reading is performed, and an abnormal cell cannot be detected by the initial inspection.

  Such an abnormal cell has its characteristics deteriorated as the use frequency overlaps, and it often leads to poor reliability over time, and becomes a serious problem especially when it becomes a bad market.

  Therefore, it is desirable to screen such an abnormal cell at the time of initial inspection as much as possible. In order to cope with this, in the method disclosed in Patent Document 1, the activation timing of the sense amplifier 104 is advanced from A to B during the screening test.

In this way, by accelerating the start timing of the sense amplifier 104, as can be seen from FIG. 4B, the read potential VMB from the abnormal cell becomes lower than the sense amplifier detection level VSA, and the abnormal cell is detected during the initial inspection. Is possible.
Japanese Laid-Open Patent Publication No. 2-206087

  By the way, as the operating voltage of the semiconductor integrated circuit device is lowered, it becomes difficult to ensure the stability of the storage node of the SRAM (hereinafter abbreviated as static noise margin: SNM), and the SRAM data is destroyed during the read operation. There is a problem that it is easy to cause “reading crushing”. For more information on this phenomenon, see IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. SC-22, No. 5, OCTOBER 1987 “Static-Noise Margin Analysis of MOS SRAM Cells” and IEICE Transactions C-II Vol. J75-C-II No. 7 pp. 350-361 July 1992 “Static noise margin analysis of fine CMOS memory cell”.

  As described above, it has become difficult to ensure a sufficient SNM value due to a decrease in power supply voltage accompanying the miniaturization of semiconductor elements, and further, the ability of a transistor constituting an SRAM cell due to foreign matter generated in the manufacturing process. When the deterioration occurs and the transistor capability in the cell deviates from the design value, the SNM value deteriorates and leads to a failure.

  As described above, defects due to foreign matters generated in such a manufacturing process deteriorate the characteristics as the frequency of use of the abnormal cells overlaps, and thus often lead to poor reliability over time, resulting in market defects. In order to prevent this, it is desirable to screen at the initial inspection.

  Here, in the conventional method described above, screening is performed by accelerating the operation timing of the sense amplifier. However, with the recent reduction in voltage and speed of semiconductor elements, the operation timing of the sense amplifier is almost marginal. Therefore, it is almost impossible to substantially advance the operation timing. Therefore, in the future, it will be virtually impossible to screen for a reliability failure due to SNM shortage by an initial inspection by this method.

  The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to provide a semiconductor memory device that can be screened for a reliability failure due to a shortage of SNM values by an initial test, and a test method therefor.

  In order to solve the above problems, a first semiconductor memory device of the present invention is a semiconductor memory device having an SRAM mounted thereon, and a normal operation precharge circuit is provided on each bit line of the SRAM bit line pair. Each end of the test precharge circuit is connected in parallel, and the normal operation precharge circuit and the test precharge circuit are connected to the same power supply voltage, and each bit line of the bit line pair The first and second normal operation precharge circuits connected to are activated by the same first activation signal and are connected to one bit line of the bit line pair. The circuit is activated by a second activation signal, and the second inspection precharge circuit connected to the other bit line of the bit line pair is activated by a third activation signal, and the first to Third The activation signals are controlled independently of each other, and the second activation line is in a state where the other bit line of the bit line pair is at the first precharge potential before the read operation at the time of inspection of the semiconductor memory device. By activating the enable signal, one bit line of the bit line pair is set to a second precharge potential, or one bit line of the bit line pair is at the precharge potential of 1, By activating the third activation signal, the other bit line of the bit line pair is set to a second precharge potential, and one bit line of the bit line pair and the other of the bit line pair are Precharge means for precharging the bit lines to different precharge potentials is provided.

  In the first semiconductor memory device of the present invention, the sense amplifier for setting the potential of each bit line of the bit line pair is held in the memory cell before the read operation at the time of inspection of the semiconductor memory device. Depending on the data, one bit line of the bit line pair is set to a predetermined logic potential of H or L level, and the other bit line is complementary to the logic potential set to the one bit line. When the other bit line of the bit line pair is set to an H level logical potential equal to the first precharge potential by the sense amplifier, the precharge means Is activated to charge one of the bit lines set to the L level logic potential to a second precharge potential lower than the H level logic potential, and to the sense amplifier. When the one bit line is set to the H level logic potential equal to the first precharge potential, the third activation signal is activated and the other bit line set to the L level logic potential is activated. It is preferable to charge the bit line to a second precharge potential lower than the H level logic potential.

  In the first semiconductor memory device of the present invention, the normal operation precharge circuit and the test precharge circuit are both P-channel type transistors, and the precharge means includes a P channel of the test precharge circuit. The type transistor is preferably composed of a transistor having a smaller driving capability than the P-channel type transistor of the normal operation precharge circuit.

  In the first semiconductor memory device of the present invention, the normal operation precharge circuit is formed of a P-channel transistor, the inspection precharge circuit is formed of an N-channel transistor, and one bit of the bit line pair Means for precharging the line and the other bit line of the bit line pair to different precharge potentials, the first precharge potential is applied to the bit line connected to the normal operation precharge circuit; It is preferable that a second precharge potential that is lower than the first precharge potential by the threshold voltage of the N-channel transistor is applied to the bit line to which the inspection precharge circuit is connected.

  A second semiconductor memory device according to the present invention is a semiconductor memory device having an SRAM mounted thereon, wherein a normal operation precharge circuit and a test precharge circuit are provided for each bit line of the SRAM bit line pair. Each one end is connected in parallel, the normal operation precharge circuit is connected to a first power supply voltage, and the test precharge circuit is a second power supply voltage lower than the first power supply voltage. The normal operation precharge circuit connected to one bit line of the bit line pair is activated by a first activation signal and connected to the other bit line of the bit line pair. The normal operation precharge circuit is activated by the second activation signal, and the inspection precharge circuit connected to one bit line of the bit line pair is activated by the third activation signal. The test precharge circuit connected to the other bit line of the line pair is activated by a fourth activation signal, and the first to fourth activation signals are controlled independently of each other, and the semiconductor memory device When the first and fourth activation signals are activated or the second and third activation signals are activated before the read operation at the time of the inspection, one of the bit line pairs is activated. Precharge means for precharging the bit line and the other bit line of the bit line pair to different precharge potentials is provided.

  In the second semiconductor memory device of the present invention, the normal operation precharge circuit and the test precharge circuit are both P-channel type transistors, and the precharge means includes a P channel of the test precharge circuit. The type transistor and the P-channel type transistor of the normal operation precharge circuit are preferably composed of transistors having the same driving capability.

  A third semiconductor memory device according to the present invention is a semiconductor memory device having an SRAM mounted thereon, wherein a normal operation precharge circuit and a test precharge circuit are provided on each bit line of the SRAM bit line pair. Each one end is connected in parallel, the normal operation precharge circuit and the test precharge circuit are connected to the same power supply voltage, and are connected to one bit line of the bit line pair for normal operation The precharge circuit is activated by the first activation signal, the normal operation precharge circuit connected to the other bit line of the bit line pair is activated by the second activation signal, and the bit line pair is activated. The precharge circuit for inspection connected to one of the bit lines is activated by the third activation signal via the first level shift circuit and connected to the other bit line of the bit line pair. The inspection precharge circuit is activated by the fourth activation signal through the second level shift circuit, and the first to fourth activation signals are controlled independently of each other, and the semiconductor memory device is inspected. In some cases, before the read operation, by activating the first and fourth activation signals or activating the second and third activation signals, one bit line of the bit line pair And precharge means for precharging the other bit line of the bit line pair to different precharge potentials.

  In the third semiconductor memory device of the present invention, both of the normal operation precharge circuit and the test precharge circuit are P-channel transistors, and the precharge means includes the first or second level shifter. It is preferable to control the driving capability of the P-channel transistor of the inspection precharge circuit to be smaller than the driving capability of the P-channel transistor of the normal operation precharge circuit.

  The fourth semiconductor memory device according to the present invention is a semiconductor memory device having an SRAM mounted thereon, to which the first and second precharge circuits of each bit line of the SRAM bit line pair are connected. The precharge circuits are connected to the same power supply voltage, and the first precharge circuit connected to one bit line of the bit line pair has a first active level via a first level shift circuit. The second precharge circuit activated by the activation signal and connected to the other bit line of the bit line pair is activated by the second activation signal via the second level shift circuit, and The second activation signal and the second activation signal are controlled independently of each other, and switching between the normal operation mode and the inspection operation mode of the first and second precharge circuits is a control for controlling the first and second level shift circuits. By activating the first and second activation signals before the read operation at the time of testing the semiconductor memory device, the one bit line of the bit line pair and the bit line pair are Precharge means for precharging the other bit line to different precharge potentials is provided.

  In the fourth semiconductor memory device of the present invention, each of the precharge circuits is composed of a P-channel transistor, and the precharge means is connected to one of the precharge circuits by the first and second level shift circuits. It is preferable to control so that the drive capability of the P-channel transistor is smaller than the drive capability of the other P-channel transistor of each precharge circuit.

  The fifth semiconductor memory device of the present invention is a semiconductor memory device having an SRAM mounted thereon, and first and second precharge circuits are connected to each bit line of the SRAM bit line pair. Each of the precharge circuits is connected to the same power supply voltage, and the first precharge circuit connected to one bit line of the bit line pair has a first active circuit via a first delay circuit. A second precharge circuit activated by an activation signal and connected to the other bit line of the bit line pair is activated by a second activation signal via a second delay circuit, and The second activation signals are controlled independently of each other, and switching between the normal operation mode and the inspection operation mode of the precharge circuit is performed by a control circuit that controls the first and second delay circuits. apparatus By activating the first and second activation signals at the time of inspection before the read operation, one bit line of the bit line pair and the other bit line of the bit line pair are precharged differently. Precharge means for precharging to potential is provided.

  Further, in the fifth semiconductor memory device of the present invention, each precharge circuit is formed of a P-channel transistor, and the precharge means includes one of the precharge circuits by the first and second delay circuits. The rising operation of the P-channel transistor of each precharge circuit is advanced earlier than the rising operation of the other P-channel transistor of each precharge circuit, and the precharge of one P-channel transistor of each precharge circuit is insufficient. It is preferable to complete the charging operation.

  A first semiconductor memory device inspection method according to the present invention is a semiconductor memory device inspection method using the first semiconductor memory device according to the present invention, wherein the first or second normal operation precharge is performed. A first precharge potential is applied to one bit line of the bit line pair to which the circuit is connected, and the other bit line of the bit line pair to which the first or second test precharge circuit is connected A first step of applying a second precharge potential lower than the first precharge potential, and a second step of performing an operation margin inspection by performing a read operation after the first step.

  A second semiconductor memory device inspection method of the present invention is a semiconductor memory device inspection method using the second semiconductor memory device of the present invention, wherein the first or second normal operation precharge is performed. The first power supply voltage is applied to one bit line of the bit line pair to which the circuit is connected, and the other bit line of the bit line pair to which the first or second test precharge circuit is connected A first step of applying the second power supply voltage, and a second step of performing an operation margin inspection by performing a read operation after the first step.

  A third semiconductor memory device inspection method of the present invention is a semiconductor memory device inspection method using the third semiconductor memory device of the present invention, wherein the first or second normal operation precharge is performed. A power supply voltage is applied to one bit line of the bit line pair connected to the circuit, and the second bit line of the bit line pair connected to the first or second test precharge circuit is connected to the first bit line. A first step of applying a potential set lower than the power supply voltage by the first or second level shift circuit; and a second step of performing a read operation after the first step to perform an operation margin inspection. Have

  The fourth semiconductor memory device inspection method of the present invention is a semiconductor memory device inspection method using the fourth semiconductor memory device of the present invention, wherein the second precharge circuit is connected to the semiconductor memory device. A power supply voltage is applied to the other bit line of the bit line pair, and the power supply voltage is applied to one bit line of the bit line pair to which the first precharge circuit is connected by the first and second level shift circuits. A first step of applying a potential set lower than the first step, and a second step of performing an operation margin inspection by performing a read operation after the first step.

  The fifth semiconductor memory device inspection method of the present invention is a semiconductor memory device inspection method using the fifth semiconductor memory device of the present invention, wherein the second precharge circuit is connected to the second delay circuit. Activated by a second activation signal through a circuit, a power supply voltage is applied to the other bit line of the bit line pair to which the second precharge circuit is connected, and the first precharge circuit is It is activated by a first activation signal through a first delay circuit, and the rising operation of the first precharge circuit is made earlier than the rising operation of the second precharge circuit by the first delay circuit. The precharge operation is completed with insufficient precharge, and a potential lower than the power supply voltage is applied to one bit line of the bit line pair to which the first precharge circuit is connected. First Having between step and a second step of performing an operation margin test performs a read operation after the first step.

  According to the semiconductor memory device and the inspection method thereof according to the present invention, it is possible to screen a reliability failure due to a shortage of an SNM value due to a process failure or the like, which cannot be screened by a normal operation, by an initial inspection.

  Before describing the embodiment of the present invention, “read-out” failure due to lack of SNM value will be described with reference to the drawings.

  The “read-out” failure due to the shortage of the SNM value and the effects common to all the embodiments of the present invention will be described with reference to FIGS. 5 (a) to 5 (d).

  FIG. 5A shows each signal waveform during the operation of the SRAM memory cell, as in FIG. 3, and shows an enlarged waveform of a portion surrounded by a broken-line circle, which is shown in FIGS. 5B to 5D. ).

  BL / XBL in FIG. 5B indicates the waveform of the bit line pair. In this figure, a solid line indicates BL and a broken line indicates XBL. Further, it is assumed that BL = “H” and data “1” is stored in the memory cell. SN and XSN indicate waveforms of internal nodes of the memory cell, and SN = “H” and XSN = “L”.

  In the case of a normal cell, the waveforms of SN and XSN are as shown by solid lines. On the other hand, the waveforms SN and XSN of the internal node of the memory cell having a shortage of the SNM value as described above are as indicated by the alternate long and short dash line and the broken line, and the potential difference between the two becomes smaller than that of the normal cell. Such a failure mode deteriorates as the actual usage time elapses, and as shown in FIG. 5C, there is no potential difference between the internal nodes, and eventually a read failure occurs.

  Such poor reliability is desirably screened at the initial inspection. Therefore, in the present invention, means for screening at the initial inspection will be described below.

  In the present invention, as shown in FIG. 5D, the potential of the bit line XBL connected to the internal node XSN storing “L” data is set higher than that of the paired bit line BL immediately before the start of reading. Thereafter, when the read operation is started, in the conventional circuit, the internal waveform of the XSN indicated by the broken line, which is the “L” side node of the memory cell having a small SNM value in the initial state, as shown in FIG. Is a low voltage as shown in FIG. 5B, but in the circuit of the present invention, since the initial potential of the bit line XBL to be connected is set higher as described above, FIG. ), The potential is higher than in the case of reading with a conventional circuit. As a result, the potential of the paired SN is relatively low, and as a result, as shown in FIG. 5D, the potential difference shown in FIG. Thus, a malfunctioning memory can be brought to an early stage, and a memory cell having a shortage of SNM values that cannot be screened by normal operation can be determined to be defective in the initial state.

  From the above, conventionally, it was not possible to detect as an initial failure by performing a read inspection after applying different precharge potentials to one bit line of the bit line pair and the other bit line before reading. A memory cell having an insufficient SNM value can be determined to be defective in the initial state.

(Embodiment 1)
The semiconductor memory device according to the first embodiment of the present invention will be described below with reference to the drawings.

  1A is a diagram showing a circuit configuration of a semiconductor memory device according to the first embodiment of the present invention, FIG. 1B is a diagram showing a circuit configuration of memory cells constituting the semiconductor memory device, and FIG. (C) is a figure which shows an example of the operation | movement waveform of the main signal in this semiconductor memory device.

  1, the same reference numerals as those in FIGS. 2 and 3 denote the same components as those in the conventional semiconductor memory device, 101a to 101d are precharge circuits for normal operation, 102a to 102d are precharge circuits for screening tests, PRC0 is an activation signal for the normal operation precharge circuits 101a to 101d (first activation signal, hereinafter also referred to as a PRC0 signal), and PRCT is for testing connected to the positive logic side bit lines BL0 and BL1. The precharge circuits 102b and 102d are connected to the negative logic side bit lines BLX0 and BLX1. PRCB is an activation signal of the precharge circuits 102a and 102c (second activation signal, hereinafter also referred to as a PRCT signal) and PRCB. Activation signal (a third activation signal, hereinafter also referred to as a PRCB signal).

Hereinafter, the configuration of the semiconductor memory device according to the first embodiment will be described in more detail.
First, as shown in FIG. 1A, the semiconductor memory device of the first embodiment has a positive logic side bit line BL and a negative logic side bit line XBL as precharge circuits for precharging bit line pairs. Each bit line includes two precharge circuits, that is, precharge circuits 101a, 101b, 101c, and 101d for normal operation, and precharge circuits 102a, 102b, 102c, and 102d for screening test.

  The normal operation precharge circuits 101a, 101b, 101c, and 101d connected to the respective bit lines BL0, XBL0, BL1, and XBL1 are supplied with a normal operation precharge activation signal PRC0 = "L" (first activation signal). To precharge the bit line to the “H” = “Vdd” state. The screening test precharge circuits 102a and 102c connected to the positive logic side bit lines BL0 and BL1 are activated by the positive logic bit line precharge circuit activation signal PRCT (second activation signal), and the positive logic side A bit line precharge operation is performed. The precharges 102b and 102d for screening test connected to the negative logic side bit lines XBL0 and XBL1 are activated by a negative logic bit line precharge circuit activation signal PRCB (third activation signal), and the negative logic side bit lines Is precharged. Here, the screening test precharge circuits 102a to 102d are configured by a circuit having a function of precharging the bit line to a different potential from the normal operation precharge circuits 101a to 101d.

  In FIG. 1B, in the memory cell 103, Q11, Q12, Q13, Q14, Q15, and Q16 are transistors that constitute the memory cell 103.

Next, the operation of the semiconductor memory device according to the first embodiment will be described.
During normal operation, only the PRC0 signal (first activation signal) is activated, and only the normal operation precharge circuits 101a to 101d are operated. As shown in FIG. 3, the bit line pair is read out. Precharge to “H” = “Vdd” state before.

Next, the operation at the screening test for screening SNM deficient bits will be described.
At the time of this inspection, the bit line connected to the node holding the “L” data in the memory cell in the bit line pair is precharged to the first precharge potential, and the “H” in the memory cell in the bit line pair is precharged. “The bit line connected to the data holding node is precharged to a second precharge potential lower than the first precharge potential.

  For example, assume that when the memory cell 103 holds data “1”, the internal node SN is in the “H” state and the complementary node XSN is in the “L” state.

  Prior to reading the corresponding cell data, data complementary to the data held in the corresponding cell is read onto the bit line. That is, “L” data complementary to the “H” state held in the positive logic side internal node SN is read out to the positive logic side bit line BL0, and the negative logic side internal node is connected to the negative logic side bit line XBL0. Read XSN “L” data and complementary “H” data. This can be easily performed by using an inspection pattern in which “H” and “L” are alternately written / read, such as one of the inspection patterns normally used in the inspection of the semiconductor memory device, for example, “checker pattern”. . As a result, the positive logic side bit line BL0 is in the “L” state, and the negative logic side bit line XBL0 is in the “H” state. At this time, the potential of the bit line in the “H” state is a normal “H” = “Vdd” potential, which is equal to the first precharge potential.

  Thereafter, the positive logic side precharge circuit activation signal PRCT is activated to precharge BL0 in the “L” state. At this time, since the screening test precharge circuit 102 has a function of precharging to a potential lower than the normal “H” = “Vdd” potential, the positive logic side bit line BL 0 has a potential lower than “H”. Is the second precharge potential. The negative logic side bit line XBL0 does not need to be precharged because the potential is equal to the first precharge potential “H” = “Vdd” by the sense amplifier in the immediately preceding read operation.

  As a result, a potential difference set by the screening test precharge circuit 102 is generated in the bit line pair BL0 / XBL0. Thereafter, if the read operation is performed in the same manner as usual, as described above, the SNM value is erroneously read in the memory cell 103 having a small margin with respect to the detection level of the sense amplifier, and is judged to be defective and screened. It will be.

  On the other hand, when the memory cell 103 in which “H” is written in the negative logic side node XSN of the memory cell holds “0” data, the negative logic side precharge circuit activation signal PRCB is activated. Can be inspected as well.

  Next, more detailed contents of the precharge circuit are shown in FIG. The normal operation precharge activation signal PRC0 (first activation signal) is connected to the precharge transistors Q1 and Q2 constituting the normal operation precharge circuits 101a and 101b, respectively. Precharge to potential “Vdd”. The screening test precharge activation signals PRCT / PRCB (second and third activation signals) are connected to transistors Q3 and Q4 constituting the screening test precharge circuits 102a and 102b, respectively. The pair is precharged to the power supply potential “Vdd” (ie, these signals PRCT / PRCB precharge the bit line pair in the “L” = “Vss” state and the bit line pair in the “H” = “Vdd” state. Do not precharge).

  The drive capability of these four transistors is set as Q1 = Q2> Q3 = Q4, and the transistors of Q1 and Q2 have sufficient drive capability for precharge operation during normal operation, but the transistors of Q3 and Q4 The driving capability is smaller than Q1 and Q2, and the driving capability to precharge the bit line sufficiently to “H” = “Vdd” level is not provided at the normal operation timing. Therefore, a potential difference can be generated in the bit line pair by using the transistors Q3 and Q4 during the screening test.

  As a result, in the first embodiment, it becomes possible to screen the memory cell 103 having an insufficient SNM value, which is not determined to be defective in the normal inspection, by the screening inspection, and in the market of the semiconductor memory device that has performed such an inspection. Reliability can be improved.

  As described above, according to the semiconductor memory device according to the first embodiment, in the semiconductor memory device mounting the SRAM, the normal operation precharge circuit and the test precharge circuit are provided for each bit line of the SRAM bit line pair. The normal operation precharge circuit and the inspection precharge circuit are connected to the same power supply voltage, and the normal operation precharge circuit connected to each bit line of the bit line pair is the same. The test precharge circuit that is activated by the first activation signal and connected to one bit line of the bit line pair is activated by the second activation signal and is connected to the other bit line of the bit line pair The precharge circuit for use is activated by the third activation signal, and the first to third activation signals are controlled independently of each other. At the time of inspection, before the read operation, One or the other bit of the bit line pair is activated by activating the second or third activation signal in a state where the other or one bit line of the bit line pair is at the first precharge potential. Since the line is set to the second precharge potential and one bit line of the bit line pair and the other bit line of the bit line pair are precharged to different precharge potentials, screening is performed in normal operation. An effect is obtained in which a reliability failure due to a shortage of SNM values due to a process failure that cannot be performed can be screened in an initial inspection.

(Embodiment 2)
Hereinafter, a semiconductor memory device according to a second embodiment of the present invention will be described with reference to the drawings.
Since the basic circuit configuration of the semiconductor memory device according to the second embodiment is shown in FIG. 1 which is the same as that of the first embodiment, the description thereof is omitted.

In the second embodiment, the circuit configuration of the precharge circuit is different from that of the first embodiment.
Specifically, in the first embodiment shown in FIG. 7, the normal operation precharge transistor, that is, the transistors Q1 and Q2 constituting the normal operation precharge circuit, and the screening test precharge transistor, that is, the screening test. The transistors Q3 and Q4 constituting the precharge circuit are both made of a P-type semiconductor, but in the second embodiment shown in FIG. 8, the normal operation precharge transistors Q1 and Q2 are made of a P-type semiconductor. The screening test precharge transistors Q3 and Q4 are formed of an N-type semiconductor.

  Along with this, the polarity of the activation signal PRCT / PRCB (second and third activation signals) of the screening test precharge circuit is also inverted, and these signals XPRCT / XPRCB are “H”. In the “Vdd” state, the bit line pair is precharged. In the “L” = “Vss” state, the bit line pair is not precharged.

  In the second embodiment, similarly to the first embodiment, the memory cell 103 having an insufficient SNM value is screened. In the second embodiment, the screening test precharge transistor is an N-type semiconductor transistor. Therefore, when the screening test precharge circuit is activated, the source potential of the test precharge transistor made of the N-type semiconductor transistor is “Vdd” and its gate potential is also “VDD”. The precharge potential of the pair is only precharged to a level lower than “Vdd” by the threshold voltage of the transistor.

  As a result, in the second embodiment, as in the first embodiment, a potential difference can be provided to the bit line pair before the read operation during the screening test. As a result, in the second embodiment, it becomes possible to screen the memory cell 103 having an insufficient SNM value that is not determined to be defective by a normal inspection, and the reliability of the semiconductor memory device that has performed such an inspection is improved in the market. be able to.

  In the first embodiment, since the potential difference is provided in the precharge potential of the bit line due to the difference in driving capability of the transistors, the potential difference to be generated varies depending on the inspection temperature and the precharge time. Since the voltage appears as a potential difference, a more stable potential difference can be generated than in the first embodiment.

(Embodiment 3)
Hereinafter, a semiconductor memory device according to a third embodiment of the present invention will be described with reference to the drawings.

  As shown in FIG. 6A, the semiconductor memory device according to the third embodiment is provided as a precharge circuit for precharging a bit line pair for each bit line, that is, a positive logic side bit line and a negative logic side. Each bit line is provided with two precharge circuits, that is, normal operation precharge circuits 101a, 101b, 101c, and 101d and screening test precharge circuits 102a, 102b, 102c, and 102d. is there.

  That is, in the first embodiment, the normal operation precharge circuit connected to the positive logic side bit line BL and the normal operation precharge circuit connected to the negative logic side bit line XBL are both activated by the precharge activation signal PRC0. However, in the semiconductor memory device of the third embodiment, as shown in FIG. 6A, the normal operation precharge circuit 101a connected to the positive logic side bit line BL and the negative logic side bit line XBL are connected. The normal operation precharge circuit 101b connected to is activated by different activation signals PRC0T and PRC0B.

  In FIG. 6B, Q11, Q12, Q13, Q14, Q15, and Q16 are transistors constituting the memory cell 103 as in FIG. 1B.

  Next, more detailed contents of the precharge circuit are shown in FIG. 9, Q1 and Q2 are transistors constituting normal operation precharge circuits 101a and 101b, and Q3 and Q4 are transistors constituting screening test precharge circuits 102a and 102b, as in FIG. The gates of the transistors Q1, Q2, Q3, and Q4 are controlled by precharge activation signals PRC0T, PRC0B, PRCT, and PRCB.

  Here, since the precharge transistors Q1, Q2, Q3, and Q4 are composed of P-type transistors, these activation signals PRC0T, PRC0B, PRCT, and PRCB are in the “L” (= “Vss”) state. The precharge transistors Q1, Q2, Q3, and Q4 are turned on to precharge the bit line, and when the activation signals PRC0T, PRC0B, PRCT, and PRCB are in the “H” (= “Vdd”) state, the precharge transistor Q1 , Q2, Q3, and Q4 are nonconductive and do not precharge the bit lines. Transistors Q1 and Q2 are connected to a power supply Vdd0, and transistors Q3 and Q4 are connected to another power supply Vdd1, where the power supply Vdd0 and the power supply Vdd1 can be set independently.

  In the configuration of the third embodiment, if the activation signals PRC0T and PRC0B are driven simultaneously and Vdd0 = Vdd1 = Vdd, the same operation as in the first embodiment can be performed.

  Further, since the power supply Vdd0 and the power supply Vdd1 can be controlled independently, in the precharge at the screening test, for example, when “H” data is stored in the memory cell 103, the positive logic connected to “H”. When inspecting the side bit line BL, by activating the activation signals PRCT and PRC0B and setting the potential such that Vdd1 <Vdd0, a desired potential difference can be set for the bit line pair. .

  At this time, the driving capabilities of the transistors Q3 and Q4 do not need to be smaller than those of the transistors Q1 and Q2, and may be equal. At this time, it is possible to set Vdd1 <Vdd0 <Vdd, Vdd <Vdd1 <Vdd0, Vdd1 <Vdd <Vdd0 with respect to the normal power supply voltage Vdd, and set more detailed screening conditions. It becomes possible to do.

  In the first and second embodiments, data that is complementary to the data stored in the memory cell to be inspected, such as a “checker pattern” or “column bar”, is used as a predetermined bit line. However, in the third embodiment, the bit line potential is arbitrarily set for each precharge operation before reading. Therefore, the setting of the inspection pattern is not limited to the above, and the degree of freedom is increased and the screening effect can be further enhanced.

  As described above, according to the semiconductor memory device according to the third embodiment, in the semiconductor memory device equipped with the SRAM, the normal operation precharge circuit and the test precharge are applied to each bit line of the SRAM bit line pair. One end of the circuit is connected in parallel, the normal operation precharge circuit is connected to the first power supply voltage, the test precharge circuit is connected to the second power supply voltage lower than the first power supply voltage, and the bit line The normal operation precharge circuit connected to one bit line of the pair is activated by the first activation signal, and the normal operation precharge circuit connected to the other bit line of the bit line pair is the second activation signal. And the test precharge circuit connected to one bit line of the bit line pair is activated by a third activation signal and connected to the other bit line of the bit line pair. The first activation circuit is activated by the fourth activation signal, and each of the first to fourth activation signals is controlled independently of each other. By activating or activating the second and third activation signals, one bit line of the bit line pair and the other bit line of the bit line pair are precharged to different precharge potentials. The normal operation precharge circuit and the test precharge circuit provided for each bit line are connected to different power sources, and the four precharge circuits are activated by different activation signals. Since a desired potential difference is obtained for the line pair, it is possible to set finer screening conditions, and in this way, precharge operation before readout By being able to arbitrarily set the bit line potential bets increases the flexibility of the test pattern, it is possible to enhance the screening effect.

(Embodiment 4)
Hereinafter, a semiconductor memory device according to a fourth embodiment of the present invention will be described with reference to the drawings.
In the third embodiment, by controlling the source potentials of the precharge transistors Q1, Q2, Q3, Q4 for normal operation and inspection shown in FIG. 9, the precharge circuits 101a, 101b, 102a, The bit line precharge potential by 102b is controlled to generate a potential difference in the bit line pair.

  On the other hand, in the fourth embodiment, as shown in FIG. 10, the source potentials of the normal operation precharge transistors Q1, Q2 and the screening test precharge transistors Q3, Q4 are set to Vdd. The voltages of the activation signals PRCT and PRCB for controlling the inspection precharge transistors Q3 and Q4 are controlled by the level shift circuits 105a and 105b connected to the screening inspection precharge transistors Q3 and Q4. . As a result, the driving capability of the screening test precharge transistors Q3 and Q4 for driving the bit line is controlled, and the driving capability difference of the transistors as shown in the first embodiment is provided for this, so that the bit line pair In this embodiment, the same effect as that of the first embodiment can be obtained in the fourth embodiment.

  As described above, according to the semiconductor memory device according to the fourth embodiment, in the semiconductor memory device mounting the SRAM, the normal operation precharge circuit and the test precharge circuit are provided for each bit line of the SRAM bit line pair. Are connected in parallel, each precharge circuit is connected to the same power supply voltage, the normal operation precharge circuit connected to one bit line of the bit line pair is activated by the first activation signal, The normal operation precharge circuit connected to the other bit line of the line pair is activated by the second activation signal, and the test precharge circuit connected to one bit line of the bit line pair is the third activation signal. And the test precharge circuit connected to the other bit line of the bit line pair is activated by the fourth activation signal, and the first to fourth activation signals are controlled independently of each other. One bit line of the bit line pair is activated by activating the first and fourth activation signals or activating the second and third activation signals before the read operation at the time of inspection. And the other bit line of the bit line pair are precharged to different precharge potentials, the source potentials of the normal operation and inspection precharge transistors are set to Vdd, and the screening inspection precharge transistors The voltage of the activation signal for controlling the voltage is controlled by a level shift circuit connected to the screening test precharge transistors Q3 and Q4. At this time, a potential difference is applied to the bit line pair by providing a drive capability difference of the precharge transistors. As in the first embodiment, the screen Reliability failure due SNM value shortage due process defect like that can not be grayed, it is possible to obtain the effect of screening at initial testing.

(Embodiment 5)
Hereinafter, a semiconductor memory device according to a fifth embodiment of the present invention will be described with reference to the drawings.
In the fourth embodiment shown in FIG. 10, the normal inspection precharge circuits 101a and 101b, the screening inspection precharge circuits 102a and 102b, and the control signals PRCT for controlling the transistors Q1 to Q4 of the respective precharge circuits. , PRCB, PRC0T, and PRC0B are provided to control each precharge circuit. However, in the fifth embodiment shown in FIG. 11, a test signal for switching functions during normal operation and inspection operation. The output signal level of the level shift circuits 51a and 51b is controlled by TEST, thereby controlling each precharge circuit and changing the drive capability of each precharge transistor to generate a potential difference in the bit line pair. It is made to let you.

  That is, the semiconductor memory device according to the fifth embodiment is provided with one precharge circuit for each bit line as a precharge circuit for precharging a bit line pair, as shown in FIG. Are provided with precharge circuits 101a, 101b, 101c, 101d on the bit lines BL0, XBL0, BL1, XBL1, and precharge circuits 101a, 101c connected to the positive logic side bit line BL and precharge circuits connected to the negative logic side bit line XBL. The charge circuits 101b and 101d are configured to be activated via first and second level shift circuits 51a and 51b controlled by the control circuit 50 by separate activation signals PRCT and PRCB, respectively.

  Further, as shown in FIG. 11B, the gate of the transistor Q1 constituting the precharge circuit connected to the positive logic side bit line BL is leveled according to the control signal TEST from the control circuit 50 in the level shift circuit 51a. The gate of the transistor Q2, which is controlled by the shifted activation signal PRCT and forms the precharge circuit connected to the negative logic side bit line XBL, is level-shifted by the level shift circuit 51b according to the control signal TEST from the control circuit 50. The activation signal PRCB is controlled.

  During the normal operation, when the test signal TEST = “L” from the control circuit 50, the level shift circuits 51a and 51b do not perform the level shift operation and the normal voltage level “H” = “Vdd” or “ Output is performed with L ”=“ Vss ”. On the other hand, during the test operation, that is, when the test signal TEST = “H” from the control circuit 50, the levels of the precharge activation signals PRCT and PRCB are controlled by the level shift circuits 51a and 51b, and the precharge transistors Q1, Let Q2 be a drive capability lower than usual. As a result, the precharge potential of the “L” side bit line is not precharged until “Vdd”, and a potential difference occurs in the bit line before reading, and the aforementioned screening effect appears. Also in the fifth embodiment, the same effect as in the first embodiment can be obtained.

  According to the semiconductor memory device according to the fifth embodiment as described above, in the semiconductor memory device mounting the SRAM, the precharge circuit is connected to each bit line of the SRAM bit line pair, and each precharge circuit is the same. The first precharge circuit connected to one bit line of the bit line pair is activated by the first activation signal via the first level shift circuit, and the other of the bit line pair is activated. The second precharge circuit connected to the bit line is activated by the second activation signal via the second level shift circuit, and the first and second activation signals are controlled independently of each other. The switching between the normal operation mode and the inspection operation mode of each of the first and second precharge circuits is performed by a control circuit that controls the first and second level shift circuits. Means for precharging one bit line of the bit line pair and the other bit line of the bit line pair to different precharge potentials by activating the first and second activation signals before the output operation. The output signal level of the first and second level shift circuits is controlled by the test signal TEST for switching the function between the normal operation and the inspection operation, and the potential difference is generated in the bit line pair by changing the driving capability of the precharge transistor. For example, the precharge potential of the “L” side bit line is not precharged up to “Vdd”, and a potential difference occurs in the bit line pair before reading, so that a screening effect appears. Similar to the first embodiment, an initial inspection is performed for a reliability failure due to a shortage of SNM values due to a process failure that cannot be screened by normal operation It is possible to obtain the screening can effectively.

(Embodiment 6)
Hereinafter, a semiconductor memory device according to a sixth embodiment of the present invention will be described with reference to the drawings.
As shown in FIG. 12, the semiconductor memory device according to the sixth embodiment has a function of making the pulse width of a precharge control signal, which is an activation signal of the precharge circuit, variable between a normal operation and an inspection operation. It is made to have.

  That is, the semiconductor memory device according to the sixth embodiment is provided with one precharge circuit for each bit line as a precharge circuit for precharging a bit line pair, as shown in FIG. Are provided with precharge circuits 101a, 101b, 101c, 101d on the bit lines BL0, XBL0, BL1, XBL1, and precharge circuits 101a, 101c connected to the positive logic side bit line BL and precharge circuits connected to the negative logic side bit line XBL. The charge circuits 101b and 101d are activated by separate activation signals PRCT and PRCB from the first and second pulse width generation circuits 61a and 61b controlled by the control circuit 60, respectively.

  As shown in FIG. 12B, the gate of the transistor Q1 constituting the precharge circuit connected to the positive logic side bit line BL is in response to the control signal TEST from the control circuit 60 in the pulse width generation circuit 61a. The gate of the transistor Q2, which is controlled by the signal PRCT obtained by delaying the activation signal PRCOT and forms the precharge circuit connected to the negative logic side bit line XBL, is a control signal from the control circuit 60 by the pulse width generation circuit 61b. It is controlled by a signal PRCB obtained by delaying the activation signal PRCOT in accordance with TEST.

  Normally, the circuit 61 for generating a pulse width is composed of a delay circuit 41 and logic circuits 40a and 40b as shown in FIG. 13A, and the delay circuit 41 is an inverter 42 as shown in FIG. 13C. It is configured by multi-stage connection. This inverter 42 is formed by connecting a P-channel transistor 42a and an N-channel transistor 42b in series between a Vdd power source and a Vss power source, the common gate of both transistors being an input node, and the connection point of both transistors being an output. It is a node.

  Then, as shown in FIG. 13 (d), by providing a circuit for inputting a TEST signal for switching between the normal operation and the inspection operation, a part of the inverter 42 constituting the pulse generating circuit is used to The delay time of the delay circuit 41 can be made variable, that is, the output pulse width thereof can be made variable, and thus the driving capability of the precharge transistor can be switched by the output, as shown in FIGS. 12 (a) and 12 (b). The pulse width generation circuits 61a and 61b to which the first and second activation signals PRCOT and PRCOB of the sixth embodiment are input can be easily realized.

  FIG. 13 (b) shows a pulse width generation circuit 61a that receives the first activation signal PRCOT of the sixth embodiment, and FIG. 13 (d) shows the pulse width generation circuit. One inverter constituting the delay circuit in 61a is shown. This inverter is formed by connecting P-channel transistors 43a and 43b connected in parallel between the N-channel transistor 42b of the inverter 42 shown in FIG. 13C and the low-potential-side power supply Vss. The gate of the channel transistor 43a is connected to the high potential side power supply Vdd, and the test signal TEST from the control circuit 60 is input to the gate of the other P channel transistor 43b.

  In this way, during the screening test, the test signal TEST from the control circuit 60 is set to “L” level so that the delay time of the delay circuit 41 is shortened by turning on the P-channel transistor 43b, and the precharge pulse width is shortened. By doing so, the precharge operation can be completed before the bit line is sufficiently precharged from the “L” level to the “H” level, and as a result, a bit line potential difference before reading is generated. And screening can be performed as described above.

  Here, as described above, in the screening method in the prior art, screening is performed by accelerating the operation timing of the sense amplifier. However, the operation timing of the sense amplifier is recently increased due to the lower voltage and higher speed of the semiconductor element. Since the design has almost no margin, it is almost impossible to advance the operation timing substantially by the above-described conventional method. On the other hand, in the sixth embodiment, precharge that is not directly related to the access speed is performed. Since the time is controlled, this screening can be easily realized without impairing the operation margin of the SRAM. In the sixth embodiment, the same effect as in the first embodiment is obtained in this way. It can be obtained.

  According to the semiconductor integrated device according to the sixth embodiment as described above, in the semiconductor memory device mounting the SRAM, a precharge circuit is connected to each bit line of the SRAM bit line pair, and each precharge circuit is The first precharge circuit connected to the same power supply voltage and connected to one bit line of the bit line pair is activated by the first activation signal via the first delay circuit, and the other of the bit line pair is activated. The second precharge circuit connected to the bit line is activated by the second activation signal via the second delay circuit, and the first and second activation signals are controlled independently of each other, Switching between the normal operation mode and the inspection operation mode of the precharge circuit is performed by a control circuit that controls the first and second delay circuits, and the first and second activation signals before the read operation at the time of inspection. A means for precharging one bit line of the bit line pair and the other bit line of the bit line pair to different precharge potentials by being activated is configured. The circuit is composed of a P-channel transistor, and means for precharging one bit line of the bit line pair and the other bit line of the bit line pair to different precharge potentials is provided by the first and second delay circuits. The rise operation of one P-channel transistor of the precharge circuit is made earlier than the rise operation of the other P-channel transistor of each precharge circuit, so that the precharge of one P-channel transistor of each precharge circuit is not performed. Since it was controlled to complete the precharge operation in a sufficient state During the screening test, the precharge pulse width is shortened so that the precharge operation can be completed before the bit line is sufficiently precharged from the “L” level to the “H” level. The previous bit line potential difference can be generated, and screening can be performed reliably. Further, in the conventional screening method, the operation timing of the sense amplifier is designed to have almost no margin with the recent reduction in voltage and speed of the semiconductor element, so that the operation timing is substantially advanced for screening. In the sixth embodiment, since the precharge time that is not directly related to the access speed is controlled, this screening can be realized easily without deteriorating the operation margin of the SRAM. It is something that can be done.

  As described above, the semiconductor memory device and the inspection method thereof according to the present invention can screen the reliability failure due to the shortage of the SNM value due to the process failure or the like in the initial inspection, which cannot be screened in the normal operation. This is useful for SRAM screening methods and the like.

1 is a diagram for explaining a semiconductor memory device according to a first embodiment of the present invention, and is a diagram illustrating an overall circuit configuration of the semiconductor memory device according to the first embodiment; It is a figure explaining the semiconductor memory device by Embodiment 1 of this invention, and is a figure which shows the circuit structure of the memory cell which comprises the said semiconductor memory device. It is a figure explaining the semiconductor memory device by Embodiment 1 of this invention, and is a figure which shows an example of the operation waveform of the main signal in the said semiconductor memory device. The figure which shows the example of the simplified circuit structure of general SRAM The figure which shows an example of the operation waveform of the main signal in the circuit structure shown in FIG. Main waveform diagram explaining read operation in conventional SRAM Enlarged waveform diagram for explaining a read operation in a conventional SRAM The figure explaining the main signal waveform at the time of operation | movement of the conventional SRAM memory cell. The figure explaining the waveform of bit line pair BL / XBL at the time of operation | movement of the conventional SRAM memory cell. The figure explaining the static noise margin shortage state at the time of operation of the conventional SRAM memory cell FIG. 6 is a diagram for explaining a state in which a conventional SRAM memory cell is caused to malfunction at an early stage during operation. The figure which shows the circuit structure explaining the semiconductor memory device by Embodiment 3 of this invention A circuit diagram showing a memory cell constituting a semiconductor memory device according to a third embodiment of the present invention. Circuit diagram showing a configuration of a precharge circuit of the semiconductor memory device according to the first embodiment. Circuit diagram showing a configuration of a precharge circuit of a semiconductor memory device according to a second embodiment of the present invention. Circuit diagram showing a configuration of a precharge circuit of the semiconductor memory device according to the third embodiment. Circuit diagram showing a configuration of a precharge circuit of a semiconductor memory device according to a fourth embodiment of the present invention. It is a figure explaining the semiconductor memory device by Embodiment 5 of this invention, and is a figure which shows the whole circuit structure of the semiconductor memory device of Embodiment 5. FIG. It is a figure explaining the semiconductor memory device by Embodiment 5 of this invention, and is a circuit diagram which shows the structure of the precharge circuit of this semiconductor memory device. It is a figure explaining the semiconductor memory device by Embodiment 6 of this invention, and is a figure which shows the whole circuit structure of the semiconductor memory device of Embodiment 6. FIG. It is a figure explaining the semiconductor memory device by Embodiment 6 of this invention, and is a circuit diagram which shows the structure of the precharge circuit of this semiconductor memory device. It is a figure explaining the semiconductor memory device by Embodiment 6 of this invention, and is a wave form diagram which shows an example of the operation waveform of the main signal in the said semiconductor memory device. Circuit diagram explaining a normal pulse width generator Circuit diagram for explaining a pulse width generation circuit for generating a precharge control signal of the semiconductor memory device according to the sixth embodiment. Circuit diagram for explaining an inverter constituting the normal pulse width generation circuit. Circuit diagram illustrating an inverter constituting a pulse width generation circuit of a semiconductor memory device according to the sixth embodiment.

Explanation of symbols

PRC0 Normal operation precharge activation signal PRCT Screening inspection positive logic bit line precharge circuit activation signal PRCB Screening inspection negative logic bit line precharge circuit activation signal 101a, 101b, 101c, 101d Normal operation Precharge circuit 102a, 102b, 102c, 102d Precharge circuit for screening test 103 Memory cell WL Word line activation signal SA Sense amplifier activation signal BL0 Positive logic side bit line XBL0 Negative logic side bit line SN Positive logic side memory Cell internal node XSN Negative logic side memory cell internal node Q1, Q2, Q3, Q4 Precharging transistors

Claims (17)

A semiconductor memory device equipped with SRAM,
One end of each of the first normal operation precharge circuit and the first inspection precharge circuit is connected in parallel to one bit line of the SRAM bit line pair,
Each one end of the second normal operation precharge circuit and the second inspection precharge circuit is connected in parallel to the other bit line of the SRAM bit line pair,
The first and second normal operation precharge circuits and the first and second test precharge circuits are connected to the same power supply voltage;
Both the first and second normal operation precharge circuits connected to one and the other bit lines of the bit line pair are activated by a first activation signal,
The first inspection precharge circuit connected to one bit line of the bit line pair is activated by a second activation signal;
A second test precharge circuit connected to the other bit line of the bit line pair is activated by a third activation signal;
The first to third activation signals are controlled independently of each other;
By activating the second activation signal while the other bit line of the bit line pair is at the first precharge potential before the read operation at the time of inspection of the semiconductor memory device, the bit The third activation signal is activated in a state where one bit line of the line pair is set to the second precharge potential or one bit line of the bit line pair is at the first precharge potential. As a result, the other bit line of the bit line pair is set to the second precharge potential, and one bit line of the bit line pair and the other bit line of the bit line pair are precharged to different precharge potentials. Provided with pre-charging means for charging,
A semiconductor memory device. The semiconductor memory device according to claim 1,
The sense amplifier that sets the potential of each bit line of the bit line pair is:
One bit line of the bit line pair is set to a predetermined logic potential of H or L level according to the data held in the memory cell before the read operation at the time of inspection of the semiconductor memory device. Is set to a logic potential complementary to the logic potential set to the one bit line,
The precharge means activates the second activation signal when the other bit line of the bit line pair is set to an H level logic potential equal to the first precharge potential by the sense amplifier. One bit line set to the L level logic potential is charged to a second precharge potential lower than the H level logic potential, and the one bit line is set to the first precharge by the sense amplifier. When the H level logic potential equal to the potential is set, the third activation signal is activated, and the other bit line set to the L level logic potential is set to the second level lower than the H level logic potential. To the precharge potential of
A semiconductor memory device. The semiconductor memory device according to claim 1,
The first and second normal operation precharge circuits and the first and second test precharge circuits are both P-channel transistors,
The precharge means comprises a transistor in which the P channel type transistors of the first and second test precharge circuits have a smaller driving capability than the P channel type transistors of the first and second normal operation precharge circuits. ,
A semiconductor memory device. The semiconductor memory device according to claim 1,
The first and second normal operation precharge circuits comprise P-channel transistors,
The first and second test precharge circuits comprise N-channel transistors,
The precharge means applies a first precharge potential to the bit line to which the first and second normal operation precharge circuits are connected, and the first and second test precharge circuits are connected. Precharging is performed by applying a second precharge potential lower than the first precharge potential by the threshold voltage of the N-channel transistor to the bit line formed,
A semiconductor memory device. A semiconductor memory device equipped with SRAM,
One end of each of the first normal operation precharge circuit and the first inspection precharge circuit is connected in parallel to one bit line of the SRAM bit line pair,
Each one end of the second normal operation precharge circuit and the second inspection precharge circuit is connected in parallel to the other bit line of the SRAM bit line pair,
The first and second normal operation precharge circuits are connected to a first power supply voltage;
The first and second test precharge circuits are connected to a second power supply voltage lower than the first power supply voltage;
A first normal operation precharge circuit connected to one bit line of the bit line pair is activated by a first activation signal;
A second normal operation precharge circuit connected to the other bit line of the bit line pair is activated by a second activation signal;
The first inspection precharge circuit connected to one bit line of the bit line pair is activated by a third activation signal;
A second test precharge circuit connected to the other bit line of the bit line pair is activated by a fourth activation signal;
The first to fourth activation signals are controlled independently of each other,
The bit line is activated by activating the first and fourth activation signals or activating the second and third activation signals before a read operation at the time of testing the semiconductor memory device. Precharge means for precharging one bit line of the pair and the other bit line of the bit line pair to different precharge potentials;
A semiconductor memory device. The semiconductor memory device according to claim 5.
The first and second normal operation precharge circuits and the first and second test precharge circuits are both P-channel transistors,
The precharge means includes a transistor in which the P channel type transistors of the first and second test precharge circuits and the P channel type transistors of the first and second normal operation precharge circuits have the same driving capability. Become,
A semiconductor memory device. A semiconductor memory device equipped with SRAM,
One end of each of the first normal operation precharge circuit and the first inspection precharge circuit is connected in parallel to one bit line of the SRAM bit line pair,
Each one end of the second normal operation precharge circuit and the second inspection precharge circuit is connected in parallel to the other bit line of the SRAM bit line pair,
The first and second normal operation precharge circuits and the first and second test precharge circuits are connected to the same power supply voltage;
A first normal operation precharge circuit connected to one bit line of the bit line pair is activated by a first activation signal;
A second normal operation precharge circuit connected to the other bit line of the bit line pair is activated by a second activation signal;
The first inspection precharge circuit connected to one bit line of the bit line pair is activated by a third activation signal via the first level shift circuit,
The second inspection precharge circuit connected to the other bit line of the bit line pair is activated by a fourth activation signal via the second level shift circuit,
The first to fourth activation signals are controlled independently of each other,
The bit line is activated by activating the first and fourth activation signals or activating the second and third activation signals before a read operation at the time of testing the semiconductor memory device. Precharge means for precharging one bit line of the pair and the other bit line of the bit line pair to different precharge potentials;
A semiconductor memory device. The semiconductor memory device according to claim 7,
The first and second normal operation precharge circuits and the first and second test precharge circuits are both P-channel transistors,
In the precharge means, the first and second level shift circuits allow the first and second inspection precharge circuits to drive the P-channel transistors in the first and second normal operation precharges. Control to be smaller than the driving capability of the P-channel transistor of the circuit,
A semiconductor memory device. A semiconductor memory device equipped with SRAM,
First and second precharge circuits are connected to one and the other bit lines of the SRAM bit line pair,
The first and second precharge circuits are connected to the same power supply voltage,
A first precharge circuit connected to one bit line of the bit line pair is activated by a first activation signal via a first level shift circuit;
A second precharge circuit connected to the other bit line of the bit line pair is activated by a second activation signal via a second level shift circuit;
The first and second activation signals are controlled independently of each other;
Switching between the normal operation mode and the test operation mode of the first and second precharge circuits is performed by a control circuit that controls the first and second level shift circuits,
By activating the first and second activation signals before the read operation at the time of testing the semiconductor memory device, one bit line and the other bit line of the bit line pair are precharged differently from each other. Provided with a precharge means for precharging to a potential;
A semiconductor memory device. The semiconductor memory device according to claim 9.
The first and second precharge circuits comprise P-channel transistors,
In the precharge means, the first and second level shift circuits cause the drive capability of one P-channel transistor of the first and second precharge circuits to be the other of the first and second precharge circuits. Control to be smaller than the driving capability of the P-channel transistor of
A semiconductor memory device. A semiconductor memory device equipped with SRAM,
First and second precharge circuits are connected to one and the other bit lines of the SRAM bit line pair,
The first and second precharge circuits are connected to the same power supply voltage,
A first precharge circuit connected to one bit line of the bit line pair is activated by a first activation signal via a first delay circuit;
A second precharge circuit connected to the other bit line of the bit line pair is activated by a second activation signal via a second delay circuit;
The first and second activation signals are controlled independently of each other,
Switching between the normal operation mode and the inspection operation mode of the first and second precharge circuits is performed by a control circuit that controls the first and second delay circuits,
By activating the first and second activation signals before the read operation during the inspection of the semiconductor device, one bit line and the other bit line of the bit line pair are made to have different precharge potentials. Equipped with precharge means for precharging up to,
A semiconductor memory device. The semiconductor memory device according to claim 11,
The first and second precharge circuits comprise P-channel transistors,
The precharge means performs a rising operation of one P-channel transistor of the first and second precharge circuits with the other of the first and second precharge circuits by the first and second delay circuits. A precharge operation is completed in a state where the precharge of one P channel transistor of the first and second precharge circuits is insufficient before the rising operation of the P channel transistor.
A semiconductor memory device. A method for inspecting a semiconductor memory device according to claim 1, comprising:
A first precharge potential is applied to one bit line of the bit line pair to which the first or second normal operation precharge circuit is connected, and the first or second test precharge circuit is Applying a second precharge potential lower than the first precharge potential to the other bit line of the connected bit line pair;
A second step of performing an operation margin inspection by performing a read operation after the first step;
A method of inspecting a semiconductor memory device. A method for inspecting a semiconductor memory device according to claim 5, comprising:
A first power supply voltage is applied to one bit line of the bit line pair to which the first or second normal operation precharge circuit is connected, and the first or second test precharge circuit is connected. A first step of applying the second power supply voltage to the other bit line of the paired bit lines;
A second step of performing an operation margin inspection by performing a read operation after the first step;
A method of inspecting a semiconductor memory device. 8. A method for inspecting a semiconductor memory device according to claim 7, comprising:
A power supply voltage is applied to one bit line of the bit line pair to which the first or second normal operation precharge circuit is connected, and the first or second test precharge circuit is connected. A first step of applying a potential set lower than the power supply voltage by the first or second level shift circuit to the other bit line of the bit line pair;
A second step of performing an operation margin inspection by performing a read operation after the first step;
A method of inspecting a semiconductor memory device. A method for inspecting a semiconductor memory device according to claim 9, comprising:
A power supply voltage is applied to the other bit line of the bit line pair connected to the second precharge circuit, and the first bit line of the bit line pair connected to the first precharge circuit is applied to the first bit line. A first step of applying a potential set lower than the power supply voltage by the first and second level shift circuits;
A second step of performing an operation margin inspection by performing a read operation after the first step;
A method of inspecting a semiconductor memory device. 12. A method of inspecting a semiconductor memory device according to claim 11, comprising:
The second precharge circuit is activated by a second activation signal through a second delay circuit, and a power supply voltage is applied to the other bit line of the bit line pair to which the second precharge circuit is connected. , The first precharge circuit is activated by the first activation signal via the first delay circuit, and the rising operation of the first precharge circuit is activated by the first delay circuit. The bit line pair of the bit line pair to which the first precharge circuit is connected is completed earlier than the rise operation of the precharge circuit 2 and the precharge operation is completed in a state where the precharge is insufficient. And a first step of applying a potential lower than the power supply voltage;
A second step of performing an operation margin inspection by performing a read operation after the first step;
A method of inspecting a semiconductor memory device.

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