JP2007201437A5

JP2007201437A5 -

Info

Publication number: JP2007201437A5
Application number: JP2006342689A
Authority: JP
Filing date: 2006-12-20
Publication date: 2010-05-20

Claims

A nonvolatile memory device having a memory element including an electric element, a reset element, and a latch element is mounted, information is stored in the latch element by the reset element, and the electric element is electrically conductive. 2. The semiconductor device according to claim 1, wherein the information stored in the latch element is determined depending on whether insulation is performed.

A nonvolatile memory device having a memory element including a P-type transistor, an electric element, and a latch element;
A gate of the P-type transistor is electrically connected to a reset terminal;
A source of the P-type transistor is electrically connected to a power supply terminal;
The drain of the P-type transistor is electrically connected to the output terminal and the latch element,
One terminal of the electrical element is electrically connected to a ground terminal, and the other terminal is electrically connected to the output terminal and the latch terminal,
Information is stored in the latch element by electrically conducting the P-type transistor,
With the information stored in the latch element, depending on whether the electric element and the output terminal are electrically connected or insulated by the P-type transistor being electrically insulated. The semiconductor device is characterized in that information output from the output terminal is determined.

A nonvolatile memory device having a memory element including a P-type transistor, an N-type transistor, an electric element, and a latch element;
A gate of the P-type transistor and a gate of the N-type transistor are electrically connected to a reset terminal;
A source of the P-type transistor is electrically connected to a power supply terminal;
The drain of the P-type transistor is electrically connected to one terminal of the electrical element,
A source of the N-type transistor is electrically connected to a ground terminal;
A drain of the N-type transistor is electrically connected to the other terminal of the electric element;
One terminal or the other terminal of the electrical element is electrically connected to the latch element and the output terminal,
When one of the P-type transistor and the N-type transistor is electrically conducted, information is stored in the latch element,
In a state where the information is stored in the latch element, one of the P-type transistor and the N-type transistor is electrically insulated, so that the electrical element and the output terminal are electrically connected, or Information output from the output terminal is determined depending on whether it is insulated.

In any one of claims 1 to 3, wherein the electrical element is a semiconductor device characterized in that it is electrically insulated by being cut by laser writing.

In any one of claims 1 to 3, wherein the electrical element is a semiconductor device characterized in that it is electrically insulated by destroying applying the overcurrent.

In any one of claims 1 to 3, wherein the electrical element includes a first diode, and a second diode, an overcurrent is applied to at least one of said first diode and said second diode A semiconductor device which is electrically connected by being destroyed.

In any one of claims 1 to 3, wherein the electrical element is a semiconductor device which is a phase change memory device electrical resistance value is changed by a phase change.

In any one of claims 1 to 3, wherein the electrical element is a semiconductor device which is a nonvolatile memory transistor having a floating gate.

In any one of claims 1 to 3, wherein the electrical element is a semiconductor device which is a memory transistor having a MONOS structure.

A non-volatile storage device having a storage element including an electrical resistance, a reset element electrically connected to the electrical resistance, and a latch element electrically connected to the reset element and the electrical resistance;
Information is stored in the latch element by the reset element,
The information is determined depending on whether the electrical resistance is electrically conducting or insulating,
The semiconductor device is characterized in that the electrical resistance is electrically insulated by being cut by laser drawing.

A non-volatile memory device having a memory element including an electrical resistance, a reset element, and a latch element;
A first terminal of the reset element is electrically connected to the first wiring;
A first terminal of the electrical resistance is electrically connected to the second wiring;
A second terminal of the reset element is electrically connected to the second terminal of the electrical resistance and a third wiring;
A first terminal and a second terminal of the latch element are electrically connected to the third wiring;
The semiconductor device is characterized in that the electrical resistance is electrically insulated by being cut by laser drawing.

A non-volatile memory device having a memory element including a first diode, a second diode, a reset element, and a latch element;
A terminal of the reset element is electrically connected to the first wiring;
A first terminal and a second terminal of the latch element are electrically connected to the first wiring;
The second diode is electrically connected to the first wiring through the first diode,
At least one of the first diode and the second diode is electrically connected when an overcurrent is applied thereto.

A first diode, a second diode electrically connected to the first diode, a reset element electrically connected to the first diode and the second diode, the reset element, A non-volatile memory device having a memory element including a latch element electrically connected to the first diode and the second diode;
Information is stored in the latch element by the reset element,
The information is determined depending on whether at least one of the first diode and the second diode is electrically conductive or insulated,
At least one of the first diode and the second diode is electrically connected when an overcurrent is applied thereto.

In any one of claims 1, 10 to 13, wherein the reset element, wherein a thin film transistor is used for the semiconductor thin film formed on a substrate an active layer having an insulating surface.

15. The semiconductor device according to claim 1, wherein the latch element is a thin film transistor having a semiconductor thin film formed over a substrate having an insulating surface as an active layer.

16. The semiconductor device according to claim 14, wherein the substrate having an insulating surface is a glass substrate, a quartz substrate, a plastic substrate, or an SOI substrate.

17. The semiconductor device according to claim 1, wherein the latch element includes a first inverter and a second inverter.