JP2007242995A - Multilayer ceramic electronic component and manufacturing method thereof - Google Patents

Multilayer ceramic electronic component and manufacturing method thereof Download PDF

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JP2007242995A
JP2007242995A JP2006065383A JP2006065383A JP2007242995A JP 2007242995 A JP2007242995 A JP 2007242995A JP 2006065383 A JP2006065383 A JP 2006065383A JP 2006065383 A JP2006065383 A JP 2006065383A JP 2007242995 A JP2007242995 A JP 2007242995A
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layer
ceramic element
electronic component
plating
glass
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Atsushi Kanazawa
篤志 金澤
Yoshimasa Kanazawa
賢昌 金沢
Tsutomu Onuma
力 大沼
Keiji Kawajiri
圭嗣 川尻
Tomohisa Okimoto
知久 沖本
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Abstract

【課題】本発明はメッキ流れによる両端の外部電極間短絡を防止することを目的とするものである。
【解決手段】この目的を達成するために、本発明は内部電極層1を有するセラミック素子3と、このセラミック素子3の外部に設けられ、かつ前記内部電極層1に電気的に接続された外部電極4とを備え、前記セラミック素子3の外表面の内、少なくとも外部電極4部分以外の表面をガラス層5で覆うとともに、このガラス層5上の少なくとも一部分を酸化物層6、または絶縁物層で覆い、かつ前記外部電極4は、メッキ層を有する構成とした。
【選択図】図1
An object of the present invention is to prevent a short circuit between external electrodes at both ends due to a plating flow.
To achieve this object, the present invention provides a ceramic element 3 having an internal electrode layer 1 and an external element provided outside the ceramic element 3 and electrically connected to the internal electrode layer 1. An electrode 4, and at least a portion of the outer surface of the ceramic element 3 other than the portion of the external electrode 4 is covered with a glass layer 5, and at least a part of the glass layer 5 is covered with an oxide layer 6 or an insulating layer. And the external electrode 4 has a plating layer.
[Selection] Figure 1

Description

本発明は、例えばセラミックコンデンサや積層バリスター等の積層セラミック電子部品とその製造方法に関するものである。   The present invention relates to a multilayer ceramic electronic component such as a ceramic capacitor or a multilayer varistor and a method for manufacturing the same.

例えばセラミックコンデンサは、内部電極層を有するセラミック素子と、このセラミック素子の外部に設けられ、かつ前記内部電極層に電気的に接続された外部電極とを備えた構造になっており、前記セラミック素子の外表面のうち、少なくとも外部電極部分以外の表面は、電界メッキを施す際、または腐食雰囲気中での保護を目的として、ガラス層で覆っている。   For example, a ceramic capacitor has a structure including a ceramic element having an internal electrode layer and an external electrode provided outside the ceramic element and electrically connected to the internal electrode layer. Of these outer surfaces, at least the surface other than the external electrode portion is covered with a glass layer for the purpose of electroplating or protection in a corrosive atmosphere.

なお、このような従来の技術に対応する先行文献としては、下記特許文献1が存在する。
特開2000−164406号公報
In addition, the following patent document 1 exists as a prior art document corresponding to such a conventional technique.
JP 2000-164406 A

上述のごとくセラミック素子の外表面の内、少なくとも外部電極部分以外の表面をガラス層で覆えば、このガラス層により電界メッキを施す際、または腐食雰囲気中でのセラミック素子の保護を行うことはできるが、メッキにより前記内部電極層に電気的に接続された外部電極をセラミック素子の両端に形成する時に、これら両端の外部電極間のガラス層にもメッキ層が形成されてしまい(いわゆるメッキ流れ)、これによって両端の外部電極間が短絡されてしまうという問題が発生することがある。   As described above, if at least the surface of the ceramic element other than the external electrode portion is covered with a glass layer, the ceramic element can be protected when electroplating with this glass layer or in a corrosive atmosphere. However, when external electrodes electrically connected to the internal electrode layer by plating are formed at both ends of the ceramic element, a plating layer is also formed on the glass layer between the external electrodes at both ends (so-called plating flow). This may cause a problem that the external electrodes at both ends are short-circuited.

その理由は種々考えられるが、セラミック素子の外表面を覆うガラス層は熱膨張係数の関係であまり肉厚にすることができず、その結果ガラス層上には下面のセラミック素子の表面凸凹形状が略転写され、これによりガラス層上に形成された突出部がメッキの核となり、上述のごとく両端の外部電極間のガラス層にもメッキ層が形成されてしまい(いわゆるメッキ流れ)、これによって両端の外部電極間が短絡されてしまうという問題が発生することがあげられる。   There are various reasons for this, but the glass layer covering the outer surface of the ceramic element cannot be made too thick due to the coefficient of thermal expansion. As a result, the surface irregularity of the ceramic element on the lower surface is formed on the glass layer. The protrusions formed on the glass layer are substantially transferred, thereby forming the core of the plating, and as described above, a plating layer is also formed on the glass layer between the external electrodes at both ends (so-called plating flow). The problem that a short circuit occurs between the external electrodes is caused.

そこで本発明はいわゆるメッキ流れによる両端の外部電極間短絡を防止することを目的とするものである。   Therefore, the present invention aims to prevent a short circuit between external electrodes at both ends due to a so-called plating flow.

そしてこの目的を達成するために、本発明は、内部電極層を有するセラミック素子と、このセラミック素子の外部に設けられ、かつ前記内部電極層に電気的に接続された外部電極とを備え、前記セラミック素子の外表面の内、少なくとも外部電極部分以外の表面をガラス層で覆うとともに、このガラス層上の少なくとも一部分を酸化物層、または絶縁物層で覆い、かつ前記外部電極は、メッキ層を有する構成としたものである。   In order to achieve this object, the present invention comprises a ceramic element having an internal electrode layer, and an external electrode provided outside the ceramic element and electrically connected to the internal electrode layer, Of the outer surface of the ceramic element, at least a surface other than the external electrode portion is covered with a glass layer, and at least a part of the glass layer is covered with an oxide layer or an insulating layer, and the external electrode includes a plating layer. It is set as the structure which has.

以上のように本発明は、セラミック素子の外表面の内、少なくとも外部電極部分以外の表面をガラス層で覆うとともに、このガラス層上の少なくとも一部分を酸化物層、または絶縁物層で覆ったものであるので、ガラス層上に転写された凹凸を小さくし、メッキの核となる突出部を実質的に無くすことができるので、いわゆるメッキ流れによる両端の外部電極間短絡を防止することができる。   As described above, according to the present invention, at least a part of the outer surface of the ceramic element other than the external electrode portion is covered with the glass layer, and at least a part of the glass layer is covered with the oxide layer or the insulating layer. Therefore, the projections and depressions transferred onto the glass layer can be reduced and the protrusions that become the core of the plating can be substantially eliminated, so that a short circuit between the external electrodes at both ends due to the so-called plating flow can be prevented.

(実施の形態1)
以下、本発明の一実施の形態を、積層セラミック電子部品の一例として、積層バリスターに適用したものを、添付図面を用いて説明する。
(Embodiment 1)
Hereinafter, an embodiment in which an embodiment of the present invention is applied to a multilayer varistor as an example of a multilayer ceramic electronic component will be described with reference to the accompanying drawings.

図1に示すごとく本実施形態の積層バリスターは、Pdよりなる内部電極層1とバリスター層2を有するセラミック素子3と、このセラミック素子3の外部に設けられ、かつ前記内部電極層1に電気的に接続された外部電極4とを備えている。   As shown in FIG. 1, the laminated varistor of this embodiment includes a ceramic element 3 having an internal electrode layer 1 made of Pd and a varistor layer 2, and is provided outside the ceramic element 3. An external electrode 4 that is electrically connected is provided.

前記セラミック素子3の外表面はガラス層5で覆われ、さらにこのガラス層5の外表面は酸化物層6で覆われている。酸化物層6は本実施形態ではZnOを主成分とするもので形成され、これは後で詳述するが、バリスター層2をZnOを主成分とし、これにCoやCr等を微量添加して形成したことに起因している。   The outer surface of the ceramic element 3 is covered with a glass layer 5, and the outer surface of the glass layer 5 is covered with an oxide layer 6. In this embodiment, the oxide layer 6 is formed of ZnO as a main component, which will be described in detail later. The varistor layer 2 is mainly composed of ZnO, and a small amount of Co, Cr, or the like is added thereto. This is due to the formation.

さて上記内部電極層1はこれらのガラス層5と酸化物層6を貫通し、外部電極4に電気的に接続されているのであるが、一方外部電極4は下面の塗布によるAg層7とその上面にメッキにより形成したNi層8、その上面にメッキにより形成したSn層9から形成されている。   The internal electrode layer 1 penetrates the glass layer 5 and the oxide layer 6 and is electrically connected to the external electrode 4, while the external electrode 4 is composed of an Ag layer 7 and its An Ni layer 8 is formed on the upper surface by plating, and an Sn layer 9 is formed on the upper surface by plating.

図2はセラミック素子3の外表面の一部分を拡大したもので、上述のごとくセラミック素子3の外表面はガラス層5で覆われ、さらにこのガラス層5の外表面は酸化物層6で覆われている。この内ガラス層5は酸化ケイ素系のガラス層となっており、このガラス層5は熱膨張係数の関係であまり肉厚にすることができず、その結果ガラス層5上には下面のセラミック素子3の表面凸凹形状が略転写され、これによりガラス層5上に突出部が形成されている。   FIG. 2 is an enlarged view of a part of the outer surface of the ceramic element 3. As described above, the outer surface of the ceramic element 3 is covered with the glass layer 5, and the outer surface of the glass layer 5 is covered with the oxide layer 6. ing. The inner glass layer 5 is a silicon oxide-based glass layer, and the glass layer 5 cannot be made too thick due to the coefficient of thermal expansion. As a result, the lower ceramic element is formed on the glass layer 5. The surface unevenness shape 3 is substantially transferred, whereby a protrusion is formed on the glass layer 5.

しかしながら本実施形態ではこのガラス層5上に酸化物層6が形成され、この酸化物層6はガラス層5(0.1ミクロン)よりも遥かに肉厚の0.3〜0.5ミクロンとしているので、後の製造方法中で詳述するが、酸化物層6上には、もはやメッキの核となる突出部を実質的に無くすことができ、いわゆるメッキ流れによる両端の外部電極4間短絡を防止することができる。   However, in this embodiment, an oxide layer 6 is formed on the glass layer 5, and the oxide layer 6 is 0.3 to 0.5 μm thicker than the glass layer 5 (0.1 μm). Therefore, as will be described in detail later in the manufacturing method, it is possible to substantially eliminate protrusions that become the core of plating on the oxide layer 6, and short-circuit between the external electrodes 4 at both ends due to so-called plating flow. Can be prevented.

図3は製造方法を示すもので、先ずZnOを主成分とし、これにCoやCr等を微量添加したバリスター材料を作製する(A)。   FIG. 3 shows a manufacturing method. First, a varistor material containing ZnO as a main component and adding a small amount of Co, Cr or the like to this is prepared (A).

次にこのバリスター材料に有機バインダーや可塑剤を混入した状態でスラリー化を行う(B)。   Next, the varistor material is slurried with an organic binder and a plasticizer mixed therein (B).

その後このスラリーを用いてグリーンシートを作製し(C)、このグリーンシート上に図1の内部電極層1を印刷形成する。   Thereafter, a green sheet is prepared using this slurry (C), and the internal electrode layer 1 of FIG. 1 is printed on the green sheet.

次に内部電極層1付きのグリーンシートを積層し(D)、その後個片に分断後、成形体の面取り(E)をして成形体の両端に内部電極層1を露出させ、次に脱脂、焼成し(F)、その後外表面に樹脂を含浸し(G)、次にこの状態のセラミック素子3を、パーヒドロポリシラザンを主成分としたガラスコーティング溶液(AZエレクトリックマテリアス株式会社製)中に浸漬(H)し、その後ガラスコーティング溶液からセラミック素子3を引き上げ、450度で熱処理する。   Next, the green sheet with the internal electrode layer 1 is laminated (D), then cut into individual pieces, the molded body is chamfered (E) to expose the internal electrode layer 1 at both ends of the molded body, and then degreased. Baked (F), and then impregnated with resin on the outer surface (G), and then the ceramic element 3 in this state is in a glass coating solution (manufactured by AZ Electric Materias Co., Ltd.) mainly composed of perhydropolysilazane. Then, the ceramic element 3 is pulled up from the glass coating solution and heat treated at 450 degrees.

この結果セラミック素子3の外表面は図1、図2のごとくガラス層5で覆われ、さらにこのガラス層5の外表面は酸化物層6で覆われている。このうちガラス層5は酸化ケイ素を主成分として形成されたもので、また酸化物層6は本実施形態ではZnOを主成分とするもので形成されている。   As a result, the outer surface of the ceramic element 3 is covered with the glass layer 5 as shown in FIGS. 1 and 2, and the outer surface of the glass layer 5 is covered with the oxide layer 6. Among these, the glass layer 5 is formed with silicon oxide as a main component, and the oxide layer 6 is formed with ZnO as a main component in this embodiment.

これは、バリスター層2がZnOを主成分とし、これにCoやCr等を微量添加して形成したものであり、これを上述のガラスコーティング溶液に浸漬した場合ZnO成分の一部が溶出し、その状態でガラスコーティング溶液から引き上げ、450度で熱処理すると、セラミック素子3の外表面は図1、図2のごとくガラス層5で覆われ、さらにこのガラス層5の外表面は酸化物層6で覆われた状態となる。   This is because the varistor layer 2 is formed by adding ZnO as a main component to the varistor layer 2 and adding a small amount of Co or Cr to the varistor layer 2. When this is immersed in the glass coating solution, a part of the ZnO component is eluted. In this state, when the glass coating solution is pulled up and heat-treated at 450 ° C., the outer surface of the ceramic element 3 is covered with the glass layer 5 as shown in FIGS. 1 and 2, and the outer surface of the glass layer 5 is covered with the oxide layer 6. It becomes the state covered with.

そしてこのようにして本実施形態では、このガラス層5上に酸化物層6が形成され、この酸化物層6はガラス層5(0.1ミクロン)よりも遥かに肉厚の0.3〜0.5ミクロンとなっているので、酸化物層6上には、もはやメッキの核となる突出部を実質的に無くすことができ、いわゆるメッキ流れによる両端の外部電極4間短絡を防止することができる。   In this way, in this embodiment, the oxide layer 6 is formed on the glass layer 5, and this oxide layer 6 has a thickness of 0.3 to 0.3 which is much thicker than the glass layer 5 (0.1 micron). Since the thickness is 0.5 microns, it is possible to substantially eliminate protrusions that are the cores of plating on the oxide layer 6, and prevent short circuit between the external electrodes 4 at both ends due to so-called plating flow. Can do.

つまりその後外部電極4として、まず塗布によりAg層7が形成され(I)、その後図4のメッキ装置を用いて、Ni層8とSn層9がメッキ形成される(J)。   That is, the Ag layer 7 is first formed as the external electrode 4 by coating (I), and then the Ni layer 8 and the Sn layer 9 are plated using the plating apparatus shown in FIG. 4 (J).

図4に示すメッキ装置は、容器10中にメッキ液11とメッキ容器12を入れ、メッキ容器12中に図3の(I工程)後のセラミック素子3とスチールボール13を多数入れ、メッキ容器12を回転させながら電源14から陽極15にプラス、メッキ容器12にマイナスを印加してNi層8とSn層9を順番にメッキ形成する。   In the plating apparatus shown in FIG. 4, a plating solution 11 and a plating container 12 are placed in a container 10, and a large number of ceramic elements 3 and steel balls 13 (step I) in FIG. 3 are placed in the plating container 12. The Ni layer 8 and the Sn layer 9 are plated in order by applying a plus to the anode 15 from the power source 14 and a minus to the plating container 12 while rotating.

このメッキ時、本実施形態では、このガラス層5上に酸化物層6が形成され、この酸化物層6はガラス層5(0.1ミクロン)よりも遥かに肉厚の0.3〜0.5ミクロンとなっているので、酸化物層6上には、もはやメッキの核となる突出部を実質的に無くすことができ、この結果としていわゆるメッキ流れによる両端の外部電極4間短絡を防止することができる。   At the time of plating, in this embodiment, an oxide layer 6 is formed on the glass layer 5, and the oxide layer 6 is 0.3 to 0 which is much thicker than the glass layer 5 (0.1 micron). Since the thickness is .5 microns, it is possible to substantially eliminate the protrusions that become the core of the plating on the oxide layer 6, and as a result, a short circuit between the external electrodes 4 at both ends due to the so-called plating flow is prevented. can do.

なお、本実施形態では、このガラス層5上に酸化物層6を形成したものを説明したが、この酸化物層6に代えて絶縁物層を設け、メッキの核となる突出部を実質的に無くし、いわゆるメッキ流れによる両端の外部電極4間短絡を防止するようにしても良い。   In the present embodiment, the oxide layer 6 formed on the glass layer 5 has been described. However, an insulating layer is provided in place of the oxide layer 6 so that the protrusions serving as the core of plating are substantially formed. Alternatively, a short circuit between the external electrodes 4 at both ends due to a so-called plating flow may be prevented.

以上のように本発明はセラミック素子の外表面の内、少なくとも外部電極部分以外の表面をガラス層で覆うとともに、このガラス層上の少なくとも一部分を酸化物層、または絶縁物層で覆ったものであるので、ガラス層上に転写された凹凸を小さくし、メッキの核となる突出部を実質的に無くすことができるので、いわゆるメッキ流れによる両端の外部電極間短絡を防止することができ、各種積層セラミック部品に広く適用することができるものである。   As described above, the present invention is such that at least a part of the outer surface of the ceramic element other than the external electrode portion is covered with a glass layer, and at least a part of the glass layer is covered with an oxide layer or an insulating layer. Since there are so small irregularities transferred onto the glass layer and the protrusions that become the core of plating can be substantially eliminated, it is possible to prevent short-circuiting between external electrodes at both ends due to so-called plating flow. It can be widely applied to multilayer ceramic parts.

本発明の一実施の形態における断面図Sectional drawing in one embodiment of this invention 本発明の一実施の形態の一部拡大断面図Partially enlarged sectional view of an embodiment of the present invention 本発明の一実施の形態の製造工程を示す図The figure which shows the manufacturing process of one embodiment of this invention 本発明の一実施の形態の製造工程を示す断面図Sectional drawing which shows the manufacturing process of one embodiment of this invention

符号の説明Explanation of symbols

1 内部電極層
2 バリスター層
3 セラミック素子
4 外部電極
5 ガラス層
6 酸化物層
7 Ag層
8 Ni層
DESCRIPTION OF SYMBOLS 1 Internal electrode layer 2 Varistor layer 3 Ceramic element 4 External electrode 5 Glass layer 6 Oxide layer 7 Ag layer 8 Ni layer

Claims (7)

内部電極層を有するセラミック素子と、このセラミック素子の外部に設けられ、かつ前記内部電極層に電気的に接続された外部電極とを備え、前記セラミック素子の外表面の内、少なくとも外部電極部分以外の表面をガラス層で覆うとともに、このガラス層上の少なくとも一部分を酸化物層、または絶縁物層で覆い、かつ前記外部電極は、メッキ層を有する積層セラミック電子部品。 A ceramic element having an internal electrode layer; and an external electrode provided outside the ceramic element and electrically connected to the internal electrode layer, the outer surface of the ceramic element other than at least the external electrode portion A multilayer ceramic electronic component in which at least a part of the glass layer is covered with an oxide layer or an insulating layer, and the external electrode has a plating layer. 酸化物層、または絶縁物層は、ガラス層よりも肉厚とした請求項1に記載の積層セラミック電子部品。 The multilayer ceramic electronic component according to claim 1, wherein the oxide layer or the insulator layer is thicker than the glass layer. 酸化物層、または絶縁物層はセラミック素子の主要成分と同じものとした請求項1、または2に記載の積層セラミック電子部品。 The multilayer ceramic electronic component according to claim 1, wherein the oxide layer or the insulating layer is the same as a main component of the ceramic element. 酸化物層、または絶縁物層と、セラミック素子とは、酸化亜鉛を主成分として形成された請求項1〜3のいずれか一つに記載の積層セラミック電子部品。 The multilayer ceramic electronic component according to claim 1, wherein the oxide layer or the insulator layer and the ceramic element are formed mainly of zinc oxide. 内部電極層を有する焼結済みのセラミック素子をガラスコーティング溶液中に浸漬し、次にガラスコーティング溶液中から取り出したセラミック素子を熱処理してこのセラミック素子の外表面をガラス層で覆うとともに、このガラス層上の少なくとも一部分を酸化物層、または絶縁物層で覆い、その後メッキにより前記内部電極層に電気的に接続された外部電極を形成する積層セラミック電子部品の製造方法。 A sintered ceramic element having an internal electrode layer is immersed in a glass coating solution, and then the ceramic element taken out of the glass coating solution is heat-treated to cover the outer surface of the ceramic element with a glass layer. A method for producing a laminated ceramic electronic component, wherein at least a part of a layer is covered with an oxide layer or an insulating layer, and thereafter an external electrode electrically connected to the internal electrode layer is formed by plating. 外部電極は銀電極層上にメッキ層を設けて形成した請求項5に記載の積層セラミック電子部品の製造方法。 The method for manufacturing a multilayer ceramic electronic component according to claim 5, wherein the external electrode is formed by providing a plating layer on the silver electrode layer. セラミック素子は酸化亜鉛を主成分として形成し、ガラスコーティング溶液はパーヒドロポリシラザンを主成分とした請求項5または6に記載の積層セラミック電子部品の製造方法。 The method for producing a multilayer ceramic electronic component according to claim 5 or 6, wherein the ceramic element is formed mainly of zinc oxide, and the glass coating solution is mainly composed of perhydropolysilazane.
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