JP2009076784A5 - - Google Patents

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Publication number
JP2009076784A5
JP2009076784A5 JP2007246069A JP2007246069A JP2009076784A5 JP 2009076784 A5 JP2009076784 A5 JP 2009076784A5 JP 2007246069 A JP2007246069 A JP 2007246069A JP 2007246069 A JP2007246069 A JP 2007246069A JP 2009076784 A5 JP2009076784 A5 JP 2009076784A5
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JP
Japan
Prior art keywords
semiconductor wafer
substrate
semiconductor
layer
insulating layer
Prior art date
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Application number
JP2007246069A
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English (en)
Japanese (ja)
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JP2009076784A (ja
JP5252867B2 (ja
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Priority to JP2007246069A priority Critical patent/JP5252867B2/ja
Priority claimed from JP2007246069A external-priority patent/JP5252867B2/ja
Publication of JP2009076784A publication Critical patent/JP2009076784A/ja
Publication of JP2009076784A5 publication Critical patent/JP2009076784A5/ja
Application granted granted Critical
Publication of JP5252867B2 publication Critical patent/JP5252867B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2007246069A 2007-09-21 2007-09-21 半導体基板の製造方法 Expired - Fee Related JP5252867B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007246069A JP5252867B2 (ja) 2007-09-21 2007-09-21 半導体基板の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007246069A JP5252867B2 (ja) 2007-09-21 2007-09-21 半導体基板の製造方法

Publications (3)

Publication Number Publication Date
JP2009076784A JP2009076784A (ja) 2009-04-09
JP2009076784A5 true JP2009076784A5 (de) 2010-10-21
JP5252867B2 JP5252867B2 (ja) 2013-07-31

Family

ID=40611456

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007246069A Expired - Fee Related JP5252867B2 (ja) 2007-09-21 2007-09-21 半導体基板の製造方法

Country Status (1)

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JP (1) JP5252867B2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8318588B2 (en) * 2009-08-25 2012-11-27 Semiconductor Energy Laboratory Co., Ltd. Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate
US8735263B2 (en) * 2011-01-21 2014-05-27 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
JP6579086B2 (ja) * 2016-11-15 2019-09-25 信越半導体株式会社 デバイス形成方法
JP6686962B2 (ja) * 2017-04-25 2020-04-22 信越半導体株式会社 貼り合わせウェーハの製造方法
CN112599655A (zh) * 2019-03-13 2021-04-02 电子科技大学 多功能单晶薄膜、其制备方法和谐振器

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000150835A (ja) * 1998-11-05 2000-05-30 Fujitsu Ltd 非単結晶シリコン薄膜の製造方法
FR2877491B1 (fr) * 2004-10-29 2007-01-19 Soitec Silicon On Insulator Structure composite a forte dissipation thermique
KR20080042095A (ko) * 2005-07-27 2008-05-14 실리콘 제너시스 코포레이션 제어된 클리빙 처리를 이용하여 플레이트 상에 다수의 타일영역을 제작하는 방법 및 구조

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