JP2014123782A5

JP2014123782A5 -

Info

Publication number: JP2014123782A5
Application number: JP2014069932A
Authority: JP
Filing date: 2014-03-28
Publication date: 2014-10-16
Anticipated expiration: 2018-06-18

Description

以上説明してきたように、本発明に係る半導体記憶装置によれば、異なる導電型の能動領域をチャネル電流方向が平行となるように配置し、かつチャネル電流方向と直交する方向の隣接セル間で分離されている。また、当該能動領域にゲート電極パターンを全て直交させている。これにより、ゲート電極パターンのアライメントずれによってセル内のトランジスタサイズが殆ど変化しない、或いは変化しても一律に変化させることができる。これは、本発明をＳＲＡＭセルに適用した場合、そのインバータ特性が変化しないためデータ保持特性等のメモリセル特性について期待した特性が得られ、またメモリセルアレイ内、或いはチップ間で特性バラツキが低減される。
この平行配置された能動領域およびゲート電極のパターン形成時に位相シフト法の適用が容易化され、この超高解像度パターン形成技術によって、高集積、大容量の半導体記憶装置が実現できる。 As described above, according to the semiconductor memory device of the present invention, active regions of different conductivity types are arranged so that channel current directions are parallel, and between adjacent cells in a direction orthogonal to the channel current direction. It is separated. In addition, all the gate electrode patterns are orthogonal to the active region. As a result, the transistor size in the cell hardly changes due to misalignment of the gate electrode pattern, or can be changed uniformly even if it changes. This is because when the present invention is applied to an SRAM cell, the inverter characteristics do not change, so that expected characteristics of memory cell characteristics such as data retention characteristics can be obtained, and characteristic variations within the memory cell array or between chips are reduced. The
Application of the phase shift method is facilitated when forming the pattern of the active region and the gate electrode arranged in parallel, and a highly integrated and large capacity semiconductor memory device can be realized by this ultra-high resolution pattern forming technique.

本発明の特徴および適用可能なＳＲＡＭセルタイプは、大まかには、以下の点に集約できる。
特徴１：ｐ型能動領域とｎ型能動領域を、それぞれに形成されるトランジスタのチャネル電流方向が平行となるように配置し、かつ、それぞれがチャネル電流方向と直交する方向の隣接セル間で分離する（タイプＣ）。
特徴２：電源電圧供給線を、層間絶縁層の貫通溝を導電材料で埋め込んだ溝配線とする（タイプＡ〜Ｃ）。
特徴３：電源電圧供給線へのコンタクト構造を２層コンタクトを用いて形成する（タイプＡ〜Ｃ）。
特徴４：ビット線接続配線層を溝配線により形成する（タイプＣ）。
特徴５：電源電圧供給線の一方を溝配線とした場合、他方を上層メタル配線とし、かつ、配線方向と直交する２セル間で連結したパターンとする（好適にはタイプＣ、タイプＡとＢも適用可）。
特徴６：２つの記憶ノード配線層の形成膜を２層とし、その上層側のエッチング保護膜を一方の配線層パターンにて形成しておき、他方の配線層パターンにて下層の導電膜をパターンニングする際に、エッチング保護層をエッチングマスクとして機能させて２つの記憶ノード配線層を同時形成する（好適にはタイプＣ、タイプＡとＢも適用可）。 The features of the present invention and applicable SRAM cell types can be roughly summarized as follows.
Feature 1: The p-type active region and the n-type active region are arranged so that the channel current directions of the transistors formed in parallel are parallel to each other, and are separated between adjacent cells in the direction perpendicular to the channel current direction. (Type C)
Feature 2: The power supply voltage supply line is a groove wiring in which the through groove of the interlayer insulating layer is buried with a conductive material (types A to C).
Feature 3: A contact structure to the power supply voltage supply line is formed using a two-layer contact (types A to C).
Feature 4: The bit line connection wiring layer is formed by groove wiring (type C).
Feature 5: When one of the power supply voltage supply lines is a groove wiring, the other is an upper metal wiring and a pattern connected between two cells orthogonal to the wiring direction (preferably type C, type A and B) Is also applicable).
Feature 6: Two storage node wiring layers are formed in two layers, an upper layer side etching protection film is formed by one wiring layer pattern, and a lower layer conductive film is patterned by the other wiring layer pattern. When performing the etching, the etching protection layer functions as an etching mask to simultaneously form two storage node wiring layers (preferably type C, type A and B are also applicable).

Claims

Two inverters each composed of an n-type drive transistor and a p-type load transistor connected in series with each other and having their gates connected in common, the input and the output of which are cross-connected, An n-type first access transistor connected to a common node between one input and the other output of two inverters, and n connected to a common node between one output and the other input of the two inverters A plurality of memory cells each including a second access transistor of the type,
In each memory cell
All of the active regions in which each of the transistors is formed are arranged such that the channel current directions of all the transistors included in the memory cell are parallel to each other in the memory cell, and the channel current direction Each is separated between adjacent memory cells in the orthogonal direction,
The gate is shared by the drive transistor and the load transistor constituting each inverter, and an active region in which the drive transistor constituting each inverter is formed and an active region in which the load transistor constituting each inverter is formed It is a linear common gate line that intersects each region,
The drive transistor constituting each inverter and the first or second access transistor connected to the drive transistor are formed in an active region between the gate of the drive transistor and the gate of the access transistor. Connected by a type impurity region,
N formed in an active region between the gate of the driving transistor and the gate of the access transistor among n-type impurity regions adjacent to the common gate line and formed in the active region where the driving transistor is formed. A common potential line is connected to the n-type impurity region opposite to the common impurity line and the common gate line by an electrical connection line, and the electrical connection line includes one or both of a wiring and a plug, The electrical connection line has a single-layer or multi-layer structure,
N formed in an active region between the gate of the driving transistor and the gate of the access transistor, among p-type impurity regions adjacent to the common gate line, formed in the active region where the load transistor is formed. A power supply line is connected to the p-type impurity region opposite to the common gate line and the p-type impurity region by an electrical connection line, and the electrical connection line includes one or both of a wiring and a plug, The electrical connection line has a single-layer or multi-layer structure,
At least one part of the structure including the common potential line and the electrical connection line connected to the common potential line, and at least one of the structure including the power connection line and the electrical connection line connected to the power supply line. Any one or both of the portion is made of a trench wiring formed in the interlayer insulating film,
At least one of the common potential line and the power supply line extends to pass through the memory cell in the channel current direction.
Semiconductor memory device.

The trench wiring formed in the interlayer insulating film includes a trench wiring extending in the channel current direction,
The semiconductor memory device according to claim 1.

The trench wiring formed in the interlayer insulating film includes a trench wiring extending in a direction orthogonal to the channel current direction.
The semiconductor memory device according to claim 1.

The common potential line extends through the memory cell in the channel current direction;
The semiconductor memory device according to claim 1.

The power line extends through the memory cell in the channel current direction.
The semiconductor memory device according to claim 1.

Two inverters each composed of an n-type drive transistor and a p-type load transistor connected in series with each other and having their gates connected in common, the input and the output of which are cross-connected, An n-type first access transistor connected to a common node between one input and the other output of two inverters, and n connected to a common node between one output and the other input of the two inverters A plurality of memory cells each including a second access transistor of the type,
In each memory cell
All of the active regions in which each of the transistors is formed are arranged such that the channel current directions of all the transistors included in the memory cell are parallel to each other in the memory cell, and the channel current direction Each is separated between adjacent memory cells in the orthogonal direction,
The gate is shared by the drive transistor and the load transistor constituting each inverter, and an active region in which the drive transistor constituting each inverter is formed and an active region in which the load transistor constituting each inverter is formed It is a linear common gate line that intersects each region,
The drive transistor constituting each inverter and the first or second access transistor connected to the drive transistor are formed in an active region between the gate of the drive transistor and the gate of the access transistor. Connected by a type impurity region,
N formed in an active region between the gate of the driving transistor and the gate of the access transistor among n-type impurity regions adjacent to the common gate line and formed in the active region where the driving transistor is formed. A common potential line is connected to the n-type impurity region opposite to the common impurity line and the common gate line by an electrical connection line, and the electrical connection line includes one or both of a wiring and a plug, The electrical connection line has a single-layer or multi-layer structure,
N formed in an active region between the gate of the driving transistor and the gate of the access transistor, among p-type impurity regions adjacent to the common gate line, formed in the active region where the load transistor is formed. A power supply line is connected to the p-type impurity region opposite to the common gate line and the p-type impurity region by an electrical connection line, and the electrical connection line includes one or both of a wiring and a plug, The electrical connection line has a single-layer or multi-layer structure,
At least one part of the structure including the common potential line and the electrical connection line connected to the common potential line, and at least one of the structure including the power connection line and the electrical connection line connected to the power supply line. Any one or both of the portion is made of a trench wiring formed in the interlayer insulating film,
At least one of the common potential line and the power supply line extends so as to pass through the memory cell in a direction orthogonal to the channel current direction.
Semiconductor memory device.

The trench wiring formed in the interlayer insulating film includes a trench wiring extending in the channel current direction,
The semiconductor memory device according to claim 6.

The trench wiring formed in the interlayer insulating film includes a trench wiring extending in a direction orthogonal to the channel current direction.
The semiconductor memory device according to claim 6.

The common potential line extends through the memory cell in a direction orthogonal to the channel current direction.
The semiconductor memory device according to claim 6.

The power line extends so as to pass through the memory cell in a direction orthogonal to the channel current direction.
The semiconductor memory device according to claim 6.

Two inverters each composed of an n-type drive transistor and a p-type load transistor connected in series with each other and having their gates connected in common, the input and the output of which are cross-connected, An n-type first access transistor connected to a common node between one input and the other output of two inverters, and n connected to a common node between one output and the other input of the two inverters A plurality of memory cells each including a second access transistor of the type,
In each memory cell
All of the active regions in which each of the transistors is formed are arranged such that the channel current directions of all the transistors included in the memory cell are parallel to each other in the memory cell, and the channel current direction Each is separated between adjacent memory cells in the orthogonal direction,
The gate is shared by the drive transistor and the load transistor constituting each inverter, and an active region in which the drive transistor constituting each inverter is formed and an active region in which the load transistor constituting each inverter is formed It is a linear common gate line that intersects each region,
The drive transistor constituting each inverter and the first or second access transistor connected to the drive transistor are formed in an active region between the gate of the drive transistor and the gate of the access transistor. Connected by a type impurity region,
N formed in an active region between the gate of the driving transistor and the gate of the access transistor among n-type impurity regions adjacent to the common gate line and formed in the active region where the driving transistor is formed. A common potential line is connected to the n-type impurity region opposite to the common impurity line and the common gate line by an electrical connection line, and the electrical connection line includes one or both of a wiring and a plug, The electrical connection line has a single-layer or multi-layer structure,
N formed in an active region between the gate of the driving transistor and the gate of the access transistor, among p-type impurity regions adjacent to the common gate line, formed in the active region where the load transistor is formed. A power supply line is connected to the p-type impurity region opposite to the common gate line and the p-type impurity region by an electrical connection line, and the electrical connection line includes one or both of a wiring and a plug, The electrical connection line has a single-layer or multi-layer structure,
At least one part of the structure including the common potential line and the electrical connection line connected to the common potential line, and at least one of the structure including the power connection line and the electrical connection line connected to the power supply line. Any one or both of the portion is made of a trench wiring formed in the interlayer insulating film,
The power supply line and the structure including the electrical connection line connected to the power supply line with respect to at least a part of the structure including the common potential line and the electrical connection line connected to the common potential line. At least partially orthogonal,
Semiconductor memory device.

The trench wiring formed in the interlayer insulating film includes a trench wiring extending in the channel current direction,
The semiconductor memory device according to claim 11.

The trench wiring formed in the interlayer insulating film includes a trench wiring extending in a direction orthogonal to the channel current direction.
The semiconductor memory device according to claim 11.

At least one of the common potential line and the power supply line extends so as to pass through the memory cell in a direction orthogonal to the channel current direction.
The semiconductor memory device according to claim 11.

The power line extends so as to pass through the memory cell in a direction orthogonal to the channel current direction.
The semiconductor device according to claim 14.

At least one of the common potential line and the power supply line extends so as to pass through the memory cell in the channel current direction.
The semiconductor memory device according to claim 11.

The common potential line extends so as to pass through the memory cell in the channel current direction.
The semiconductor device according to claim 16.

The power supply line is orthogonal to the common potential line;
The semiconductor device according to claim 11.