JP2014142995A5

JP2014142995A5 - Method for reading data from semiconductor device and semiconductor device

Info

Publication number: JP2014142995A5
Application number: JP2014076283A
Authority: JP
Filing date: 2014-04-02
Publication date: 2014-11-13

Description

上記課題を解決するために、本発明は、半導体装置からデータを読み出す方法であって、メモリセルに接続されたビット線を第１の電位にプリチャージし、センスアンプ回路の出力ノードを前記第１の電位より大きい第２の電位にプリチャージし、前記センスアンプ回路のセンス検出トランジスタに接続されたセンスノードを前記第１の電位より大きい第３の電位に駆動し、前記ビット線を前記センスノードに接続する転送トランジスタを活性化し、前記ビット線の電位が前記第１の電位から前記第１の電位より大きくかつ前記第２の電位より小さい第４の電位に駆動され、前記ビット線を用いて前記メモリセルに保持されるデータを読み出し、前記センスアンプ回路の前記センス検出トランジスタを用いて、前記メモリセルから読み出されたデータがハイレベルのデータ又はローレベルのデータに対応するかを判定し、前記読み出したデータがハイレベルのデータであるときは前記出力ノードを前記第１の電位に駆動し、前記読み出したデータがローレベルのデータであるときは前記出力ノードを前記第２の電位に保ち、前記出力ノードに接続された入力を有する書き込み回路を用い、前記入力が前記出力ノードから前記第１の電位を受け取ったときは前記第１の電位より大きくかつ前記第２の電位より小さい第５の電位を供給し、前記入力が前記出力ノードから前記第２の電位を受け取ったときは前記第１の電位を供給することを特徴としている。 In order to solve the above problems, the present invention provides a method for reading data from a semiconductor device, wherein a bit line connected to a memory cell is precharged to a first potential, and an output node of a sense amplifier circuit is connected to the first node. Precharging to a second potential greater than 1 potential, driving a sense node connected to a sense detection transistor of the sense amplifier circuit to a third potential greater than the first potential, and causing the bit line to sense A transfer transistor connected to a node is activated, and the potential of the bit line is driven from the first potential to a fourth potential that is larger than the first potential and smaller than the second potential, and uses the bit line The data held in the memory cell is read out and read from the memory cell using the sense detection transistor of the sense amplifier circuit. It is determined whether the data corresponds to high level data or low level data. When the read data is high level data, the output node is driven to the first potential, and the read data is When the data is low level, the output node is kept at the second potential, a write circuit having an input connected to the output node is used, and the input receives the first potential from the output node. A fifth potential that is greater than the first potential and smaller than the second potential is supplied, and the first potential is supplied when the input receives the second potential from the output node. that it is characterized by.

また、上記課題を解決するために、本発明の半導体装置は、メモリセルと、選択トランジスタにより前記メモリセルに接続されるビット線と、前記ビット線と第１の電位との間に接続される第１のトランジスタと、センスノードと第２の電位との間に接続される第２のトランジスタと、前記ビット線を前記センスノードに接続する第３のトランジスタとを備える電荷転送制御回路と、前記センスノードに接続されるゲートを有する第４のトランジスタと、第３の電位に接続される第５のトランジスタと、前記第５のトランジスタ及び前記第４のトランジスタの間に接続される第６のトランジスタと、出力ノードとを備えるセンスアンプと、前記出力ノードの電位が、前記メモリセルからハイレベルのデータが読み出されたことを示すときは、第４の電位を供給し、前記出力ノードの電位が、前記メモリセルからローレベルのデータが読み出されたことを示すときは、前記第１の電位を供給する書き込み回路と、を備えて構成される。 In order to solve the above problems, a semiconductor device of the present invention is connected between a memory cell, a bit line connected to the memory cell by a selection transistor, and the bit line and a first potential. A charge transfer control circuit comprising: a first transistor; a second transistor connected between a sense node and a second potential; and a third transistor connecting the bit line to the sense node; A fourth transistor having a gate connected to the sense node; a fifth transistor connected to a third potential; and a sixth transistor connected between the fifth transistor and the fourth transistor. And when the potential of the output node indicates that high level data has been read from the memory cell, 4 supplies a potential, the potential of the output node, when indicating that the low-level data from said memory cell is read out is constructed and a write circuit for supplying said first potential The

Claims

A method of reading data from a semiconductor device,
Precharge the bit line connected to the memory cell to a first potential;
Precharging the output node of the sense amplifier circuit to a second potential greater than the first potential;
Driving a sense node connected to a sense detection transistor of the sense amplifier circuit to a third potential greater than the first potential;
A transfer transistor that connects the bit line to the sense node is activated, and the potential of the bit line is driven from the first potential to a fourth potential that is higher than the first potential and lower than the second potential. ,
Read data held in the memory cell using the bit line;
Using the sense detection transistor of the sense amplifier circuit to determine whether the data read from the memory cell corresponds to high level data or low level data;
When the read data is high level data, the output node is driven to the first potential, and when the read data is low level data, the output node is kept at the second potential. ,
A writing circuit having an input connected to the output node is used, and when the input receives the first potential from the output node, the fifth potential is greater than the first potential and smaller than the second potential. Supplying a potential, and supplying the first potential when the input receives the second potential from the output node;
A method characterized by that.

The method of claim 1, wherein the sense node is connected to a gate of the sense detection transistor.

The data is read from the memory cell in an accumulated charge read period,
When the data corresponds to high level data, the potential of the bit line is driven from the fourth potential to the sixth potential which is larger than the fourth potential but smaller than the fifth potential, and The transfer transistor is deactivated,
6. When the data corresponds to low level data, the potential of the bit line is driven from the fourth potential to a seventh potential that is smaller than the fourth potential but larger than the first potential. 2. The method according to 2.

4. The method according to claim 3, wherein the fourth potential is equal to a transfer control voltage that is supplied to a gate of the transfer transistor to activate the transfer transistor and is smaller than a threshold voltage of the transfer transistor.

The method of claim 3, wherein the sixth potential is greater than the transfer control voltage.

4. The method according to claim 3, further comprising: activating a word line connected to the memory cell during the accumulated charge readout period to enable the data to be read from the memory cell.

Further, in a sense period following the accumulated charge readout period,
When the data read from the memory cell corresponds to high level data, the sense node is kept at the third potential,
When the data read from the memory cell corresponds to low level data, the sense node is driven to the seventh potential;
The method of claim 3.

The method of claim 7, wherein the sense detection transistor is turned on when the sense node is at the third potential, and is turned off when the sense node is at the seventh potential.

The method according to claim 7, wherein the third potential is equal to or higher than a threshold voltage of the sense detection transistor, and the seventh potential is equal to or lower than the threshold voltage of the sense detection transistor.

When the sense detection transistor is on, the output node of the sense amplifier circuit is driven to the first potential during the sense period;
10. The method according to claim 8, wherein the output node of the sense amplifier circuit is maintained at the second potential when the sense detection transistor is off.

The write circuit has the input for receiving the first potential from the output node and the fifth potential or the first potential depending on whether the data corresponds to high level data or low level data. The method of claim 1, comprising inverters each having an output for providing a potential.

The transistor of the write circuit is activated during the refresh period following the reading of the data from the memory cell, the output of the inverter is connected to the bit line, and the output of the inverter is connected to the bit line during the refresh period. The method according to claim 11, wherein the method is provided.

The method of claim 1, wherein the second and third potentials are equal to each other.

The method of claim 1, wherein the third potential is greater than the second potential.

The method of claim 1, wherein the first potential is a ground potential.

A memory cell;
A bit line connected to the memory cell by a select transistor;
A first transistor connected between the bit line and a first potential; a second transistor connected between a sense node and a second potential; and the bit line connected to the sense node A charge transfer control circuit comprising a third transistor that
A fourth transistor having a gate connected to the sense node; a fifth transistor connected to a third potential; and a sixth transistor connected between the fifth transistor and the fourth transistor. A sense amplifier comprising a transistor and an output node;
When the potential of the output node indicates that high level data has been read from the memory cell, a fourth potential is supplied, and the potential of the output node is low level data from the memory cell. When indicating that the data has been read, a writing circuit for supplying the first potential;
A semiconductor device comprising:

Furthermore,
In a first period, a precharge signal is supplied to the first transistor to precharge the bit line to the first potential, and a precharge signal is supplied to the fifth transistor to set the output node Precharge to the third potential;
Supplying a voltage setting signal to the second transistor to charge the sense node to the second potential in a second period following the first period;
In a third period following the second period, a word line connected to the memory cell is activated to enable reading of data held in the memory cell using the bit line,
In a fourth period following the third period, a sense period control signal for activating the sixth transistor is supplied, and when the data read from the memory cell is high level data, the output node The output node is driven to the first potential, and when the data read from the memory cell is low level data, the output node is maintained at the third potential.
The semiconductor device according to claim 16, comprising a control circuit configured as described above.

The control circuit further activates a transistor of the write circuit to connect the supplied fourth potential or first potential to the bit line in a fifth period following the fourth period. Item 18. The semiconductor device according to Item 17.

The semiconductor device according to claim 17, wherein the third transistor is activated according to a transfer control voltage supplied to a gate thereof.

The semiconductor device according to claim 19, wherein in the second period, the bit line is charged to a reference voltage that is greater than the first potential but less than the transfer control voltage.

In the third period, the reference voltage drops to a fifth potential when the data read from the memory cell is low level data, and the data read from the memory cell is high level data. The semiconductor device according to claim 20, wherein the voltage rises to a sixth potential.

In the fourth period, when the data is high level data, the sense node is kept at the second potential, and when the data is low level data, the sense node is the fifth level. The semiconductor device according to claim 21, which is driven by a potential.

The fourth transistor is turned on in the fourth period when the sense node has the second potential, and is turned off in the fourth period when the sense node has the fifth potential. The semiconductor device according to claim 22.

The semiconductor device according to claim 16, wherein the sense amplifier is a single-ended sense amplifier.

The semiconductor device according to claim 16, wherein the second and third potentials are equal to each other.

The semiconductor device according to claim 16, wherein the second potential is higher than the third potential.

The semiconductor device according to claim 16, wherein the first potential is a ground potential.