JP2014179101A5 - - Google Patents
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- JP2014179101A5 JP2014179101A5 JP2014051611A JP2014051611A JP2014179101A5 JP 2014179101 A5 JP2014179101 A5 JP 2014179101A5 JP 2014051611 A JP2014051611 A JP 2014051611A JP 2014051611 A JP2014051611 A JP 2014051611A JP 2014179101 A5 JP2014179101 A5 JP 2014179101A5
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- JP
- Japan
- Prior art keywords
- entry
- counter
- data processing
- value
- response
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000004044 response Effects 0.000 claims 17
- 230000001419 dependent effect Effects 0.000 claims 10
- 239000013598 vector Substances 0.000 claims 10
- 238000003672 processing method Methods 0.000 claims 8
- 238000000034 method Methods 0.000 claims 1
- 230000001131 transforming effect Effects 0.000 claims 1
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/831,434 | 2013-03-14 | ||
| US13/831,434 US9400653B2 (en) | 2013-03-14 | 2013-03-14 | System and method to clear and rebuild dependencies |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2018071397A Division JP6604689B2 (ja) | 2013-03-14 | 2018-04-03 | ディペンデンシーを整理し、リビルディングするシステム及び方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2014179101A JP2014179101A (ja) | 2014-09-25 |
| JP2014179101A5 true JP2014179101A5 (2) | 2017-03-23 |
| JP6320801B2 JP6320801B2 (ja) | 2018-05-09 |
Family
ID=51419103
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2014051611A Expired - Fee Related JP6320801B2 (ja) | 2013-03-14 | 2014-03-14 | ディペンデンシーを整理し、リビルディングするシステム及び方法 |
| JP2018071397A Expired - Fee Related JP6604689B2 (ja) | 2013-03-14 | 2018-04-03 | ディペンデンシーを整理し、リビルディングするシステム及び方法 |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2018071397A Expired - Fee Related JP6604689B2 (ja) | 2013-03-14 | 2018-04-03 | ディペンデンシーを整理し、リビルディングするシステム及び方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US9400653B2 (2) |
| JP (2) | JP6320801B2 (2) |
| KR (1) | KR102010312B1 (2) |
| CN (1) | CN104050215B (2) |
| DE (1) | DE102014103188A1 (2) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10198263B2 (en) | 2015-09-19 | 2019-02-05 | Microsoft Technology Licensing, Llc | Write nullification |
| US11681531B2 (en) | 2015-09-19 | 2023-06-20 | Microsoft Technology Licensing, Llc | Generation and use of memory access instruction order encodings |
| US10180840B2 (en) * | 2015-09-19 | 2019-01-15 | Microsoft Technology Licensing, Llc | Dynamic generation of null instructions |
| US10031756B2 (en) | 2015-09-19 | 2018-07-24 | Microsoft Technology Licensing, Llc | Multi-nullification |
| US10061584B2 (en) | 2015-09-19 | 2018-08-28 | Microsoft Technology Licensing, Llc | Store nullification in the target field |
| US10185568B2 (en) * | 2016-04-22 | 2019-01-22 | Microsoft Technology Licensing, Llc | Annotation logic for dynamic instruction lookahead distance determination |
| US11474821B1 (en) * | 2021-05-12 | 2022-10-18 | International Business Machines Corporation | Processor dependency-aware instruction execution |
Family Cites Families (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6065105A (en) | 1997-01-08 | 2000-05-16 | Intel Corporation | Dependency matrix |
| US6334182B2 (en) | 1998-08-18 | 2001-12-25 | Intel Corp | Scheduling operations using a dependency matrix |
| US6311266B1 (en) | 1998-12-23 | 2001-10-30 | Cray Inc. | Instruction look-ahead system and hardware |
| US6557095B1 (en) | 1999-12-27 | 2003-04-29 | Intel Corporation | Scheduling operations using a dependency matrix |
| JP2003519833A (ja) | 2000-01-03 | 2003-06-24 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | 依存性連鎖の発行および再発行が可能なスケジューラ |
| US6877086B1 (en) | 2000-11-02 | 2005-04-05 | Intel Corporation | Method and apparatus for rescheduling multiple micro-operations in a processor using a replay queue and a counter |
| US6981129B1 (en) | 2000-11-02 | 2005-12-27 | Intel Corporation | Breaking replay dependency loops in a processor using a rescheduled replay queue |
| US6950927B1 (en) | 2001-04-13 | 2005-09-27 | The United States Of America As Represented By The Secretary Of The Navy | System and method for instruction-level parallelism in a programmable multiple network processor environment |
| JP2007029421A (ja) | 2005-07-27 | 2007-02-08 | Aruze Corp | 遊技機及び遊技システム |
| US20070043932A1 (en) | 2005-08-22 | 2007-02-22 | Intel Corporation | Wakeup mechanisms for schedulers |
| CN101258469B (zh) | 2005-09-05 | 2010-09-15 | 日本电气株式会社 | 信息处理设备 |
| US8291431B2 (en) | 2006-08-29 | 2012-10-16 | Qualcomm Incorporated | Dependent instruction thread scheduling |
| US9946547B2 (en) * | 2006-09-29 | 2018-04-17 | Arm Finance Overseas Limited | Load/store unit for a processor, and applications thereof |
| US7979844B2 (en) | 2008-10-14 | 2011-07-12 | Edss, Inc. | TICC-paradigm to build formally verified parallel software for multi-core chips |
| US8099582B2 (en) | 2009-03-24 | 2012-01-17 | International Business Machines Corporation | Tracking deallocated load instructions using a dependence matrix |
| US8959517B2 (en) | 2009-06-10 | 2015-02-17 | Microsoft Corporation | Cancellation mechanism for cancellable tasks including stolen task and descendent of stolen tasks from the cancellable taskgroup |
| US8453146B2 (en) * | 2009-12-23 | 2013-05-28 | Intel Corporation | Apportioning a counted value to a task executed on a multi-core processor |
| JP5548037B2 (ja) | 2010-06-11 | 2014-07-16 | パナソニック株式会社 | 命令発行制御装置及び方法 |
| US20120023314A1 (en) | 2010-07-21 | 2012-01-26 | Crum Matthew M | Paired execution scheduling of dependent micro-operations |
| FR2965948A1 (fr) * | 2010-10-07 | 2012-04-13 | Commissariat Energie Atomique | Systeme d'ordonnancement de l'execution de taches cadence par un temps logique vectoriel |
-
2013
- 2013-03-14 US US13/831,434 patent/US9400653B2/en not_active Expired - Fee Related
- 2013-12-20 KR KR1020130160342A patent/KR102010312B1/ko not_active Expired - Fee Related
-
2014
- 2014-03-11 DE DE102014103188.1A patent/DE102014103188A1/de not_active Withdrawn
- 2014-03-13 CN CN201410091598.XA patent/CN104050215B/zh not_active Expired - Fee Related
- 2014-03-14 JP JP2014051611A patent/JP6320801B2/ja not_active Expired - Fee Related
-
2016
- 2016-07-12 US US15/208,602 patent/US10552157B2/en not_active Expired - Fee Related
-
2018
- 2018-04-03 JP JP2018071397A patent/JP6604689B2/ja not_active Expired - Fee Related
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