JP6320801B2 - ディペンデンシーを整理し、リビルディングするシステム及び方法 - Google Patents

ディペンデンシーを整理し、リビルディングするシステム及び方法 Download PDF

Info

Publication number
JP6320801B2
JP6320801B2 JP2014051611A JP2014051611A JP6320801B2 JP 6320801 B2 JP6320801 B2 JP 6320801B2 JP 2014051611 A JP2014051611 A JP 2014051611A JP 2014051611 A JP2014051611 A JP 2014051611A JP 6320801 B2 JP6320801 B2 JP 6320801B2
Authority
JP
Japan
Prior art keywords
entry
counter
data processing
value
entries
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2014051611A
Other languages
English (en)
Japanese (ja)
Other versions
JP2014179101A5 (2
JP2014179101A (ja
Inventor
ラヴィ・イェンガー
サンディープ・クマール・ドゥベイ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JP2014179101A publication Critical patent/JP2014179101A/ja
Publication of JP2014179101A5 publication Critical patent/JP2014179101A5/ja
Application granted granted Critical
Publication of JP6320801B2 publication Critical patent/JP6320801B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G06F9/38585—Result writeback, i.e. updating the architectural state or memory with result invalidation, e.g. nullification

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Complex Calculations (AREA)
JP2014051611A 2013-03-14 2014-03-14 ディペンデンシーを整理し、リビルディングするシステム及び方法 Expired - Fee Related JP6320801B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/831,434 2013-03-14
US13/831,434 US9400653B2 (en) 2013-03-14 2013-03-14 System and method to clear and rebuild dependencies

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2018071397A Division JP6604689B2 (ja) 2013-03-14 2018-04-03 ディペンデンシーを整理し、リビルディングするシステム及び方法

Publications (3)

Publication Number Publication Date
JP2014179101A JP2014179101A (ja) 2014-09-25
JP2014179101A5 JP2014179101A5 (2) 2017-03-23
JP6320801B2 true JP6320801B2 (ja) 2018-05-09

Family

ID=51419103

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2014051611A Expired - Fee Related JP6320801B2 (ja) 2013-03-14 2014-03-14 ディペンデンシーを整理し、リビルディングするシステム及び方法
JP2018071397A Expired - Fee Related JP6604689B2 (ja) 2013-03-14 2018-04-03 ディペンデンシーを整理し、リビルディングするシステム及び方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2018071397A Expired - Fee Related JP6604689B2 (ja) 2013-03-14 2018-04-03 ディペンデンシーを整理し、リビルディングするシステム及び方法

Country Status (5)

Country Link
US (2) US9400653B2 (2)
JP (2) JP6320801B2 (2)
KR (1) KR102010312B1 (2)
CN (1) CN104050215B (2)
DE (1) DE102014103188A1 (2)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10198263B2 (en) 2015-09-19 2019-02-05 Microsoft Technology Licensing, Llc Write nullification
US11681531B2 (en) 2015-09-19 2023-06-20 Microsoft Technology Licensing, Llc Generation and use of memory access instruction order encodings
US10180840B2 (en) * 2015-09-19 2019-01-15 Microsoft Technology Licensing, Llc Dynamic generation of null instructions
US10031756B2 (en) 2015-09-19 2018-07-24 Microsoft Technology Licensing, Llc Multi-nullification
US10061584B2 (en) 2015-09-19 2018-08-28 Microsoft Technology Licensing, Llc Store nullification in the target field
US10185568B2 (en) * 2016-04-22 2019-01-22 Microsoft Technology Licensing, Llc Annotation logic for dynamic instruction lookahead distance determination
US11474821B1 (en) * 2021-05-12 2022-10-18 International Business Machines Corporation Processor dependency-aware instruction execution

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6065105A (en) 1997-01-08 2000-05-16 Intel Corporation Dependency matrix
US6334182B2 (en) 1998-08-18 2001-12-25 Intel Corp Scheduling operations using a dependency matrix
US6311266B1 (en) 1998-12-23 2001-10-30 Cray Inc. Instruction look-ahead system and hardware
US6557095B1 (en) 1999-12-27 2003-04-29 Intel Corporation Scheduling operations using a dependency matrix
JP2003519833A (ja) 2000-01-03 2003-06-24 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 依存性連鎖の発行および再発行が可能なスケジューラ
US6877086B1 (en) 2000-11-02 2005-04-05 Intel Corporation Method and apparatus for rescheduling multiple micro-operations in a processor using a replay queue and a counter
US6981129B1 (en) 2000-11-02 2005-12-27 Intel Corporation Breaking replay dependency loops in a processor using a rescheduled replay queue
US6950927B1 (en) 2001-04-13 2005-09-27 The United States Of America As Represented By The Secretary Of The Navy System and method for instruction-level parallelism in a programmable multiple network processor environment
JP2007029421A (ja) 2005-07-27 2007-02-08 Aruze Corp 遊技機及び遊技システム
US20070043932A1 (en) 2005-08-22 2007-02-22 Intel Corporation Wakeup mechanisms for schedulers
CN101258469B (zh) 2005-09-05 2010-09-15 日本电气株式会社 信息处理设备
US8291431B2 (en) 2006-08-29 2012-10-16 Qualcomm Incorporated Dependent instruction thread scheduling
US9946547B2 (en) * 2006-09-29 2018-04-17 Arm Finance Overseas Limited Load/store unit for a processor, and applications thereof
US7979844B2 (en) 2008-10-14 2011-07-12 Edss, Inc. TICC-paradigm to build formally verified parallel software for multi-core chips
US8099582B2 (en) 2009-03-24 2012-01-17 International Business Machines Corporation Tracking deallocated load instructions using a dependence matrix
US8959517B2 (en) 2009-06-10 2015-02-17 Microsoft Corporation Cancellation mechanism for cancellable tasks including stolen task and descendent of stolen tasks from the cancellable taskgroup
US8453146B2 (en) * 2009-12-23 2013-05-28 Intel Corporation Apportioning a counted value to a task executed on a multi-core processor
JP5548037B2 (ja) 2010-06-11 2014-07-16 パナソニック株式会社 命令発行制御装置及び方法
US20120023314A1 (en) 2010-07-21 2012-01-26 Crum Matthew M Paired execution scheduling of dependent micro-operations
FR2965948A1 (fr) * 2010-10-07 2012-04-13 Commissariat Energie Atomique Systeme d'ordonnancement de l'execution de taches cadence par un temps logique vectoriel

Also Published As

Publication number Publication date
DE102014103188A1 (de) 2014-09-18
US20140281404A1 (en) 2014-09-18
US20160321079A1 (en) 2016-11-03
US9400653B2 (en) 2016-07-26
JP2018106760A (ja) 2018-07-05
CN104050215A (zh) 2014-09-17
KR102010312B1 (ko) 2019-08-13
US10552157B2 (en) 2020-02-04
JP2014179101A (ja) 2014-09-25
JP6604689B2 (ja) 2019-11-13
CN104050215B (zh) 2019-04-09
KR20140113304A (ko) 2014-09-24

Similar Documents

Publication Publication Date Title
JP6604689B2 (ja) ディペンデンシーを整理し、リビルディングするシステム及び方法
TWI644208B (zh) 藉由對硬體資源之限制實現的向後相容性
TWI654562B (zh) 藉由演算法匹配、停用特徵或限制效能之回溯相容性
US9639369B2 (en) Split register file for operands of different sizes
US8086826B2 (en) Dependency tracking for enabling successive processor instructions to issue
JP6051458B2 (ja) 複数のハッシュ動作を効率的に実行する方法および装置
US20150277925A1 (en) Data processing apparatus and method for executing a stream of instructions out of order with respect to original program order
US20170024205A1 (en) Non-shifting reservation station
US20120204014A1 (en) Systems and Methods for Improving Divergent Conditional Branches
US20170192787A1 (en) Loop code processor optimizations
US20200326940A1 (en) Data loading and storage instruction processing method and device
US10592252B2 (en) Efficient instruction processing for sparse data
KR102700119B1 (ko) 어드레스 생성 시간에서 로드 및 스토어 큐 할당 시스템 및 방법
US20120144174A1 (en) Multiflow method and apparatus for operation fusion
JP6073392B2 (ja) 命令としてデータ値を評価するシステムおよび方法
KR20220065048A (ko) 대기열 압축 해제
US20150178089A1 (en) Load synchronization with streaming thread cohorts
US20190196839A1 (en) System and method for increasing address generation operations per cycle
US8452948B2 (en) Hybrid compare and swap/perform locked operation queue algorithm
US20190056953A1 (en) Token-based data dependency protection for memory access
WO2017116927A1 (en) Zero cache memory system extension
JP7681580B2 (ja) 選択不可能なスケジューラキューの後のレジスタリネーミング
JP2009176311A (ja) Ｊａｖａアクセラレータを備えたプロセッサシステム

Legal Events

Date Code Title Description
RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20141226

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170214

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20170214

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20180214

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20180305

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20180404

R150 Certificate of patent or registration of utility model

Ref document number: 6320801

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees