JP2018133473A - Semiconductor device manufacturing method and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve problems that a probe is required to be directly brought into contact with an impurity region when sheet resistance is measured by a four probe method and the like, and that a substrate for process control is required separately thereby to increase manufacturing cost, and that in estimation of an impurity concentration by the sheet resistance, it is difficult to detect crystal defects caused in a silicon substrate when an impurity is over dosed.SOLUTION: A manufacturing method for a semiconductor device having a silicon-containing substrate comprises the steps of: forming, on a substrate, a thin film including an impurity against the substrate and perform heat treatment on the substrate so as to form, in the substrate, an impurity region where the impurity is diffused; and measuring a refraction index of the thin film.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device.

Conventionally, a silicon substrate is doped with impurities by a solid phase diffusion method using a boron silicide film as a diffusion source (see, for example, Patent Document 1).
[Prior art documents]
[Patent Literature]
[Patent Document 1] JP-A-7-183247

  When forming an impurity region by diffusing boron into a silicon substrate, the BSG film is usually removed to confirm whether the impurity region has been formed at a desired impurity concentration, and the impurity region is obtained by a four-probe method or the like. Measure the area sheet resistance. The impurity concentration in the impurity region can be estimated from the sheet resistance. However, when measuring the sheet resistance by the four-probe method or the like, it is necessary to directly contact the probe and the impurity region. In addition, since a process management substrate is required separately, the manufacturing cost increases. Furthermore, in the estimation of the impurity concentration by the sheet resistance, there is a problem that it is difficult to detect a crystal defect generated in the silicon substrate when the impurity is overdose.

  In a first aspect of the present invention, a method for manufacturing a semiconductor device is provided. The semiconductor device may have a substrate containing silicon. The method for manufacturing a semiconductor device may include a step of forming a thin film on the substrate, heat-treating the substrate, and measuring a refractive index of the thin film. The thin film may contain impurities for the substrate. In the step of forming a thin film on the substrate and heat-treating the substrate, impurity regions may be formed in the substrate. In the impurity region, impurities may be diffused from the thin film to the substrate.

  The method for manufacturing a semiconductor device may further include a step of estimating the sheet resistance of the impurity region based on the refractive index of the thin film.

  The method for manufacturing a semiconductor device may further include a step of estimating the impurity concentration in the impurity region based on the refractive index of the thin film.

  The method for manufacturing a semiconductor device may further include a step of estimating the number of precipitates generated on the surface of the substrate based on the refractive index of the thin film.

  Furthermore, the method for manufacturing a semiconductor device may further include a step of estimating the impurity concentration in the thin film based on the refractive index of the thin film.

  The thin film may be a PSG film. The impurity may be phosphorus.

The impurity region may have an impurity concentration of 1E + 19 cm ⁻³ or more and less than 1E + 20 cm ⁻³ .

  Measuring the refractive index of the thin film may be after forming the thin film on the substrate and heat treating the substrate. The method for manufacturing a semiconductor device may further include a step of additionally heat-treating the substrate based on the refractive index of the thin film after the step of measuring the refractive index of the thin film.

  In the step of measuring the refractive index of the thin film, the refractive index of the thin film provided in contact with the entire back surface of the substrate may be measured.

  In a second aspect of the present invention, a semiconductor device is provided. The semiconductor device may include a substrate, a protective film, and a thin film. The substrate may include silicon. The protective film may be provided above the substrate. The thin film may contain impurities for the substrate. Further, the thin film may be at least partially not covered with the protective film and may be in contact with the impurity region provided in a rectangular ring shape when the substrate is viewed from above.

  The thin film may have a thickness of 300 nm or less.

  It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

It is a figure which shows the (a) upper surface and (b) cross section of the diode 100 in 1st Embodiment. FIG. 3 is a flow diagram showing steps for manufacturing a diode 100. FIG. 3 is a diagram illustrating steps for manufacturing a diode 100. It is a figure which shows the experimental result which measured the refractive index with respect to sheet resistance, and the number of precipitates. It is a flowchart in the 1st modification of 1st Embodiment. It is a figure which shows the (a) upper surface and (b) cross section of the diode 200 in 2nd Embodiment.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

  FIG. 1 is a diagram illustrating a top surface and a (b) cross section of a diode 100 according to the first embodiment. A cross section taken along line AA in FIG. 1A corresponds to FIG. In order to facilitate understanding, the mask layer 20, the BSG film 24, the PSG film, the anode electrode 30, and the protective film 35 in FIG. 1B are omitted in FIG.

  In the top view of FIG. 1A, the semiconductor substrate 10 of this example has four sides parallel to the X axis and the Y axis. The X axis and the Y axis are axes orthogonal to each other. In this example, the XY plane is parallel to the back surface 11 and the front (front) surface 19 of the semiconductor substrate 10. The Z axis is orthogonal to the X axis and the Y axis. The X-axis direction, the Y-axis direction, and the Z-axis direction form a so-called right hand system.

  In this specification, the positive direction of the Z-axis may be referred to as “up” and the negative direction of the Z-axis may be referred to as “down”. Further, the negative direction of the Z axis may be referred to as the depth direction of the semiconductor substrate 10. The top and bottom are merely convenient expressions for specifying the relative positional relationship between the substrate, the region, the layer, the film, and the like. For example, the Z-axis direction does not necessarily mean the direction of gravity or the direction perpendicular to the ground.

  The semiconductor substrate 10 may be a semiconductor chip. The semiconductor substrate 10 may contain silicon. Although the semiconductor substrate 10 of this example is a silicon substrate, the semiconductor substrate 10 may be a silicon carbide (SiC) substrate. The semiconductor substrate 10 of this example includes a lower cathode region 12, an upper cathode region 14, an anode region 16, and a field limiting ring (FLR) 18.

The lower cathode region 12 and the upper cathode region 14 are first conductivity type impurity regions. In this example, the first conductivity type is n-type. The lower cathode region 12 in this example is an n ⁺ type impurity region. The lower cathode region 12 in this example is exposed on the back surface 11.

The lower cathode region 12 of this example is formed by diffusing n-type impurities on the back surface 11 of the n ⁻ -type silicon substrate. However, in another example, the upper cathode region 14 may be formed by epitaxially growing an n ⁻ type silicon layer on the n ⁺ type lower cathode region 12. The upper cathode region 14 in this example is an n ⁻ type impurity region. The upper cathode region 14 in this example is provided on the lower cathode region 12. The uppermost portion of the upper cathode region 14 in this example is exposed to the surface 19 so as to surround the anode region 16 in the XY plane.

The anode region 16 is a second conductivity type impurity region. In this example, the second conductivity type is p-type. The anode region 16 in this example is a p ⁺ type impurity region. The anode region 16 in this example is provided in the upper cathode region 14. The uppermost portion of the p ⁺ -type anode region 16 in this example is exposed to the surface 19. A pn junction may be formed in the vicinity of the boundary between the anode region 16 and the upper cathode region 14.

The FLR 18 is a first conductivity type impurity region. The FLR 18 in this example is an n ⁺ type impurity region. The FLR 18 may be provided in a rectangular ring shape when viewed from above. The FLR 18 is provided outside the anode region 16 in the top view and inside the outer periphery of the semiconductor substrate 10. A part of the upper cathode region 14 is exposed on the surface 19 between the outer periphery of the FLR 18 and the outer periphery of the semiconductor substrate 10.

  The FLR 18 may have a function of expanding a depletion layer formed in the pn junction region between the anode region 16 and the upper cathode region 14 in the XY plane direction when a reverse bias is applied to the diode 100. By providing the FLR 18, the reverse bias withstand voltage of the diode 100 can be improved as compared with the case where the FLR 18 is not provided.

  In this example, the first conductivity type is n-type and the second conductivity type is p-type. However, in other examples, the first conductivity type is p-type and the second conductivity type is n-type. Good. Here, n or p means that electrons or holes are majority carriers, respectively. For + or − to the right of n or p, + means that the carrier concentration is higher than that where it is not described, and − means that the carrier concentration is lower than that where it is not described.

  The diode 100 as a semiconductor device includes a semiconductor substrate 10, a mask layer 20, a BSG (borosilicate glass) film 24, a PSG (phosphosilicate glass) film 28, an anode electrode 30, a protective film (passivation film) 35, A cathode electrode 40. The anode electrode 30 may be provided on the anode region 16 and may be in direct contact with the uppermost portion of the anode region 16. The anode electrode 30 may not be in direct contact with the upper cathode region 14.

The mask layer 20 is provided on the surface 19 of the semiconductor substrate 10 in direct contact with the semiconductor substrate 10. The mask layer 20 in this example is a silicon dioxide (SiO ₂ ) layer. The BSG film 24 is provided on the mask layer 20 in direct contact with the mask layer 20.

  The mask layer 20 may be used for the purpose of defining a region where the impurity source in the vapor phase diffusion method and the surface 19 of the semiconductor substrate 10 are in contact with each other. In the region covered with the mask layer 20, impurities may not diffuse downward from the mask layer 20. However, it may be allowed that impurities diffuse from the impurity source located at the same height as the mask layer 20 in the XY plane direction and enter under the mask layer 20.

  The BSG film 24 may function as a supply source for supplying boron, which is a p-type impurity, to the semiconductor substrate 10 in the manufacturing process of the diode 100. The BSG film 24 may function as an interlayer insulating film after the diode 100 is manufactured.

  The PSG film 28 is provided on the surface 19 and the BSG film 24 in direct contact with the surface 19 and the BSG film 24. The PSG film 28 may function as a supply source for supplying phosphorus, which is an n-type impurity, to the semiconductor substrate 10 in the manufacturing process of the diode 100. The PSG film 28 may also function as an interlayer insulating film after the diode 100 is manufactured.

  The protective film 35 may be provided above the semiconductor substrate 10. The protective film 35 may be provided on the uppermost part of the diode 100. The protective film 35 in this example is provided on the PSG film 28 and the anode electrode 30. The protective film 35 may have an opening 37 on the anode electrode 30. The anode terminal can be connected to the anode electrode 30 through the opening 37.

  The cathode electrode 40 in this example is provided below the lower cathode region 12 and is in direct contact with the back surface 11. The cathode terminal may be connected to the cathode electrode 40.

  FIG. 2 is a flow diagram illustrating the steps for manufacturing the diode 100. In this example, each step is executed in the order of steps S10 to S60 (that is, in ascending order of numbers).

  FIG. 3 is a diagram illustrating steps for manufacturing the diode 100. For ease of explanation, FIG. 3 shows a cross section of the diode 100 at each stage. S10 to S80 in FIG. 3 correspond to S10 to S80 in FIG. Each stage in FIG. 3 shows a state before the diode 100 is diced from the wafer into a chip. Therefore, in the description of FIG. 3, the semiconductor substrate 10 may be read as a wafer.

S <b> 10 is a step of forming a mask layer 20 on the surface 19 of the semiconductor substrate 10. The mask layer 20 may cover the back surface 11 and the front surface 19 of the semiconductor substrate 10. The mask layer 20 may be a thermal oxide film formed by thermally oxidizing the semiconductor substrate 10. The thermal oxide film may be regarded as a silicon dioxide (SiO ₂ ) film.

  S <b> 20 is a step of providing an opening 21 in the mask layer 20. The opening 21 may be formed using known photolithography and etching techniques. The opening 21 may expose a part of the surface 19. The opening 21 of the present example has a predetermined shape in a region corresponding to the anode region 16. That is, the opening 21 may define the outer shape of the anode region 16 on the surface 19. Since the opening 21 is present in the mask layer 20, the contact region between the BSG film 24 and the surface 19 can be defined by forming the BSG film 24 on the surface 19 and the mask layer 20.

  S30 is a stage in which the BSG film 24 is formed and the semiconductor substrate 10 is heat-treated. That is, S30 of this example includes a step of forming the BSG film 24 and a step of heat-treating the semiconductor substrate 10. In this example, by fixing each side surface of the plurality of semiconductor substrates 10 to a quartz boat, the plurality of semiconductor substrates 10 are arranged inside a chamber of a horizontal CVD apparatus. The temperature inside the chamber and the semiconductor substrate 10 may be adjustable by a heater provided in the horizontal CVD apparatus.

In this example, the BSG film 24 is formed around the semiconductor substrate 10 by introducing the source gas into the chamber. For example, a source gas containing boron tribromide (BBr ₃ ) and oxygen (O ₂ ) is introduced into the chamber. BBr ₃ and O ₂ are materials for forming the BSG film 24, and BBr ₃ is also a vapor phase diffusion source of boron, which is a p-type impurity. When the source gas is introduced into the chamber, the temperature inside the chamber may be 1000 ° C. or higher and 1100 ° C. or lower. Further, the time for forming the BSG film 24 by introducing the source gas into the chamber may be 30 minutes.

  The flow rate of the source gas introduced into the chamber may be controlled by a mass flow controller (MFC). The thickness of the BSG film 24 may be 10 nm or more and 300 nm or less. The thickness of the BSG film 24 in this example is 100 nm or more and 200 nm or less. A person skilled in the art can appropriately determine the flow rate of the mixed gas based on the thickness of the BSG film 24 and the introduction time of the mixed gas. In this example, the BSG film 24 is formed on both surfaces of the semiconductor substrate 10. More specifically, the BSG film 24 is formed on the mask layer 20 and the front surface 19 and also below the back surface 11.

  In the formation of the BSG film 24 and the heat treatment of the semiconductor substrate 10 immediately after that, the temperature inside the chamber may be the same. In this example, after the introduction of the source gas into the chamber is stopped, the semiconductor substrate 10 may be heat-treated at a predetermined temperature for a predetermined time. In this example, the semiconductor substrate 10 is heat-treated at a predetermined temperature of 1000 ° C. to 1100 ° C. for a predetermined time of 5 hours to 10 hours. By a series of BSG film 24 formation and heat treatment, an anode region 16 that is an impurity region in which p-type impurities are diffused from the BSG film 24 to the semiconductor substrate 10 is formed. Thus, in this example, the BSG film 24 and the anode region 16 are formed by the vapor phase diffusion method. Note that, since the entire surface under the back surface 11 is covered with the mask layer 20, the p-type impurity does not diffuse into the back surface 11.

The anode region 16 of this example has a p-type impurity concentration of 1E + 19 cm ⁻³ or more and less than 1E + 20 cm ⁻³ . Note that E means a power of 10. For example, 1E + 19 means 1 × 10 ¹⁹ . By setting the impurity concentration within the above range, the impurity concentration can be within the range of the solid solution limit of the semiconductor substrate 10 while increasing the impurity concentration to some extent.

  When the impurity concentration exceeds the solid solution limit of the semiconductor substrate 10 (that is, when the impurity is overdose into the semiconductor substrate 10), the impurity is deposited on the semiconductor substrate 10. The precipitate can function as a crystal defect. In this example, the crystal defect means a precipitate that can be visually detected.

  S40 is a stage in which openings 22 and 25 are formed in the mask layer 20 and the BSG film 24, and the mask layer 20 and the BSG film 24 in contact with the back surface 11 are removed. In this example, an opening 22 is formed in the mask layer 20 and an opening 25 is formed in the BSG film 24 using a known etching technique. The opening 22 reaches the surface 19 and the opening 25 reaches the opening 22. The opening 22 and the opening 25 may constitute a continuous contact hole. In S40, the mask layer 20 and the BSG film 24 under the back surface 11 are all removed using a known etching technique.

  S50 is a stage in which the PSG film 28 is formed and the semiconductor substrate 10 is heat-treated. That is, S50 of this example includes a step of forming the PSG film 28 and a step of heat-treating the semiconductor substrate 10 as in S30. Similarly to S30, the PSG film 28 may be formed using a horizontal CVD apparatus. The PSG film 28 is an example of a thin film.

The source gas for forming the PSG film 28 may include, for example, phosphoryl chloride (POCl ₃ ) and oxygen (O ₂ ). POCl ₃ and O ₂ are materials for forming the PSG film 28, and POCl ₃ is also a vapor phase diffusion source of phosphorus, which is an n-type impurity. The thickness of the PSG film 28 may be 10 nm or more and 300 nm or less. Since the thickness of 10 nm is thicker than the natural oxide film, it may be regarded as the film thickness formed in the manufacturing process. The thickness of the PSG film 28 in this example is 100 nm or more and 200 nm or less. In the formation of the PSG film 28 and the heat treatment of the semiconductor substrate 10 immediately thereafter, the temperature inside the chamber and the processing time may be the same. The temperature inside the chamber may be 950 ° C. or more and 1050 ° C. or less, and the time for forming the PSG film 28 by introducing the source gas into the chamber may be 1 hour or more and 2 hours or less. In this example, the temperature inside the chamber is 1000 ° C., and the time for forming the PSG film 28 is 1 hour 30 minutes. After the introduction of the source gas is stopped, the semiconductor substrate 10 may be heat-treated at a predetermined temperature of 950 ° C. to 1100 ° C. for a predetermined time of 1 hour to 2 hours. In this example, after the introduction of the source gas is stopped, the semiconductor substrate 10 is heat-treated at 1000 ° C. for 1 hour 30 minutes.

  In this example, the PSG film 28 is formed and heat-treated to form the FLR 18 and the lower cathode region 12 by a vapor phase diffusion method. In S <b> 50, the lower surface of the lower cathode region 12 is formed from the rear surface 11 to a predetermined depth position of the semiconductor substrate 10 by covering the entire surface of the lower surface 11 with the PSG film 28. The FLR 18 is an example of an impurity region in which impurities are diffused from the thin film to the semiconductor substrate 10.

  S54 is a stage in which the refractive index of the PSG film 28 is measured and then various characteristic values are estimated. That is, S54 includes two stages, a stage for measuring the refractive index and a stage for estimating the characteristic value.

  In this example, at least one semiconductor substrate 10 out of the plurality of semiconductor substrates 10 in the horizontal CVD apparatus is taken out of the chamber, and the refractive index of the PSG film 28 is measured. In this example, the refractive index of the PSG film 28 is measured by an ellipsometer having the laser light source 110 and the light receiving unit 120. By using the laser light source 110 and the light receiving unit 120, it is possible to measure the refractive index of the PSG film 28 in a minute region having a diameter of several hundred μm without contacting the PSG film 28. As long as the refractive index of the PSG film 28 can be measured in a non-contact manner, not only the ellipsometry but also other measurement methods may be used.

  The various characteristic values may include the impurity concentration of the PSG film 28, the sheet resistance of the FLR 18, the impurity concentration of the FLR 18, and the number of precipitates of the FLR 18. That is, the stage of estimating various characteristic values includes the stage of estimating the n-type impurity concentration in the PSG film 28 based on the refractive index of the PSG film 28, the stage of estimating the sheet resistance of the FLR 18, and the stage of n in the FLR 18. The method may include one or more steps of estimating the impurity concentration of the mold and estimating the number of precipitates generated on the surface 19 of the semiconductor substrate 10 in the region where the FLR 18 is provided.

  The refractive index of the PSG film 28 may change according to the n-type impurity concentration in the PSG film 28. In this example, the higher the n-type impurity concentration in the PSG film 28, the higher the refractive index of the PSG film 28, and the lower the n-type impurity concentration in the PSG film 28, the lower the refractive index of the PSG film 28.

  Further, the impurity concentration of the FLR 18 may change according to the impurity concentration in the PSG film 28 that is an impurity source. In this example, the higher the n-type impurity concentration in the PSG film 28 is, the higher the n-type impurity concentration in the FLR 18 is. The lower the n-type impurity concentration in the PSG film 28 is, the lower the n-type impurity concentration in the FLR 18 is. The impurity concentration of FLR 18 may be exponentially proportional to the n-type impurity concentration in PSG film 28.

  By obtaining in advance a table or graph that measures the first correspondence between the refractive index of the PSG film 28 and the n-type impurity concentration of the PSG film 28, the refractive index of the PSG film 28 is measured. The impurity concentration of the PSG film 28 can be estimated. Further, the impurity concentration of FLR 18 can also be estimated by measuring the refractive index of the PSG film 28 by using the first correspondence relationship acquired in advance.

  In FLR 18, there is a negative correlation between n-type impurity concentration and sheet resistance. In FLR 18, the higher the n-type impurity concentration, the lower the sheet resistance, and the lower the n-type impurity concentration, the higher the sheet resistance. By obtaining in advance a table or graph that measures the second correspondence between the refractive index of the PSG film 28 and the n-type impurity concentration and sheet resistance in the FLR 18, the refractive index of the PSG film 28 is measured. , The sheet resistance in the FLR 18 can be estimated.

  Thus, in this example, the sheet resistance of the FLR 18 can be estimated without contacting the FLR 18. Therefore, in this example, unlike the case where the sheet resistance of the impurity region is measured by the four-probe method or the like, it is not necessary to directly contact the probe and the impurity region. In this example, when the refractive index is measured, the mask layer 20, the BSG film 24, the PSG film 28, etc. on the surface 19 do not have to be peeled off, so the work required for estimating the sheet resistance is the four-probe method. It is easier compared to etc. Further, in this example, precise work for bringing the probe into contact with the FLR 18 is unnecessary. Therefore, the work time required for estimating the sheet resistance can be shortened as compared with the four-probe method.

  In addition, in this example, unlike the case where the sheet resistance of the impurity region is measured by the four-probe method or the like, the semiconductor substrate 10 for process management itself is not necessary. That is, the semiconductor substrate 10 that is the final product can be used for estimating the sheet resistance. Therefore, the manufacturing cost of the diode 100 can be reduced as compared with the case where the semiconductor substrate 10 for process management is used.

  Furthermore, in this example, the number of crystal defects deposited on the surface 19 can be estimated by measuring the refractive index. This estimation method can estimate the number of precipitates very easily as compared with the four-probe method. The crystal defect may be BSG, PSG, or BPSG (borophosphosilicate gls) deposited on the surface 19. The crystal defects in this example are BPSG lumps.

Crystal defects can occur in the FLR 18. In this example, when forming the anode region 16 having a p-type impurity concentration of 1E + 19 cm ⁻³ or more and less than 1E + 20 cm ^{−3, the} BSG film 24 having a very high concentration of p-type impurity is formed. During the manufacturing process, boron may enter the PSG film 28 and diffuse into the FLR 18. When the semiconductor substrate 10 is a silicon substrate, 1E + 20 cm ⁻³ may be considered as the solid solution limit. Therefore, when the total impurity concentration of the n-type impurity and the p-type impurity exceeds 1E + 20 cm ⁻³ , crystal defects may occur in the silicon substrate. Crystal defects may cause poor characteristics of semiconductor elements. Therefore, it is desirable to sort the semiconductor substrate 10 having a predetermined number or more of crystal defects.

  The difference between the refractive index when the crystal defect occurs in the semiconductor substrate 10 and the refractive index when the crystal defect does not occur is the difference between the sheet resistance when the crystal defect occurs in the semiconductor substrate 10 and the sheet resistance when it does not occur. Is much easier to grasp (see also FIG. 4 and its description below). Therefore, it is easier and more accurate to estimate the number of crystal defects by measuring the refractive index than when estimating the number of crystal defects by measuring the sheet resistance by the four-probe method. The number of defects can be estimated.

  In one example, as a method for detecting a crystal defect, it is conceivable that an operator visually inspects the crystal defect of the semiconductor substrate 10 with an optical microscope or the like. On the other hand, in this example, the number of crystal defects generated on the surface 19 can be estimated by measuring the refractive index, so the number of crystal defects can be estimated more accurately in a shorter time than visual inspection. can do. Accordingly, there is an advantage that it is easy to make an accurate determination as to whether the semiconductor substrate 10 should be discarded or used in the next stage.

Crystal defects may also occur in the n ⁺ -type lower cathode region 12 with which the PSG film 28 is in contact. Therefore, in addition to or instead of measuring the refractive index of the PSG film 28 provided on the FLR 18, the refractive index of the PSG film 28 provided in contact with the entire back surface of the back surface 11 is measured. May be. When boron is mixed from the adjacent semiconductor substrate 10 in the chamber of the horizontal CVD apparatus, crystal defects may also occur near the back surface 11 of the lower cathode region 12. Since the PSG film 28 is provided on the entire surface under the back surface 11, the measurement area is wider than the PSG film 28 on the FLR 18. Therefore, the refractive index of the PSG film 28 is easier.

  S60 is a stage in which openings 23 and 29 are formed in the BSG film 24 and the PSG film 28, and the PSG film 28 in contact with the back surface 11 is removed. In this example, an opening 23 is formed in the BSG film 24 and an opening 29 is formed in the PSG film 28 using a known etching technique. The opening 23 reaches the surface 19 (anode 16) and the opening 29 reaches the opening 23. The opening 23 and the opening 29 may constitute a continuous contact hole. Further, the PSG film 28 under the back surface 11 is completely removed using a known etching technique.

  S70 is a stage in which the anode electrode 30 and the cathode electrode 40 are formed. In this example, after the anode electrode 30 is formed on the surface 19 and the PSG film 28, a part of the anode electrode 30 is removed by etching so as to leave the anode electrode 30 only on the anode region 16. Thereafter, the cathode electrode 40 is formed on the whole under the back surface 11. The anode electrode 30 may be formed after the cathode electrode 40 is formed.

  S80 is a stage in which the protective film 35 is formed. In this example, after forming the protective film 35 on the anode electrode 30 and the PSG film 28, a part of the protective film 35 is removed by etching so that the opening 37 is formed only on the anode electrode 30.

  FIG. 4 is a diagram showing experimental results obtained by measuring the refractive index with respect to the sheet resistance and the number of precipitates. First, the refractive index of the PSG film 28 of each sample in which the FLR 18 was formed was measured by a vapor phase diffusion method. Further, the PSG film 28 was removed, and the sheet resistance of the FLR 18 of each sample was measured by a four-terminal method. Further, for some samples, the number of precipitates generated on the surface 19 was visually counted using an optical microscope.

  The horizontal axis is the sheet resistance (Ω / □) displayed on a logarithmic scale. The vertical axis on the left is the refractive index of the PSG film 28. The vertical axis on the right is the number of precipitates generated in a 25 mm × 25 mm square on the surface 19. In FIG. 4, the refractive index is indicated by diamonds, and the number of precipitates is indicated by squares.

  According to the results of this experiment, it was observed that the sample with higher sheet resistance has a lower refractive index, and the sample with lower sheet resistance has a higher refractive index. In the vicinity of the sheet resistance of about 2.2 (Ω / □), the refractive index changed rapidly. Further, the refractive index gradually decreased from a sheet resistance of 3.0 (Ω / □) to 100 (Ω / □). Thus, there was a clear negative correlation between sheet resistance and refractive index.

  There was also a negative correlation between sheet resistance and the number of precipitates. It is considered that the lower the sheet resistance, the higher the impurity concentration of FLR 18, and accordingly the number of precipitates is relatively large. Further, it is considered that the higher the sheet resistance, the relatively low the impurity concentration of FLR 18 and the relatively small number of precipitates accordingly.

  In the sample having a sheet resistance of about 2.2 (Ω / □), the number of precipitates is 18, and in the sample having a sheet resistance of about 4.1 (Ω / □), the number of precipitates is 3, and the sheet resistance is about 6. In the sample of 2 (Ω / □), the number of precipitates was zero. Thus, the number of precipitates changed abruptly when the sheet resistance changed by several (Ω / □). As described above, it is difficult to estimate the number of precipitates by measuring the sheet resistance while the sheet resistance slightly changes.

  On the other hand, it is clear from FIG. 4 that the change in the refractive index changes rapidly according to the change in the number of precipitates. Therefore, by estimating the number of precipitates by measuring the refractive index, it is possible to estimate the generation of precipitates more sensitively than when measuring the sheet resistance by the four probe method. That is, the refractive index is superior for detecting the occurrence of precipitates compared to the sheet resistance.

As described above, when the semiconductor substrate 10 is a silicon substrate, for example, if the total impurity concentration in the FLR 18 exceeds 1E + 20 cm ⁻³ , crystal defects may occur. In one example, a specific region of the semiconductor substrate 10 is doped with boron of 5E + 19 cm ⁻³ and doped with 6E + 19 cm ⁻³ of phosphorus, thereby doping the specific region with a total of 1.1E + 20 cm ⁻³ of impurities. Is done. Thereby, crystal defects may occur in the specific region.

  FIG. 5 is a flowchart in the first modification of the first embodiment. In this example, a step (S56) of additionally heat-treating the semiconductor substrate 10 is further provided after S54. This is different from the first embodiment. Other points are the same as in the first embodiment.

  In this example, the semiconductor substrate 10 is additionally heat-treated (S56) based on the refractive index of the PSG film 28 obtained in the refractive index measurement (S54). For example, when the impurity concentration of the PSG film 28 measured in S54 is estimated to be lower than a predetermined value, the temperature of the additional heat treatment (S56) is increased and / or the additional heat treatment (S56) is performed. Increase time.

  Thereby, impurities diffused from the PSG film 28 to the semiconductor substrate 10 can be increased, and the impurity concentration of the FLR 18 can be brought close to or matched with the design value. That is, the deviation from the design value of the impurity concentration in the PSG film 28 can be compensated for in the next stage. This is advantageous because the quality of the diode 100 can be easily managed.

In the above-described first embodiment and its modifications, the example in which the PSG film 28 is formed in order to form the n ⁺ type FLR 18 has been described. However, in other examples, the PSG film 28 may be used to form an n-type or n ⁻ -type FLR 18. In still another example, in the case where the BSG film 24 is formed to form the p-type or p ⁺ -type FLR 18, the PSG film 28 is changed to the BSG film, and the first embodiment and its modifications. An example may apply.

  FIGS. 6A and 6B are diagrams showing a (a) top surface and a (b) cross section of the diode 200 in the second embodiment. A cross section taken along line BB in FIG. 6A corresponds to FIG. As in FIG. 1, the mask layer 20, the BSG film 24, the PSG film, the anode electrode 30, and the protective film 35 in FIG. 6B are omitted in FIG.

  The protective film 35 of this example has an opening 38 above the FLR 18. The opening 38 is not at least partially covered by the protective film 35 and exposes the PSG film 28 in contact with the FLR 18 to the outside. In this regard, this example is different from the first embodiment. In FIG. 6A, the outlines of the opening 37 and the opening 38 of the protective film 35 are indicated by dotted lines.

  In this example, the refractive index of the PSG film 28 can be measured after the diode 200 is completed. Therefore, based on the refractive index of the PSG film 28, the n-type impurity concentration in the PSG film 28, the sheet resistance of the FLR 18 are estimated, the n-type impurity concentration in the FLR 18 is estimated, and the semiconductor substrate 10 One or more estimations of the number of precipitates generated on the surface 19 can be made. That is, it is advantageous that the failure analysis of the diode 200 can be performed even after the diode 200 is manufactured.

  The thickness of the PSG film 28 is 300 nm or less. On the other hand, an interlayer insulating film usually used for a semiconductor device has a thickness of about 1 μm. For a thickness of about 1 μm, it may be difficult to measure the refractive index. On the other hand, since the PSG film 28 of this example is sufficiently thinner than a normal interlayer insulating film, the refractive index can be reliably measured.

  Although the example of the semiconductor device in the above is only a diode, the technique of the present application may be applied to a semiconductor device other than the diode. The technology of the present application is an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal Oxide Field Transistor Transistor), an IGBT and a FWD (Free Wheeling Diode), which is a B-based RC.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above embodiment. It is apparent from the description of the scope of claims that embodiments with such changes or improvements can be included in the technical scope of the present invention.

  The order of execution of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior to”. It should be noted that the output can be realized in any order unless the output of the previous process is used in the subsequent process. Even if the operation flow in the claims, the description, and the drawings is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

  10..Semiconductor substrate, 11..Back surface, 12..Lower cathode region, 14..Upper cathode region, 16..Anode region, 18..FLR, 19..Front surface, 20..Mask layer, 21 .. Aperture, 22 ... aperture, 23 ... aperture, 24 ... BSG film, 25 ... aperture, 28 ... PSG film, 29 ... aperture, 30 ... anode electrode, 35 ... protective film, 37 ... aperture , 38 .. Opening, 40 .. Cathode electrode, 100 .. Diode, 110 .. Laser light source, 120 .. Light receiving part, 200.

Claims (11)

A method of manufacturing a semiconductor device having a substrate containing silicon,
Forming a thin film including impurities on the substrate on the substrate, and heat-treating the substrate to form an impurity region on the substrate in which the impurities are diffused from the thin film to the substrate;
Measuring the refractive index of the thin film. The method for manufacturing a semiconductor device according to claim 1, further comprising estimating a sheet resistance of the impurity region based on the refractive index of the thin film. The method for manufacturing a semiconductor device according to claim 1, further comprising estimating a concentration of the impurity in the impurity region based on the refractive index of the thin film. 4. The method of manufacturing a semiconductor device according to claim 1, further comprising estimating a number of precipitates generated on the surface of the substrate based on the refractive index of the thin film. 5. The method of manufacturing a semiconductor device according to claim 1, further comprising estimating a concentration of the impurity in the thin film based on the refractive index of the thin film. The method for manufacturing a semiconductor device according to claim 1, wherein the thin film is a PSG film, and the impurity is phosphorus. The method for manufacturing a semiconductor device according to claim 1, wherein the impurity region has an impurity concentration of 1E + 19 cm ⁻³ or more and less than 1E + 20 cm ⁻³ . Measuring the refractive index of the thin film is after forming the thin film on the substrate and heat treating the substrate;
The semiconductor device according to claim 1, further comprising a step of additionally heat-treating the substrate based on the refractive index of the thin film after the step of measuring the refractive index of the thin film. Manufacturing method.
The method for manufacturing a semiconductor device according to claim 1, wherein in the step of measuring the refractive index of the thin film, the refractive index of the thin film provided in contact with the entire back surface of the substrate is measured. A semiconductor device,
A substrate containing silicon;
A protective film provided above the substrate;
A semiconductor device comprising: a thin film that is not covered with the protective film and is in contact with an impurity region provided in a rectangular ring shape in a top view of the substrate and includes an impurity with respect to the substrate. The semiconductor device according to claim 10, wherein the thin film has a thickness of 300 nm or less.

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