JP2019083247A - Semiconductor device - Google Patents

Abstract

In a semiconductor device including a reference voltage generation circuit, a technique capable of reducing the temperature dependence of an output voltage output from the reference voltage generation circuit is provided. A semiconductor device includes a semiconductor chip mainly composed of silicon carbide and formed with a reference voltage generation circuit. Here, the reference voltage generation circuit includes a resistance element and a diode, and the resistance element is configured by a diffusion resistance element (p-type semiconductor region PR1) into which an acceptor is introduced. [Selection] Figure 10

Description

  The present invention relates to a semiconductor device, for example, to a technology effectively applied to a semiconductor device including a semiconductor chip made of silicon carbide and having a reference voltage generation circuit formed thereon.

  Patent Document 1 (Japanese Patent Laid-Open No. 2003-258105) describes a technique capable of reducing the temperature dependency of the output voltage from the reference voltage generation circuit. In this technology, in order to reduce the temperature dependency of the output voltage, an example is described in which a polysilicon resistor or an on-resistance of a field effect transistor is used as a component of the reference voltage generation circuit.

Japanese Patent Application Publication No. 2003-258105

  As a semiconductor device operable at high temperature, there is a semiconductor device having a semiconductor chip made of silicon carbide (hereinafter sometimes referred to as SiC). In the case of a semiconductor device using silicon carbide, since the band gap of silicon carbide exhibiting heat resistance is about three times the band gap of silicon (Si), carbonization as a component of an information processing apparatus even under high temperature conditions A semiconductor device using silicon can be employed. Also, a highly heat-resistant reference voltage generation circuit for supplying power to the information processing apparatus can be realized. In this regard, in order to make the reference voltage generation circuit usable even in a high temperature environment, a reference voltage generation circuit capable of supplying a stable output voltage even in a high temperature environment is desired. That is, it is desirable that the temperature dependency of the output voltage output from the reference voltage generation circuit be small even in a high temperature environment.

  An object of the present invention is to provide a technique capable of reducing the temperature dependency of an output voltage output from a reference voltage generation circuit in a semiconductor device including a reference voltage generation circuit.

  Other problems and novel features will be apparent from the description of the present specification and the accompanying drawings.

  The semiconductor device in one embodiment includes a semiconductor chip which is mainly composed of silicon carbide and on which a reference voltage generation circuit is formed. Here, the reference voltage generation circuit includes a resistance element and a diode, and the resistance element is formed of a diffusion resistance element into which an acceptor is introduced.

  According to one embodiment, the temperature dependence of the output voltage output from the reference voltage generation circuit can be reduced in a wide temperature range.

It is a circuit diagram showing an example of composition of a reference voltage generation circuit. It is a graph which shows the relationship between temperature and an activation rate. In acceptor concentration in the silicon carbide (N _A) introduced the aluminum 3 × 10 ¹⁷ cm ^-3 p-type diffused resistor element is a graph showing the relationship between temperature and the sheet resistance. It is a graph which shows typically the IV characteristic of the diode which used silicon. It is a graph which shows typically the IV characteristic of the diode which used silicon carbide. It is a graph which shows the temperature dependence of the forward voltage of the diode which used silicon carbide, when load current is 1 microampere. It is a graph which shows the relationship of the temperature and load current in, when it comprises resistive element R1 shown in FIG. 1 from the p-type diffused resistive element which consists of a p-type semiconductor area | region which aluminum was introduce | transduced into silicon carbide. A graph showing the relationship between temperature and forward voltage VF when the load current is controlled to be constant, and a graph showing the relationship between temperature and forward voltage VF when the load current is changed as shown in FIG. 7 FIG. It is a graph which shows the temperature dependency of the output voltage output from the output terminal of the reference voltage generation circuit shown in FIG. FIG. 2 is a cross-sectional view illustrating a device structure of a semiconductor device in the embodiment. FIG. 7 is a diagram showing a circuit configuration of a reference voltage generation circuit in a modification 1; FIG. 18 is a cross-sectional view for explaining the device structure of the semiconductor device in Modification 1; FIG. 18 is a cross-sectional view for explaining the device structure of the semiconductor device in Modification 2; FIG. 16 is a cross-sectional view for explaining another device structure that embodies the technical idea in the second modification. FIG. 16 is a cross-sectional view for explaining another device structure that embodies the technical idea in the second modification.

  In the following embodiments, when it is necessary for the sake of convenience, it will be described by dividing into a plurality of sections or embodiments, but they are not unrelated to each other unless specifically stated otherwise, one is the other And some or all of the variations, details, and supplementary explanations.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), it is particularly pronounced and clearly limited to a specific number in principle. It is not limited to the specific number except for the number, and may be more or less than the specific number.

  Furthermore, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily essential unless explicitly stated or considered to be obviously essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components etc., unless specifically stated otherwise and in principle not considered otherwise in principle, etc., It includes those that are similar or similar to the shape etc. The same applies to the above numerical values and ranges.

  Further, in all the drawings for describing the embodiments, the same reference numeral is attached to the same member in principle, and the repetitive description thereof will be omitted. In order to make the drawings easy to understand, hatching may be attached even to a plan view.

<Configuration Example of Reference Voltage Generation Circuit>
FIG. 1 is a circuit diagram showing a configuration example of a reference voltage generation circuit. The reference voltage generation circuit shown in FIG. 1 includes a power supply line VL, a ground line GL, a resistance group 100 including two resistance elements R1 and R2, and a diode group 200 including three diodes Q1 to Q3. And five field effect transistors M1 to M5. In the reference voltage generation circuit shown in FIG. 1, of the five field effect transistors M1 to M5, the field effect transistor M1 and the field effect transistor M3 are formed of n-channel field effect transistors. On the other hand, the field effect transistor M2, the field effect transistor M4, and the field effect transistor M5 are composed of p-channel field effect transistors.

  Here, for example, when integrating the reference voltage generation circuit on one semiconductor chip, the diodes Q1 to Q3 often adopt a configuration in which the base and collector of the npn bipolar transistor are shorted, and the occupied area of the diode Q2 Is larger by “K times” the area occupied by the diode Q1 and the area occupied by the diode Q3. At this time, in the reference voltage generation circuit shown in FIG. 1, the cathodes of the diodes Q1 to Q3 are connected to the ground line GL to which the reference potential is supplied.

  Furthermore, in the reference voltage generation circuit shown in FIG. 1, the field effect transistor M1 and the field effect transistor M3 constitute an n channel current mirror circuit, and the field effect transistor M2 and the field effect transistor M4 are p channel current mirror It constitutes a circuit. In the reference voltage generation circuit shown in FIG. 1, an n-channel current mirror circuit composed of a field effect transistor M1 and a field effect transistor M3, and a p channel current composed of a field effect transistor M2 and a field effect transistor M4. Two stages of mirror circuits are stacked in series. The current mirror circuit is a circuit that supplies the same current from the power supply line VL, and has a configuration in which a common potential is supplied to the gate electrode of the field effect transistor M1 and the gate electrode of the field effect transistor M3. The potential at point A and the potential at point B shown in FIG. 1 become equal. As a result, it is possible to equalize the voltages applied to the circuit composed of the resistor group 100 and the diode group 200. In particular, since the gate electrode of the field effect transistor M5 is short-circuited between the gate electrode of the field effect transistor M2 and the gate electrode of the field effect transistor M4, the field effect transistor M5 functions as a current source. The current having the same current value as the current flowing through the field effect transistor M4 can be supplied to the output terminal OT.

  The output voltage Vref output from the reference voltage generation circuit configured in this way can be expressed by the following equation (1).

Vref = V _BE3 + (kT / q) × (r2 / r1) × ln (K) formula (1)
Here, “V _BE3 ” represents the base-emitter voltage of the diode Q 3, “k” represents the Boltzmann constant, “T” represents the absolute temperature, and “q” represents the elementary charge. . Also, “r1” indicates the resistance value of the resistance element R1, and “r2” indicates the resistance value of the resistance element R2. Furthermore, “K” indicates the area ratio of the area occupied by the diode Q2 to the area occupied by the diode Q1.

  Next, the load current in the reference voltage generation circuit shown in FIG. 1 will be described. The load current is a factor that affects the power consumption of the reference voltage generation circuit, and can be expressed, for example, by the following equation (2).

I = (kT / q) × ln (K) / r1 formula (2)
From this equation (2), the load current in the reference voltage generation circuit shown in FIG. 1 is “K” which is the ratio of the resistance value “r1” of resistance element R1 to the area occupied by diode Q2 to the area occupied by diode Q1. It can be seen that it is determined by However, since the design range of the area ratio "K" is narrow, the load current is mainly adjusted by the resistance value "r1" of the resistance element R1. For example, when the load current is set to 1 μA or less to reduce the power consumption of the reference voltage generation circuit, although depending on the temperature range in which the reference voltage generation circuit is used, the resistance value r1 of the resistance element R1 is several tens It is designed to kΩ to several hundreds kΩ.

  As described above, when the load current is determined according to the equation (2), the output voltage Vref is substantially adjusted by the resistance value r2 of the resistance element R2 according to the equation (1).

<First Basic Idea in Embodiment>
As described above, the output voltage Vref output from the reference voltage generation circuit is expressed by equation (1). At this time, the base-emitter voltage "V _BE3 " of the diode Q3 has a negative temperature characteristic because it depends on the built-in potential (forward voltage VF) of the pn junction. That is, the higher the temperature is, the smaller the built-in potential is, so the base-emitter voltage of diode Q3 "V _BE3 " is smaller.

In this regard, the basic idea in the present embodiment is that the temperature dependency of “V _BE3 ” shown in the first term of the equation (1) is given by “(kT / q It is an idea that the temperature dependency of the output voltage Vref output from the reference voltage generation circuit is reduced by canceling the temperature dependency by x × (r2 / r1) × ln (K) ”.

Here, when the load current is determined by the equation (2), “K” and “r1” in the equation (1) are determined, so that the adjustment of the second term of the equation (1) is substantially It is adjusted only by the resistance value "r2" of the resistance element R2. Then, in the second term of the equation (1), in order to cancel the temperature dependence of the first term of the equation (1), the first term of the equation (1) has negative temperature characteristics In consideration of the above, the second term of the equation (1) also needs to have negative temperature characteristics. This is because the built-in potential affecting the first term “V _BE3 ” of the formula (1) becomes smaller as the temperature becomes higher, so that “V _BE3 ” becomes smaller, but the numerator of the second term of the formula (2) This is because the resistance value r2 of the existing resistive element R2 has negative temperature characteristics. That is, the fact that the resistance value r2 of the resistance element R2 present in the molecule of the second term of the equation (2) has negative temperature characteristics means that the higher the temperature in the reference voltage generation circuit shown in FIG. This means that the current flowing to the resistance element R2 is increased, which causes the current flowing to the diode Q3 to be increased. And, the fact that the current flowing through the diode Q3 is increased means that the forward voltage of the diode Q3 is increased according to Ohm's law, and the increase of the forward voltage causes a drop in the built-in potential of "V _BE3 ". As a result, the temperature dependency of the output voltage Vref from the reference voltage generation circuit is reduced.

Therefore, in order to realize the first basic concept in the present embodiment, it is necessary to configure the resistive element R2 from a resistive element having a negative temperature characteristic. Thus, the first basic idea in the present embodiment is that the temperature dependency of “V _BE3 ” shown in the first term of the formula (1) is given by “(kT shown in the second term of the formula (2) / Q) x (r2 / r1) x ln (K) "is the idea of canceling with temperature dependency, and in order to embody this first basic idea, resistive element R2 has negative temperature characteristics It needs to be composed of resistive elements.

<Consideration to embody the first basic idea>
As described above, in order to embody the first basic concept in the present embodiment, it is necessary to adopt the resistive element R2 having a negative temperature characteristic. Therefore, a resistive element made of metal can not be used as the resistive element R2. This is because the metal resistive element has positive temperature characteristics. Next, for example, it is conceivable to adopt a polysilicon resistance element made of a polysilicon film as the resistance element R2, but the polysilicon resistance element is a unipolar device, and the influence of electron scattering due to lattice vibration at high temperatures growing. As a result, the polysilicon resistance element can not be adopted as the resistance element R2 because it has a positive temperature characteristic that the resistance value becomes higher as the temperature becomes higher. For the same reason, a diffused resistor whose component is a semiconductor region made of silicon can not be used either.

  In this regard, the situation is completely different in a semiconductor device using silicon carbide. That is, the diffusion resistance element having the semiconductor region made of silicon carbide as a component has a temperature characteristic different from that of the diffusion resistance element having the semiconductor region made of silicon as a constituent. That is, the diffusion resistance element having a semiconductor region made of silicon carbide as a component has negative temperature characteristics.

<The reason why the diffusion resistance element in which conductive impurities are introduced into silicon carbide has negative temperature characteristics>
The reason that the diffusion resistance element in which the conductive impurity is introduced into silicon carbide has negative temperature characteristics is that the activation ratio of the conductive impurity introduced into the semiconductor region made of silicon carbide has a large temperature dependency. It is from. FIG. 2 is a graph showing the relationship between the temperature and the activation rate. In FIG. 2, the broken line indicates the temperature dependence of the activation ratio of nitrogen when nitrogen (N), which is an n-type impurity (donor), is introduced into the semiconductor region made of silicon carbide. On the other hand, in FIG. 2, the solid line indicates the temperature dependency of the activation ratio of aluminum when aluminum (Al), which is a p-type impurity (acceptor), is introduced into the semiconductor region made of silicon carbide. At this time, for example, the activation rate of the acceptor is smaller than the activation rate of the donor.

  As shown in FIG. 2, it can be seen that the activation ratio increases as the temperature rises, in both the donor nitrogen and the acceptor aluminum. As a result, for example, in a diffusion resistance element consisting of an n-type semiconductor region in which nitrogen is introduced into silicon carbide, the activation ratio of nitrogen increases as the temperature rises, and the conduction band from nitrogen serving as a donor to silicon carbide As a result, the amount of electrons supplied to the n.sup. Therefore, an n-type diffused resistor element formed of an n-type semiconductor region in which nitrogen is introduced into silicon carbide has negative temperature characteristics.

  On the other hand, for example, even in the case of a p-type diffusion resistive element consisting of a p-type semiconductor region in which aluminum is introduced into silicon carbide, the activation ratio of aluminum increases when the temperature rises, and the acceptor aluminum is the valence of silicon carbide. The amount of electrons trapped in the electron band is increased, and many holes are generated in the valence band. As a result, the resistance value of the p-type diffused resistance element is lowered. Therefore, the p-type diffused resistive element also has negative temperature characteristics.

  By the above mechanism, the diffusion resistance element (both n-type diffusion resistance element and p-type diffusion resistance element) in which conductive impurities are introduced into silicon carbide exhibits negative temperature characteristics.

<Reason for adopting p-type diffusion resistance element>
Here, as shown in FIG. 2, the temperature dependence of the activation ratio of aluminum, which is a p-type impurity (acceptor), is greater than the temperature dependence of the activation ratio of nitrogen, which is an n-type impurity (donor) It turns out that it has become. This is because the energy difference between the donor level of nitrogen, which is an n-type impurity (donor), and the lower end of the conduction band of silicon carbide is 0.09 eV, while that of aluminum, which is a p-type impurity (acceptor). This is because the energy difference between the acceptor level and the upper end of the valence band of silicon carbide is 0.19 eV. That is, the acceptor level of aluminum, which is a p-type impurity (acceptor), is deeper than the donor level of nitrogen, which is an n-type impurity (donor), and activates the p-type impurity (acceptor) The energy for the activation is greater than the energy for activating the n-type impurity (donor).

  This means that the energy for the electrons present in the valence band of silicon carbide to be trapped in the acceptor level of the p-type impurity (acceptor) is from the donor level of the n-type impurity (donor) to the conduction band of silicon carbide It means that it will be greater than the energy reached by. Thereby, as shown in FIG. 2, while the activation ratio of nitrogen which is an n-type impurity (donor) tends to be saturated at a relatively low temperature, activation of aluminum which is a p-type impurity (acceptor) is shown. The rate tends to be less likely to saturate to relatively high temperatures.

  At this time, as the temperature dependency of the activation rate increases, the difference between the resistance value at low temperature and the resistance value at high temperature increases. From this, the fluctuation range of the resistance value of the p-type diffused resistor element becomes larger than the fluctuation range of the resistance value of the n-type diffused resistor element with respect to the temperature change.

  From the above, both the n-type diffused resistance element and the p-type diffused resistance element satisfy the requirement for embodying the first basic concept in the present embodiment described above in that they have negative temperature characteristics. . However, from the viewpoint of realizing the first basic concept in the present embodiment described above, it is desirable that the adjustment range of the resistance value be larger. Therefore, in the present embodiment, for example, as the resistance element R2 shown in FIG. A p-type diffused resistive element is adopted.

Figure 3 is the acceptor concentration (N _A) in the silicon carbide was introduced aluminum 3 × 10 ¹⁷ cm ^-3 p-type diffused resistor element is a graph showing the relationship between temperature and the sheet resistance. In FIG. 3, it can be seen that the sheet resistance of the p-type diffused resistor decreases as the temperature rises. That is, it is understood that the p-type diffusion resistance element in which aluminum is introduced into silicon carbide has negative temperature characteristics. Specifically, as shown in FIG. 3, the sheet resistance is 140 kΩ ^□ at a temperature of about 40 ° C., while the sheet resistance is significantly reduced to 30 kΩ ^□ at a temperature of about 300 ° C. Know that

<First Feature Point in Embodiment>
Summarizing the above, the first feature point in the present embodiment is the temperature dependency of “V _BE3 ” shown in the first term of the above-mentioned formula (1) to the second term of the formula (2) In order to embody the first basic idea in the present embodiment of canceling by the temperature dependency of “(kT / q) × (r2 / r1) × ln (K)” shown, for example, in FIG. It is in the point which comprises resistive element R2 shown from a resistive element which has a negative temperature characteristic. Specifically, the first feature point in the present embodiment is that, for example, resistance element R2 shown in FIG. 1 is formed of a p-type diffused resistance element formed of a p-type semiconductor region in which aluminum is introduced into silicon carbide. . As a result, the first basic idea of the present embodiment described above is embodied, and according to the present embodiment, the temperature dependency of the output voltage Vref from the reference voltage generation circuit can be reduced.

  The semiconductor device in the present embodiment includes a semiconductor chip which is mainly composed of silicon carbide and on which a reference voltage generation circuit is formed. At this time, the reference voltage generation circuit includes a resistance element and a diode, and the resistance element is formed of a diffusion resistance element into which an acceptor is introduced.

<Considerations for Diodes>
Next, the diodes Q1 to Q3 shown in FIG. 1 are formed of, for example, npn bipolar transistors in which an n-type collector into which a donor is introduced and a p-type base into which an acceptor is introduced are shorted. At this time, the p-type base of the npn-type bipolar transistor is formed of the diffusion region formed in the silicon carbide substrate. That is, each of the diodes Q1 to Q3 shown in FIG. 1 also has a p-type base formed of a diffusion region of the same conductivity type as the above-described p-type diffusion resistor element. Here, for example, the acceptor introduced in the p-type diffusion resistance element and the acceptor introduced in the p-type base are elements of the same type. Specifically, the acceptor introduced into the p-type diffusion resistance element is aluminum, and the acceptor introduced into the p-type base is also aluminum.

  Therefore, also in the p-type base of diodes Q1 to Q3 shown in FIG. 1, the temperature dependency of the activation ratio of aluminum which is a p-type impurity (acceptor) becomes large as in the p-type diffusion resistance element (see FIG. ). And, the IV characteristics (current-voltage characteristics) of the diode using silicon carbide use silicon (silicon) due to the temperature dependency of the activation rate of the p-type impurity (acceptor) becoming large. This is different from the IV characteristics of the diode. Below, this point is explained.

  FIG. 4 is a graph schematically showing an IV characteristic of a diode using silicon. In FIG. 4, the horizontal axis indicates the cathode voltage, and the vertical axis indicates the anode current. As shown in FIG. 4, in the IV characteristic of a diode using silicon, the higher the temperature, the lower the rising voltage (forward voltage) at which the anode current rises, while the slope of the anode current after the rising voltage is The smaller the temperature, the smaller.

  On the other hand, FIG. 5 is a graph schematically showing an IV characteristic of a diode using silicon carbide. In FIG. 5, the horizontal axis indicates the cathode voltage, and the vertical axis indicates the anode current. As shown in FIG. 5, in the IV characteristic of a diode using silicon carbide, the higher the temperature, the lower the rising voltage (forward voltage) at which the anode current rises, while the slope of the anode current after the rising voltage is Unlike the silicon-based diode, the higher the temperature, the larger it becomes. This is because in the p-type base of a diode using an npn-type bipolar transistor, as the temperature rises, the activation rate of the p-type impurity (acceptor) increases, so injection of minority carriers is promoted, and the electrical resistance decreases. It is thought that it is because it became. Thus, the IV characteristics of the diode using silicon carbide are silicon due to the temperature dependency of the activation rate of the p-type impurity (acceptor) introduced in the diffusion region constituting the p-type base. And the I-V characteristics of the diode using the

Thus, the temperature dependency of the forward voltage of the diode using silicon carbide is different from the temperature dependency of the forward voltage of the diode using silicon. Specifically, FIG. 6 is a graph showing the temperature dependency of the forward voltage of a diode using silicon carbide when the load current is 1 μA. In FIG. 6, the horizontal axis indicates the temperature, and the vertical axis indicates the forward voltage VF. As shown in FIG. 6, the temperature coefficient of forward voltage in a diode using silicon carbide is -3.7 mV / ° C, and the temperature coefficient of forward voltage in a diode using silicon is -1.5 mV / Compared to ° C to -2.0 mV / ° C, it is about twice as large. At this time, the fact that the temperature coefficient of the forward voltage increases means that the temperature dependency of the base-emitter voltage “V _BE3 ” in the equation (1) becomes large. Then, the fact that the temperature dependency of the base-emitter voltage "V _BE3 " in the equation (1) becomes large means the temperature dependency of the "V _BE3 " shown in the first term of the equation (1) The resistance value "r2" of the resistance element R2 in the first basic concept of canceling by the temperature dependence of "(kT / q) x (r2 / r1) x ln (K)" shown in the second term of 2) It means that it is necessary to increase the temperature dependence of. This means that the fluctuation range of the resistance value "r2" of the resistance element R2 becomes large, and that the fluctuation range of the resistance value "r2" of the resistance element R2 becomes large, the size of the resistance element R2 becomes large It means that the need to be born is born. This leads to an increase in the size of the semiconductor chip that forms the reference voltage generation circuit, resulting in an increase in manufacturing cost. Therefore, in the present embodiment, a device for reducing the temperature coefficient of the forward voltage in a diode using silicon carbide is further provided.

<Second Basic Idea in the Embodiment>
The second basic idea in the present embodiment is the idea of utilizing the fact that the forward voltage increases or decreases depending on the current density in order to reduce the temperature coefficient of the forward voltage in a diode using silicon carbide. That is, since the temperature coefficient of the forward voltage in the diode using silicon carbide is "negative", the forward voltage at low temperature is relatively high while the forward voltage at high temperature is relatively low. . On the other hand, the forward voltage in the diode using silicon carbide is relatively small when the current flowing through the diode is small, and relatively large when the current flowing through the diode is large. Therefore, the second basic concept in the present embodiment is to lower the forward voltage at low temperature by decreasing the current flowing through the diode using silicon carbide at low temperature, while carbonizing at high temperature The idea is to shift the forward voltage at high temperature in the direction of increasing by increasing the current flowing through the diode using silicon. According to the second basic concept of the present embodiment, the temperature coefficient of the forward voltage in the diode using silicon carbide can be reduced (the slope is made smooth).

  By adopting the second basic concept in the present embodiment, the need to increase the temperature dependency of the resistance value “r2” of the resistance element R2 is reduced, and thereby, the resistance element R2 The need to increase the size of will be reduced. As a result, adopting the second basic concept in the present embodiment leads to suppression of the increase in size of the semiconductor chip forming the reference voltage generation circuit, which leads to the manufacture of a semiconductor device including the reference voltage generation circuit. It is possible to reduce costs.

<Second Feature Point in Embodiment>
Subsequently, a second feature point embodying the second basic concept in the above-described embodiment will be described. A second feature of the present embodiment is that, for example, not only the resistive element R2 shown in FIG. 1 but also the resistive element R1 shown in FIG. 1 is composed of a resistive element having negative temperature characteristics. Specifically, the second feature of the present embodiment is that, for example, resistance element R1 shown in FIG. 1 is formed of a p-type diffused resistance element formed of a p-type semiconductor region in which aluminum is introduced into silicon carbide. .

  Here, according to the above-mentioned equation (2), the load current is in inverse proportion to the resistance value “r1” of the resistance element R1. And in this embodiment, resistive element R1 is constituted from a resistive element which has a negative temperature characteristic. As a result, the load current at a low temperature relatively decreases because the resistance value "r1" of the resistance element R1 increases. On the other hand, the load current at high temperature relatively increases because the resistance value “r1” of the resistance element R1 decreases. In this way, automatically, at low temperature, by decreasing the current flowing to the diode using silicon carbide, the forward voltage at low temperature is shifted downward, while at high temperature, silicon carbide is used. The second basic idea of increasing the forward voltage at high temperature can be realized by increasing the current flowing through the diode. As a result, according to the second feature point in the present embodiment, the increase in size of the semiconductor chip forming the reference voltage generation circuit can be suppressed, which means that the manufacturing cost of the semiconductor device including the reference voltage generation circuit can be reduced. It will be possible to reduce.

  Specifically, FIG. 7 is a graph showing the relationship between temperature and load current when resistance element R1 shown in FIG. 1 is formed of a p-type diffused resistance element consisting of a p-type semiconductor region in which aluminum is introduced into silicon carbide. It is. In FIG. 7, the horizontal axis indicates the temperature, and the vertical axis indicates the load current. As shown in FIG. 7, the load current value at room temperature (25.degree. C.) can be obtained by configuring the resistive element R1 shown in FIG. 1 from a p-type diffused resistive element consisting of a p-type semiconductor region in which aluminum is On the other hand, it is understood that the load current value at 500 ° C. increases by 24 times. In this way, at low temperature, the forward voltage at low temperature is shifted downward by reducing the current flowing to the diode using silicon carbide, while at high temperature, the current flowing to the diode using silicon carbide It can be understood that the second basic idea of increasing the forward voltage at high temperature can be realized by increasing the value of.

  Specifically, FIG. 8 is a graph showing the relationship between the temperature and the forward voltage VF when the load current is controlled to be constant, and the temperature and the forward voltage when the load current is changed as shown in FIG. It is a figure which shows the graph which shows a relationship with VF. In FIG. 8, the horizontal axis indicates the temperature, and the vertical axis indicates the forward voltage VF. As shown in FIG. 8, the temperature coefficient when the load current is constant (1 μA) is −3.7 mV / ° C., whereas the temperature coefficient when the load current is changed as shown in FIG. 7 Is −3.0 mV / ° C., and it can be seen that it becomes gentle.

<Novelty of Second Basic Thought>
As described above, the second basic idea in this embodiment is the idea of utilizing the fact that the forward voltage increases or decreases depending on the current density in order to reduce the temperature coefficient of the forward voltage in the diode using silicon carbide. is there.

  The forward voltage of the diode not only has temperature dependence but also current density dependence. In this regard, the conventional reference voltage generation circuit is designed to control the load current to be constant. The reason is that only the temperature dependency of the forward voltage of the diode is revealed. However, in a diode using silicon carbide, if the load current is controlled to be constant, as shown in FIG. 6, the slope of the temperature coefficient of the forward voltage becomes large. Therefore, in the present embodiment, in order to make the slope of the temperature coefficient of the forward voltage smooth, it is used that the forward voltage is increased or decreased depending on the current density. Specifically, in the present embodiment, the forward voltage at low temperature is shifted to lower the forward voltage by reducing the current flowing to the diode using silicon carbide at low temperature, while silicon carbide is used at high temperature. By increasing the current flowing through the diode, the forward voltage at high temperature is shifted upward. As described above, in the present embodiment, the load current is not controlled to be constant, but the load current is relatively decreased at low temperature and is relatively increased at high temperature. Vary the load current. In this respect, the technical idea in the present embodiment is novel with respect to the prior art on the premise that the load current is controlled to be constant. Then, as a means to embody the second basic concept in the present embodiment, for example, a p-type diffused resistor element comprising a p-type semiconductor region in which aluminum is introduced into silicon carbide as resistor element R1 shown in FIG. It consists of As a result, due to the p-type diffused resistive element having negative temperature characteristics, the load current at a low temperature automatically has a relatively large resistance value "r1" of the resistive element R1. It becomes smaller from that. On the other hand, the load current at high temperature relatively increases because the resistance value “r1” of the resistance element R1 decreases. In this manner, by adopting the second feature point in the present embodiment, the forward voltage at low temperature is automatically reduced at low temperature by reducing the current flowing to the diode using silicon carbide. While shifting in the direction, at high temperature, the second basic idea of increasing the forward voltage at high temperature can be realized by increasing the current flowing to the diode using silicon carbide. That is, in the present embodiment, the load current is increased or decreased by simply forming the resistance element R1 shown in FIG. 1 from the p-type diffusion resistance element formed of the p-type semiconductor region in which aluminum is introduced into silicon carbide. There is no need to provide a large control circuit to control the That is, according to the second feature point in the present embodiment that the resistance element R1 shown in FIG. 1 is formed of a p-type diffusion resistance element consisting of a p-type semiconductor region in which aluminum is introduced into silicon carbide It can be seen that the technical concept is useful in that the second basic concept in the present embodiment can be realized without providing a large-scale control circuit for controlling the increase and decrease of

<Effect of Embodiment>
Next, the effects of the present embodiment will be described. FIG. 9 is a graph showing, for example, the temperature dependency of the output voltage Vref output from the output terminal OT of the reference voltage generation circuit shown in FIG. In FIG. 9, the horizontal axis indicates the temperature, and the vertical axis indicates the output voltage Vref. As shown in FIG. 9, by adopting a first feature that embodies the first basic idea in the present embodiment and a second feature that embodies the second basic idea in the present embodiment, For example, it is understood that the temperature dependency of the output voltage Vref output from the reference voltage generation circuit shown in FIG. 1 can be reduced.

<Device structure>
Subsequently, the device structure of the semiconductor device in the present embodiment will be described. FIG. 10 is a cross-sectional view for explaining the device structure of the semiconductor device in the present embodiment. In FIG. 10, the device structure of the resistance element R1 and the resistance element R2 which are components of the reference voltage generation circuit shown in FIG. 1 is illustrated in the area A1. On the other hand, in the region A2, the device structure of the diodes Q1 to Q3 which are components of the reference voltage generation circuit shown in FIG. 1 is illustrated.

  First, the device structure of the p-type diffused resistor element formed in the region A1 of FIG. 10 will be described. As shown in FIG. 10, an n-type silicon carbide substrate 1S, a p-type semiconductor layer PSL provided on the n-type silicon carbide substrate 1S, and a p-type semiconductor layer PSL are provided in the region A1 of the semiconductor chip. An n-type semiconductor layer EPI is formed. A back surface electrode BE is formed on the back surface (bottom surface) of the n-type silicon carbide substrate 1S. On the other hand, in the n-type semiconductor layer EPI, a p-type semiconductor region PR1 included in the n-type semiconductor layer EPI is formed, and this p-type semiconductor region PR1 functions as a p-type diffused resistance element. Furthermore, the interlayer insulating film IL is formed over the surface of the n-type semiconductor layer EPI and the surface of the p-type semiconductor region PR1. In the interlayer insulating film IL, an opening OP1 and an opening OP2 that expose the surface of the p-type semiconductor region PR1 are formed through the interlayer insulating film IL. A wire WL1 and a wire WL2 are formed to be electrically connected to the p-type semiconductor region PR1 and to extend over the interlayer insulating film IL from within the opening OP1. As described above, the p-type diffused resistor element is formed in the region A1 of the semiconductor chip.

  Subsequently, the device structure of the diode formed in the region A2 of FIG. 10 will be described. As shown in FIG. 10, an n-type silicon carbide substrate 1S, a p-type semiconductor layer PSL provided on the n-type silicon carbide substrate 1S, and a p-type semiconductor layer PSL are provided in the region A2 of the semiconductor chip. An n-type semiconductor layer EPI to be an n-type collector is formed. A back surface electrode BE is formed on the back surface (bottom surface) of the n-type silicon carbide substrate 1S. On the other hand, in the n-type semiconductor layer EPI, a trench TR which reaches the p-type semiconductor layer PSL is formed penetrating the n-type semiconductor layer EPI. Inside the trench TR, for example, a p-type semiconductor layer is used. Embedded layer BSL is embedded. Then, in a plan view, the n-type semiconductor layer EPI is surrounded by the embedded layer BSL embedded in the trench TR. At this time, in the n-type semiconductor layer EPI surrounded by the buried layer BSL, the p-type semiconductor region PR2 as a p-type base and the n-type emitter included in the p-type semiconductor region PR2 in plan view The semiconductor region NR2 is formed. Furthermore, over the n-type semiconductor layer EPI in which the buried layer BSL embedded in the trench TR, the p-type semiconductor region PR2, and the n-type semiconductor region NR2 are formed, the interlayer insulating film IL is formed. Here, in the interlayer insulating film IL, the opening OP3 penetrating the interlayer insulating film IL and exposing the surface of the n-type semiconductor region NR2 and the p-type semiconductor region PR2 penetrating the interlayer insulating film IL An opening OP4 that exposes the surface of the semiconductor device and an opening OP5 that penetrates the interlayer insulating film IL and exposes the surface of the n-type semiconductor layer EPI are formed. Then, the wiring WL3 is formed to be electrically connected to the n-type semiconductor region NR2 and to extend from the opening OP3 to over the interlayer insulating film IL. Similarly, it is electrically connected to p-type semiconductor region PR2, extends from opening OP4 to over interlayer insulating film IL, and is electrically connected to n-type semiconductor layer EPI2, and from opening OP5 to the interlayer insulating film A wire WL4 extending over IL is formed. Thus, in the region A2 of FIG. 10, the n-type semiconductor layer EPI is an n-type collector, the p-type semiconductor region PR2 is a p-type base, and the n-type semiconductor region NR2 is an n-type emitter. A diode having a configuration in which the p-type base and the n-type collector of the npn bipolar transistor are short-circuited is formed.

  The diode formed in the region A2 of FIG. 10 is separated from the n-type silicon carbide substrate 1S to which the power supply potential is applied by the buried layer BSL and the p-type semiconductor layer PSL. Therefore, since the potential of the n-type semiconductor layer EPI of the diode formed in the region A2 of FIG. 10 can be set to an arbitrary potential, the device structure of the diode formed in the region A2 of FIG. The diodes Q1 to Q3 of the reference voltage generation circuit shown in FIG.

<Modification 1>
FIG. 11 is a diagram showing a circuit configuration of a reference voltage generation circuit according to the first modification. In FIG. 11, the anodes of the diodes Q1 to Q3 are electrically connected to a power supply line VL to which a power supply potential is supplied. In the reference voltage generation circuit configured as described above, an output voltage of negative bias can be output from the output terminal OT.

  Here, FIG. 12 is a cross-sectional view for explaining the device structure of the semiconductor device according to the first modification. In FIG. 12, in the region A1, the device structure of the resistance element R1 and the resistance element R2 which are components of the reference voltage generation circuit shown in FIG. 11 is illustrated. On the other hand, in the region A2, the device structure of the diodes Q1 to Q3 which are components of the reference voltage generation circuit shown in FIG. 11 is illustrated. In FIG. 12, an n-type semiconductor layer EPI is formed on an n-type silicon carbide substrate 1S, and a p-type semiconductor region PR2 is formed so as to be included in the n-type semiconductor layer EPI. An n-type semiconductor region NR2 is formed to be included in the p-type semiconductor region PR2. Unlike the diode formed in region A2 of FIG. 10, the diode formed in region A2 of FIG. 12 is not separated from n-type silicon carbide substrate 1S. This is because the power supply potential is applied to n-type silicon carbide substrate 1S, and the power supply potential is also supplied to the anode of the diode that is a component of the reference voltage generation circuit shown in FIG. This is because it is not necessary to separate the n-type semiconductor layer EPI and the n-type silicon carbide substrate 1S, which become the This simplifies the device structure of the diode in the first modification.

<Modification 2>
FIG. 13 is a cross-sectional view for explaining the device structure of the semiconductor device in the second modification. In FIG. 13, in the area A1, the device structure of the resistive element R1 and the resistive element R2 which are components of the reference voltage generation circuit shown in FIG. 1 is illustrated. On the other hand, in the region A2, the device structure of the diodes Q1 to Q3 which are components of the reference voltage generation circuit shown in FIG. 1 is illustrated. In FIG. 13, unlike in FIG. 10, the insulating layer OXL is embedded in the trench TR. For example, in the device structure shown in FIG. 10, a parasitic pnp type bipolar device having ap type semiconductor region PR2 as ap type emitter, an n type semiconductor layer EPI as an n type base and a buried layer BSL as an n type collector. A transistor is formed. On the other hand, in the device structure shown in FIG. 13, since the layer embedded in the trench TR is not the buried layer (p-type semiconductor layer) BSL but the insulating layer OXL, no parasitic pnp bipolar transistor is formed. As a result, according to the semiconductor device in the second modification, false firing due to the parasitic pnp type bipolar transistor can be prevented, whereby the reliability of the semiconductor device can be improved.

  The technical idea of the present modification 2 of preventing the formation of the parasitic pnp type bipolar transistor by burying the insulating layer OXL in the inside of the trench TR is not limited to this, and, for example, as shown in FIG. The insulating film OXF may be formed on the inner wall of the trench TR, and the buried layer BSL may be embedded inside the trench TR via the insulating film OXF. Further, for example, as shown in FIG. 15, in the device structure shown in FIG. 14, the formation of the parasitic pnp type bipolar transistor is prevented even in the configuration where the insulating film OXF formed at the bottom of the trench TR is removed. The technical idea of the present modification 2 can be embodied.

  As mentioned above, although the invention made by the present inventor was concretely explained based on the embodiment, the present invention is not limited to the embodiment, and can be variously changed in the range which does not deviate from the summary. Needless to say.

  For example, in the reference voltage generation circuit shown in FIG. 1, a configuration example is shown in which an n-type current mirror circuit and a p-type current mirror circuit are connected in series, but the technical idea in the embodiment is not limited to this. The present invention can also be applied to a reference voltage generation circuit using an operational amplifier. Further, although the reference voltage generation circuit has been described in the above embodiment, the technical idea in the above embodiment can be applied to a reference current generation circuit operating according to the same principle.

  In the above embodiment, a diode having a configuration in which a p-type base and an n-type collector of an npn bipolar transistor are short-circuited is taken as an example, but the technical idea in the above embodiment is not limited to this. Can also be applied to various pn junction diodes. However, the advantage of adopting a diode having a configuration in which the p-type base and n-type collector of an npn bipolar transistor are short-circuited is that all terminals (anode terminal and Since the cathode terminal can be taken out, an advantage can be obtained that the mounting configuration of the semiconductor device is easy.

1S n-type silicon carbide substrate BE back surface electrode BSL buried layer EPI n-type semiconductor layer M1 field effect transistor M2 field effect transistor M3 field effect transistor M4 field effect transistor M5 field effect transistor NR2 n type semiconductor region PR1 p type semiconductor region PR2 p type Semiconductor region PSL p-type semiconductor layer Q1 diode Q2 diode Q3 diode R1 resistive element R2 resistive element TR trench

Claims (15)

A semiconductor chip mainly composed of silicon carbide and having a reference voltage generation circuit formed thereon;
The reference voltage generation circuit includes a resistive element and a diode,
The semiconductor device, wherein the resistance element is a diffusion resistance element into which an acceptor is introduced. In the semiconductor device according to claim 1,
The semiconductor device, wherein the diode is an npn bipolar transistor in which an n-type collector into which a donor is introduced and a p-type base into which an acceptor is introduced are shorted. In the semiconductor device according to claim 2,
The semiconductor device, wherein the acceptor introduced into the diffusion resistance element and the acceptor introduced into the p-type base are elements of the same type. In the semiconductor device according to claim 3,
The acceptor introduced into the diffusion resistance element is aluminum,
The semiconductor device, wherein the acceptor introduced into the p-type base is also aluminum. In the semiconductor device according to claim 2,
A semiconductor in which the energy difference between the acceptor level of the acceptor and the top of the valence band of the silicon carbide is greater than the energy difference between the donor level of the donor and the bottom of the conduction band of the silicon carbide apparatus. In the semiconductor device according to claim 2,
The semiconductor device, wherein the donor is nitrogen. In the semiconductor device according to claim 2,
The semiconductor device, wherein the activation rate of the acceptor is smaller than the activation rate of the donor. In the semiconductor device according to claim 2,
The semiconductor device, wherein the temperature dependence of the activation rate of the acceptor is larger than the temperature dependence of the activation rate of the donor. In the semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein a load current in the reference voltage generation circuit is a first current value at room temperature, and is 20 times or more of the first current value at 500 ° C. In the semiconductor device according to claim 1,
The semiconductor device, wherein the diffusion resistance element has negative temperature dependency. In the semiconductor device according to claim 1,
The cathode of the diode is connected to a ground line to which a reference potential is supplied. In the semiconductor device according to claim 1,
A semiconductor device, wherein an anode of the diode is connected to a power supply line to which a power supply potential is supplied. In the semiconductor device according to claim 2,
The semiconductor chip is
n-type silicon carbide substrate,
A p-type semiconductor layer formed on the n-type silicon carbide substrate;
An n-type semiconductor layer formed on the p-type semiconductor layer and serving as the n-type collector;
A trench penetrating the n-type semiconductor layer to reach the p-type semiconductor layer;
A buried layer embedded inside the trench;
Have
In plan view, the n-type semiconductor layer is surrounded by the buried layer,
In the n-type semiconductor layer surrounded by the buried layer,
A p-type semiconductor region to be the p-type base;
An n-type semiconductor region included in the p-type semiconductor region in plan view and serving as an n-type emitter;
A semiconductor device to be formed. In the semiconductor device according to claim 13,
The semiconductor device, wherein the buried layer is composed of a p-type buried semiconductor layer. In the semiconductor device according to claim 13,
The semiconductor device, wherein the embedded layer is composed of an insulating layer.

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