JP2019088185A - Dc motor drive circuit, drive method, and electronic device using the same - Google Patents

Abstract

To reduce power consumption.SOLUTION: An error detector 310 is a position error value ERR corresponding to a difference between a position command value P_REF indicating the target position of a rotor based on a clock signal CLK and a position detection value P_FB indicating the current position of the rotor based on the pulse signals EN_A and EN_B from the encoder. A feedback controller 330 generates a torque command value T_REF such that the position error value ERR approaches zero. A drive IC 200D can perform switching between the rotation control mode and the holding mode, and the control characteristic of the feedback controller 330 is switched between the rotation control mode and the holding mode.SELECTED DRAWING: Figure 7

Description

  The present invention relates to a drive circuit of a DC motor.

  A stepping motor is used to position the control target. A clock signal (pulse rate signal) is used to control the stepping motor, and the motor can be rotated in an open loop in proportion to the number of pulses of the input clock signal, and when the clock signal is stopped, The motor can be stationary. Because of such ease of control, stepping motors are often used in office automation equipment such as printers, facsimiles, scanners, multifunction machines, etc., or in industrial equipment.

  However, the stepping motor has a problem that power consumption increases because the coil continues to be energized even in the stationary state. In recent years, low power consumption has been required in various applications including OA equipment, but the power consumption of a stepping motor is one factor that hinders the reduction in power consumption of the OA equipment.

  The brushless DC motor is characterized in that control is complicated but power consumption is small. Therefore, from now on, in applications where low power consumption is required, it is required to replace the stepping motor with a DC motor.

  FIG. 1 is a block diagram of a motor drive system provided with a DC motor. In this motor drive system, the DC motor is controlled by a control interface using a clock signal as in the case of a conventional stepping motor. The motor drive system 100R includes a DC motor 102, a host controller 104, a driver 106, and a motor control device 800. The upper controller 104 is, for example, a microcomputer or a CPU (Central Processing Unit), and generates a clock signal CK that indicates the position of the rotor of the DC motor 102. The motor control device 800 is also constituted by a CPU and a microcomputer, and converts the clock signal into a PWM signal adapted to drive of the DC motor by software control. The driver 106 includes a three-phase inverter and drives the DC motor 102 based on the PWM signal. Such a system is described, for example, in Patent Document 1.

Patent No. 5487910

Problem 1.
Since the CPU and the microcomputer are expensive, if the motor control device 800 for controlling the DC motor is configured by the CPU and the microcomputer, there is a problem that the cost of the device becomes high.

  In addition, the designer of the motor drive system 100R needs to create a software program to be executed by the motor control device 800 in consideration of the specification of the clock signal CK, the characteristics of the DC motor 102 to be driven, etc. It causes the problem of soaring prices and prolonging the development period.

Problem 2.
In many applications, a period for rotating the stepping motor and a period for stopping the rotation (holding operation) occur alternately. In the situation where there is no external force, it is possible to stop the DC motor by stopping the power supply to the DC motor, but in the situation where the external force is applied, it is necessary to generate a torque that balances the external force with the external force.

  An embodiment of the present invention is to provide a drive circuit capable of solving the problems 1 and / or 2.

1. One embodiment of the present invention relates to a drive circuit of a DC motor. The drive circuit is composed of a logic circuit, receives the clock signal from the host controller and the pulse signal from the encoder, and is the difference between the current position of the rotor based on the pulse signal and the target position of the rotor based on the clock signal. An error detector that generates a position error value, a feedback controller that generates a command value such that the position error value approaches zero, and a logic circuit that is configured by a logic circuit, and a drive signal that corresponds to the command value And a drive signal generation unit to be generated, and integrated on one semiconductor substrate.

2. One embodiment of the present invention relates to a drive circuit of a DC motor. The drive circuit drives the DC motor according to the clock signal from the host controller and the pulse signal from the encoder. An error detector that generates a position error value according to a difference between a position command value indicating a target position of the rotor based on the clock signal and a position detection value indicating the current position of the rotor based on the pulse signal; A feedback controller that generates a torque command value so that the error value approaches zero, and a drive signal generation unit that generates a drive signal according to the torque command value. The drive circuit can switch between the rotation control mode and the holding mode, and the control characteristic of the feedback controller is switched between the rotation control mode and the holding mode.

  It is to be noted that any combination of the above-described constituent elements, or one in which the constituent elements and expressions of the present invention are mutually replaced among methods, apparatuses, systems, etc. is also effective as an aspect of the present invention.

  According to an aspect of the present invention, the stepping motor can be replaced with a DC motor inexpensively. According to another aspect, it is possible to stop the DC motor without impairing the response during the rotation operation.

1 is a block diagram of a motor drive system including a DC motor. It is a block diagram of a motor drive system provided with drive IC concerning an embodiment. It is a block diagram which shows the structure of drive IC. It is a block diagram which shows the basic composition of a logic circuit. It is a figure explaining operation of an error detector. FIGS. 6A to 6C are block diagrams showing configuration examples of the position command value generation unit. FIG. 7 is a block diagram of a drive IC that supports switching between rotation control mode and holding mode. It is a block diagram showing an example of composition of drive IC. It is a time chart explaining transition of a mode of drive IC of FIG. FIG. 16 is a block diagram of a portion of a drive IC according to a fourth modification. FIG. 6 is a block diagram of a portion of a drive IC that supports sleep mode. It is a figure explaining transition to the rest mode of drive IC of FIG. It is a block diagram of a part of drive IC provided with a short brake function. It is a block diagram of a brake controller. Fig.15 (a), (b) is a figure explaining operation | movement of a brake controller. It is a waveform diagram of the frequency _{f CK} of the clock signal CLK. It is a figure which shows the rotation speed of the motor at the time of starting of a motor drive system. It is a figure explaining the function of an electronic gear. It is a block diagram of drive IC provided with the function of an electronic gear. It is a block diagram of drive IC provided with the function of an electronic gear. It is a figure showing electronic equipment provided with a motor drive system.

(Summary of Embodiment 1)
One embodiment disclosed herein relates to a motor drive circuit (drive IC). The motor drive IC comprises a logic circuit, receives a clock signal from the host controller and a pulse signal from the encoder, and a difference between the current position of the rotor based on the pulse signal and the target position of the rotor based on the clock signal. An error detector that generates a position error value, and a feedback controller that is configured with a logic circuit and that generates a command value such that the position error value approaches zero, and a drive signal according to the command value And a drive signal generation unit for generating the signal, which is integrated on one semiconductor substrate.

  By using this drive IC, a microcomputer, a CPU, etc. become unnecessary, the stepping motor can be replaced with a DC motor at low cost, and the power consumption of the system can be reduced.

  The feedback controller may include a PI (proportional integration) controller. The control characteristics of the PI controller may change dynamically according to the frequency of the clock signal. Thereby, followability can be improved.

  The integral gain of the PI controller is constant, and the proportional gain may change according to the frequency of the clock signal. By making the integral gain constant, vibration of the rotational speed can be suppressed.

  The error detector generates a target value according to an integrated value of the number of edges of the clock signal, and a position detection value generator that generates a feedback value indicating the current position of the rotor based on the pulse signal. And a subtractor that generates a difference between the target value and the feedback value.

  The position command value generation unit may be capable of selecting the amount of change of the target value per edge of the clock signal from a plurality of values. Thereby, an electronic gear can be realized.

  The position detection value generation unit may be capable of selecting the amount of change in feedback value per pulse signal from a plurality of values. Thereby, an electronic gear can be realized.

  The drive IC may further include a setting pin for specifying the amount of change in the target value or the feedback value.

  The drive IC may further include a predriver that controls an inverter that drives the DC motor.

(Summary of Embodiment 2)
One embodiment disclosed herein relates to a motor drive circuit. The motor drive circuit drives the DC motor according to the clock signal from the host controller and the pulse signal from the encoder.
An error detector that generates a position error value according to a difference between a position command value indicating a target position of the rotor based on the clock signal and a position detection value indicating the current position of the rotor based on the pulse signal; A feedback controller that generates a torque command value so that the error value approaches zero, and a drive signal generation unit that generates a drive signal according to the torque command value. The drive circuit can switch between the rotation control mode and the holding mode, and the control characteristic (control parameter) of the feedback controller is switched between the rotation control mode and the holding mode.

  In the rotation control mode, a control parameter that emphasizes the followability to the rotation command based on the clock signal is given, and in the hold mode, a control parameter that emphasizes stability, not the followability, gives the DC motor like a stepping motor. It becomes possible to drive.

  The feedback controller may include a PI (Proportional Integral) controller. At least one of the proportional gain and the integral gain may be different between the rotation control mode and the holding mode.

  If the mode is switched while the integral value remains, torque may continue to be generated until the integral value becomes zero, which may cause unnecessary vibration or a long delay until the control is stabilized. Therefore, when the rotation control mode and the holding mode are switched, by resetting the integral value to zero, unnecessary vibration can be suppressed or the stabilization time can be shortened.

  The drive circuit may further include a mode determination unit that determines the rotation control mode and the holding mode based on the input state of the clock signal. Since the non-input state of the clock signal is a motor stop instruction, the rotation control mode and the holding mode can be switched without requiring an additional control line.

  The mode determination unit may include a counter that measures the duration of the non-input state of the clock signal, and may shift from the rotation control mode to the hold mode when the non-input state of the clock signal continues for a predetermined time.

  The feedback controller may include a first controller associated with the rotational control mode and a second controller associated with the hold mode. By preparing two systems of controllers, seamless switching becomes possible.

  The feedback controller includes a single controller, and the gain may be changed in the rotation control mode and the hold mode.

  The drive signal generation unit generates a drive signal based on the pulse width modulator that generates a PWM (Pulse Width Modulation) signal having a duty ratio corresponding to the torque command value, and the PWM signal and the output of the hall comparator. And may be included.

  The drive circuit may further include a predriver that controls an inverter that drives the DC motor.

  The drive circuit may be integrated on one semiconductor substrate. "Integrated integration" includes the case where all of the circuit components are formed on a semiconductor substrate, and the case where the main components of the circuit are integrally integrated. A resistor, a capacitor or the like may be provided outside the semiconductor substrate. By integrating the circuit on one chip, the circuit area can be reduced and the characteristics of the circuit elements can be kept uniform.

Embodiment
Hereinafter, the present invention will be described based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and duplicating descriptions will be omitted as appropriate. In addition, the embodiments do not limit the invention and are merely examples, and all the features and combinations thereof described in the embodiments are not necessarily essential to the invention.

  In the present specification, "a state in which the member A is connected to the member B" means that the members A and B are physically directly connected, or the members A and B are electrically connected. It also includes the case of being indirectly connected through other members that do not affect the state or inhibit the function.

  Similarly, "a state in which the member C is provided between the member A and the member B" means that the member A and the member C, or the member B and the member C are directly connected, or the electric member It also includes the case of being indirectly connected through other members that do not affect the connection state or inhibit the function.

  FIG. 2 is a block diagram of a motor drive system 100 including a drive IC 200 according to the embodiment. The motor drive system 100 includes a DC motor 102, a host controller 104, a driver 106, hall sensors 110U to 110W, and an encoder 112 in addition to the drive IC 200. The name of each signal, the pin (terminal) to which it is input / output, and the wiring are given the same reference numerals. In the present embodiment, the drive target is a three-phase DC motor.

  The upper controller 104 is a microcomputer, a CPU, an application specified IC (ASIC), a field programmable gate array (FPGA) or the like, and generates a clock signal CLK indicative of a target position of the rotor of the DC motor 102 (hereinafter also referred to simply as the motor position). Generate The host controller 104 also generates a direction indication signal (CW_CCW signal) that indicates the rotational direction of the motor. These signals are input to corresponding pins CLK and CW_CC of the drive IC 200. For example, the low of the CW_CCW signal is a rotation instruction in a first direction (for example, clockwise), and the high is a rotation instruction in a second direction (for example, counterclockwise).

The driver 106 includes a three-phase inverter and a shunt resistor R _S. Output voltages VU to VW of respective phases of the three-phase inverter are input to feedback pins (U to W) of the drive IC 200. The shunt resistor R _S is provided on a path of current flowing to the three-phase inverter, and a voltage drop (detection voltage) proportional to the current occurs. The voltage drop (current detection signal) V _CL of the shunt resistor R _S is input to the RCL (overcurrent detection voltage input) pin of the drive IC 200. The current detection signal V _CL can be used, for example, for current limitation of pulse-by-pulse.

  The Hall sensors 110U to 110W generate three-phase Hall signals HUP, HUN, HVP, HVN, HWP, HWN according to the position of the rotor. These signals are input to corresponding pins of the drive IC 200.

The Hall sensor 110U～110W, Hall bias signal _{V HB} generated by the drive IC200 and an external transistor _{Q 1} and resistors _{R 11, R 12} are supplied.

  The encoder 112 generates pulse signals (A-phase pulse signal EN_A and B-phase pulse signal EN_B) indicating information (absolute position, relative position or displacement amount) regarding the position of the rotor. These pulse signals are input to corresponding pins of the drive IC 200.

  The drive IC 200 generates gate signals for controlling the driver 106 based on the CLK signal, the CW_CCW signal, the hall signals HUP to HWN, and the pulse signals EN_A and EN_B, and the UH, VH, WH, UL, VL, and WL pins. Output from

The high side transistor of the driver 106 is N-channel, and a voltage higher than the power supply voltage V _CC is required to drive the gate. The drive IC 200 incorporates a charge pump, and external capacitors are connected to the CP1, CP2 and VG pins.

  The drive IC 200 is configured by hardware, that is, a combination of logic circuits and analog circuits. In the present specification, “composed of a logic circuit” means an architecture such as a CPU and a microcomputer that does not require software control.

  The power supply (VCC) pin of the drive IC 200 is supplied with a power supply voltage, and the ground (GND) pin is grounded.

  FIG. 3 is a block diagram showing the configuration of the drive IC 200. As shown in FIG. The drive IC 200 includes a plurality of input buffers BUF1 to BUF4, hole comparators HMPPU to HCMPW, a logic circuit 300, a predriver 250, a power supply circuit group 260, and a protection circuit 280.

  The plurality of input buffers BUF high and low binarize signals input to the corresponding pins, respectively. The U-phase Hall comparator HCMPU compares the same U-phase Hall signals HUP and HUN input to the HUP pin and the HUN pin. The same applies to the Hall comparators HHCMPV and HCMPW of the V phase and the W phase. The outputs of the input buffer BUF and the Hall comparator HCMP are input to the logic circuit 300.

The power supply circuit group 260 includes an operational amplifier 262 and a reference voltage source 264 which constitute a Hall bias circuit together with external parts (a transistor Q11 and resistors R ₁₁ and R _{12 in} FIG. 2). Hall bias voltage _VHB is stabilized at the following voltage levels.
V _HB = V _REF × (1 + R ₁₁ / R ₁₂ )

The charge pump 266 is connected with external capacitors (C ₁₁ and C _{12 in} FIG. 2) via the CP pin, the CN pin and the VG pin. The charge pump 266 is supplied with the power supply voltage V _CC as an input voltage. The charge pump 266 boosts the power supply voltage V _CC to generate the boosted high voltage V _G at the VG pin. The high voltage V _G is supplied to the pre-driver 250 is used to drive the subsequent stage of the high-side transistor (upper arm of the driver 106 FIG. 2).

The power supply circuit 268 generates a power supply voltage V _REGD (for example, 1.5 V) for the digital circuit and supplies it to the logic circuit 300. The power supply circuit 270 generates a power supply voltage V _REG (for example, 5 V) for an analog circuit and supplies it to the logic circuit 300 and the predriver 250.

Protection circuit 280 includes various protection circuits. A thermal shut down (TSD) circuit 282 detects an overheat condition. An under voltage lock out (UVLO) circuit 284 detects a low state of the power supply voltage V _CC . An OVLO (Over Voltage Lock Out) circuit 286 detects an overvoltage condition of the power supply voltage V _CC . The output (detection signal) of each circuit is input to the logic circuit 300 directly or indirectly via an OR gate.

The oscillator 288 generates a system clock CK _SYS and supplies it to the logic circuit 300.

The overcurrent detection circuit 290 is provided for overcurrent protection based on the detection voltage _VCL input to the RCL pin. An over current protection (OCP) comparator 292 compares the detection voltage V _CL with a threshold value V _TH, and asserts (eg, high) the OCP signal when V _CL > V _TH . The OCP signal is supplied to the logic circuit 300.

  The logic circuit 300 generates a drive signal of the driver (three-phase inverter) 106 connected to the rear stage of the drive IC 200 based on the outputs of the Hall comparator HCMP and the input buffer BUF. In addition, protection processing in each abnormal state is executed. For example, when the OCP signal is asserted, pulse-by-pulse overcurrent protection is applied. When an abnormality is detected in the protection circuit 280, the drive of the motor is stopped.

The pre-driver 250 drives the driver 106 at the rear stage based on the drive signal from the logic circuit 300 and the coil end voltages V _U , V _V and V _W of each phase fed back to the U, V and W pins. The coil end voltages V _U , V _V and V _W are used to generate low level of the gate signal of the high side transistor of the driver 106.

  The above is a block diagram of the drive IC 200. Subsequently, the configuration of the logic circuit 300 will be described.

  FIG. 4 is a block diagram showing a basic configuration of logic circuit 300. Referring to FIG. The logic circuit 300 mainly includes an error detector 310, a feedback controller 330, and a drive signal generator 340.

  The error detector 310 is a position error value that indicates an error between the target position and the current position of the rotor based on the difference between the pulse signals EN_A and EN_B from the encoder and the integrated value of the number of pulses of the clock signal CK from the host controller. Generate ERR.

  The error detector 310 includes a position command value generation unit 312, a position detection value generation unit 314, and a subtractor 316. The position command value generation unit 312 generates a target value TGT indicating a target position of the rotor based on the clock signal CLK and the CW_CCW signal. More specifically, position command value generation unit 312 generates an integrated value of the number of positive edges (and / or negative edges, hereinafter simply referred to as edges) of clock signal CLK.

  The position detection value generation unit 314 generates a feedback value FB indicating the current position of the rotor based on the pulse signals EN_A and EN_B from the encoder 112. The subtractor 316 generates a difference between the target value TGT and the feedback value FB.

  The feedback controller 330 generates the control command value REF such that the value of the position error value ERR approaches zero. For example, the feedback controller 330 can include a PI (Proportional Integral) controller. The control command value REF may be a torque command value of the motor.

  The drive signal generation unit 340 generates drive signals SUH, SUL, SVH, SVL, SWH, and SWL according to the command value REF. For example, the drive signal generator 340 includes a pulse width modulator 342 and a conduction logic 344. The pulse width modulator 342 generates a PWM (Pulse Width Modulation) signal having a duty ratio corresponding to the control command value REF.

  The energization logic 344 determines the direction of rotation based on the CW_CCW signal. The energization logic 344 switches the phase to be driven (drive phase) based on the hall comparators HMPPU to HCMPW (commutation control). The energization method is not particularly limited, but, for example, 120 degree energization control (rectangular wave drive) can be adopted. Besides, another method such as 180 degree conduction control (sine wave drive) may be adopted.

  The energization logic 344 modulates any one of the drive signals SUH, SUL, SVH, SVL, SWH and SWL according to the PWM signal. Although the method of PWM control is not limited, for example, the logic of the drive signals SUL, SVL, SWL on the low side may be fixed, and the logic of the drive signals SUH, SVH, SWH on the high side may be modulated based on the PWM signal. Conversely, the low side drive signal may be modulated, or both may be modulated.

  Energization logic 344 may apply pulse-by-pulse current limiting based on the OCP signal. Specifically, when the OCP signal is asserted, the drive signals SUH to SWH and SUL to SWL are changed such that the current-carrying transistors are turned off.

  The configurations of the pulse width modulator 342 and the energization logic 344 may be similar to those of the drive circuit of the conventional DC motor, and known techniques may be used.

  FIG. 5 is a diagram for explaining the operation of the error detector 310. In this example, the CW_CCW signal is low. Every time an edge of the clock signal CLK occurs, the target value TGT increases by one, and as a result, the position error value ERR increases by one. Further, the feedback value FB changes according to the combination of the pulse signals EN_A and EN_B, and as a result, the position error value ERR decreases or increases.

  FIGS. 6A to 6C are block diagrams showing configuration examples of the position command value generation unit 312. FIG. The position command value generation unit 312 of FIG. 6A includes an edge detection circuit 320 that detects an edge of the clock signal CLK, and a counter 322 that counts up / counts down for each edge. The CW_CCW signal that indicates the direction of rotation is used to select whether the counter 322 counts up or down. The output of the counter 322 is the target value TGT.

  The position command value generation unit 312 in FIG. 6B includes an arithmetic unit 324, a memory (register) 325, and an operation code selector 326. The operator 324 can switch at least the addition operation A + B and the subtraction operation AB in accordance with the operation code (OPECODE). The value (position error value ERR) of the memory 325 is input to the input A, and the fixed value 1 is input to the input B. Opcode selector 326 issues an opcode each time an edge of clock signal CLK is detected. The opcode is added when CW_CCW is at the first level, and subtracted when the CW_CCW signal is at the second level. Thus, a value obtained by integrating the number of edges of the clock signal CLK is stored in the memory 325, which represents the target value TGT.

  The position command value generation unit 312 of FIG. 6C includes a selector 327, an adder 328, and a memory 329. The values 1 and -1 are input to the selector 327, and one of the values according to the value of CW_CCW is selected. The adder 328 operates in accordance with the edge of the clock signal CLK, adds the output of the selector 327 and the value of the memory 329, and updates the value of the memory 329 with the addition result. Thus, a value obtained by integrating the number of edges of the clock signal CLK is stored in the memory 329, which represents the target value TGT.

  The above is the configuration of the logic circuit 300.

  By using the drive IC 200 according to the embodiment, the microcomputer and CPU (900 in FIG. 1) in the conventional system become unnecessary, so the stepping motor can be replaced with the DC motor at low cost, reducing the power consumption of the system. You can enjoy the benefits of

  Subsequently, further features of the drive IC 200 will be described.

(Rotation control mode and holding mode)
FIG. 7 is a block diagram of a drive IC 200D that supports switching between the rotation control mode and the holding mode.

  The drive IC 200D includes a mode determination unit 470 in addition to the error detector 310, the feedback controller 330, and the drive signal generation unit 340. The basic functions and operations of the error detector 310, the feedback controller 330 and the drive signal generator 340 have already been described with reference to FIG.

  The error detector 310 includes a position command value generation unit 312, a position detection value generation unit 314, and a subtractor 316. Position command value generation unit 312 generates position command value P_TGT indicating a target position of the rotor based on clock signal CLK. Position command value P_TGT corresponds to position command value TGT in FIG.

  The position detection value generation unit 314 generates a position detection value P_FB indicating the current position of the rotor based on the pulse signals EN_A and EN_B from the encoder. The position detection value P_FB corresponds to the feedback value FB of FIG.

  Position command value P_TGT and position detection value P_FB are input to subtractor 316 to generate position error value ERR.

  The feedback controller 330 generates the torque command value T_REF so that the position detection value P_FB approaches the position command value P_TGT, that is, the position error value ERR approaches zero. Torque command value T_REF corresponds to command value REF in FIG. The torque command value T_REF is supplied to the drive signal generation unit 340.

  The drive IC 200D is configured to be able to switch between the rotation control mode and the holding mode. Control characteristics of the feedback controller 330 are different between the rotation control mode and the holding mode.

As mentioned above, the feedback controller 330 can include a PI (Proportional Integral) controller. In the rotation control mode and the holding mode, at least one of the proportional gain K _P and the integral gain K _I is preferably different.

Typically, the proportional gain K _P in hold mode is equal to or less than the proportional gain K _P in rotational control mode. The integral gain K _I in the holding mode, or equal to the integral gain K _I in the rotation control mode is smaller than that.

  Mode determination unit 470 determines the rotation control mode and the hold mode based on the input state of clock signal CK. Mode determination unit 470 shifts from the rotation control mode to the holding mode when the no-input state of clock signal CLK continues for a predetermined time. In addition, when the edge of the clock signal CLK is detected in the holding mode, the rotation control mode is immediately entered.

  The above is the basic configuration of the drive IC 200D. According to drive IC 200D, in the rotation control mode, a control parameter giving priority to followability to a rotation command based on clock signal CLK is given, and in the hold mode, a control parameter giving importance not to followability but stability. It becomes possible to drive the DC motor like a stepping motor.

  When the rotation control mode and the holding mode are switched, it is preferable to reset the integrated value in the PI controller to zero. As a result, it is possible to suppress the induction of unnecessary vibration accompanying the switching of control parameters and the prolongation of the stabilization time.

  Furthermore, the operation of the drive signal generator 340 (energization logic 344), that is, the method of generating the drive signal may be different between the rotation control mode and the holding mode.

  For example, in the rotation control mode, drive signal generation unit 340 determines the rotation direction according to the CW_CCW signal, and when torque command value T_REF is positive, the DC motor is operated at a duty ratio according to torque command value T_REF. PWM drive. When the torque command value T_REF is negative, the driver 106 is set to high impedance to perform idling control.

  Further, in the holding mode, drive signal generation unit 340 determines the rotation direction according to the sign (positive or negative) of torque command value T_REF regardless of the CW_CCW signal. Thereby, the position of the rotor can be fixed more accurately.

FIG. 8 is a block diagram showing a configuration example of the drive IC 200D. For example, mode determination unit 470 includes a counter 472 and a state machine 474. Counter 472 measures the duration of the no-input state of the clock signal CLK, and no input time the asserted (e.g. high) time-up signal TIMEUP1 exceeds a predetermined time tau _1.

Although the configuration of counter 472 is not particularly limited, it may be formed of, for example, a free run counter reset by the positive edge of clock signal CLK. Counter 472, the count value reaches the threshold value TH ₁ corresponding to the determined time tau ₁ (overflow), and asserts a time-up signal TIMEUP1.

  The state machine 474 shifts to the holding mode in response to the assertion of the time-up signal TIMEUP1. The state machine 474 immediately shifts to the rotation control mode when it detects an edge of the clock signal CLK in the hold mode.

  The feedback controller 330 includes a first controller 332, a second controller 334, and a selector 336. The first controller 332 is associated with the rotation control mode and generates a torque command value T_REF1. The second controller 334 is associated with the holding mode and generates a torque command value T_REF2. As described above, in the first controller 332 and the second controller 334, at least one of the proportional gain and the integral gain is different.

  The selector 336 receives the torque command values T_REF1 and T_REF2, selects one according to the current mode, and supplies the selected one as the torque command value T_REF to the drive signal generation unit 340 in the subsequent stage.

The state machine 474 also outputs a reset signal RESET at each mode transition.
The first controller 332 and the second controller 334 reset the integrated value to zero in response to the reset signal RESET.

  The first controller 332 may be stopped during the holding mode or may continue to operate. In addition, the second controller 334 may be stopped or kept operating during the rotation control mode.

  As shown in FIG. 8, the rotation control mode and the holding mode can be switched seamlessly by providing the two systems of controllers 332 and 334.

  FIG. 9 is a time chart for explaining the transition of the mode of the drive IC 200D of FIG. While the clock signal CLK is input, the rotation control mode is selected, and the DC motor is controlled based on the torque command value T_REF1 generated by the first controller 332.

The counter 472 is free-running using an internal clock CK _SYS generated by an oscillator incorporated in the drive IC 200D. When the clock signal CLK stops, the counter 472 continues to count up without being reset. When the count value at time _{t 1} reaches the threshold TH _1, the time-up signal TIMEUP1 is asserted, the process proceeds to the holding mode.

  In the holding mode, the DC motor is controlled based on the torque command value T_REF2 generated by the second controller 334.

To time _{t 2, the} clock signal CLK from the host controller is re-entered, to return to the rotation control mode, DC motor is controlled based on the torque command value T_REF1 the first controller 332 generates.

  A modification of switching between the rotation control mode and the holding mode will be described.

(Modification 1)
Although the case of switching the gain of the PI controller in the rotation control mode and the holding mode has been described, it is not limited thereto. For example, control methods (P control, PI control, PID control) may be different between the rotation control mode and the holding mode.

(Modification 2)
The calculation cycle (ΔT) may be different between the rotation control mode and the holding mode. That is, in the holding mode, the operation cycle ΔT may be extended, and in the rotation control mode, the operation cycle ΔT may be shortened.

(Modification 3)
The counter 472 can be shared with the counter 450 when the drive IC 200D supports the sleep mode described later and the counter 450 (FIG. 11) described later is provided. Further, the determination time τ ₁ in the counter 472 is set equal to or shorter than the determination time τ ₂ in the counter 450.

(Modification 4)
FIG. 10 is a block diagram of part of a drive IC 200D according to the fourth modification. In this variation, feedback controller 330 includes a single PI controller 338. As proportional gain K _P and integral gain K _I of PI controller 338, values K _P1 and K _I1 for rotation control mode and values K _P2 and K _I2 for holding mode are prepared separately, and mode judgment unit 470 instructs The set of values according to the mode to be loaded is loaded into the PI controller 338 and the gain is changed. Further, the value of the memory 339 holding the integral value of the PI controller 338 becomes zero in response to the reset signal RESET generated by the mode determination unit 470.

(Modification 5)
The mode is switched depending on the presence or absence of the clock signal CLK, but this is not the case. A signal indicating a mode may be given from the host controller to the drive IC 200D, and the mode may be switched according to this signal.

(Pause mode)
FIG. 11 is a block diagram of a portion of a drive IC 200C that supports sleep mode. The drive IC 200C includes a counter 450 and a pause mode determination unit 460 in addition to the error detector 310, the feedback controller 330, and the drive signal generation unit 340. The main functions and operations of the error detector 310, the feedback controller 330, and the drive signal generator 340 have already been described with reference to FIG.

  The error detector 310 includes a position command value generation unit 312, a position detection value generation unit 314, and a subtractor 316. Position command value generation unit 312 generates position command value P_TGT indicating a target position of the rotor based on clock signal CLK. Position command value P_TGT corresponds to position command value TGT in FIG.

  The position detection value generation unit 314 generates a position detection value P_FB indicating the current position of the rotor based on the pulse signals EN_A and EN_B from the encoder. The position detection value P_FB corresponds to the feedback value FB of FIG.

  Position command value P_TGT and position detection value P_FB are input to subtractor 316 to generate position error value ERR.

  The feedback controller 330 generates the torque command value T_REF so that the position detection value P_FB approaches the position command value P_TGT, that is, the position error value ERR approaches zero. Torque command value T_REF corresponds to command value REF in FIG. The torque command value T_REF is supplied to the drive signal generation unit 340.

In a situation where it is not necessary to rotate the DC motor, the clock signal CLK from the host controller is stopped. So drive IC200C is no input of the clock signal CLK as a condition for a predetermined time (referred judgment time tau ₂₎ that sustained, the operation of at least some of the circuit blocks is transferred to sleep mode to stop. The determination time may be settable using a register.

Counter 450 receives a clock signal CLK, when the no-input state of the clock signal CLK judgment time tau ₂ lasts, asserts a time-up signal TIMEUP2 (e.g. high). The counter 450 may use a counter provided for purposes other than the detection of the non-input state of the clock signal CLK.

The configuration of counter 450 is not particularly limited, but may be a free run counter that is reset by the positive edge of clock signal CLK, for example. Counter 450 reaches the threshold TH ₂ the count value corresponding to the determined time (overflow), and asserts a time-up signal TIMEUP2.

  The sleep mode determination unit 460 transitions to the sleep mode under assertion of the time-up signal TIMEUP2 as one of the conditions.

FIG. 12 is a time chart illustrating the transition to the sleep mode. The counter 450 is free-running using an internal clock CK _SYS generated by an oscillator incorporated in the drive IC 200C. When the clock signal CLK stops, the counter 450 continues to count up without being reset. When the time _{t 1} the count value reaches the threshold TH, the time-up signal TIMEUP2 is asserted, the process proceeds to sleep mode.

  By using the drive IC 200C, the power consumption of the drive IC 200C can be reduced in a state in which the stop of the DC motor should be maintained.

  In the sleep mode, the counter 450 can be stopped. Continued free running of the counter 450 consumes wasteful power, but once it has entered the sleep mode, there is no need to measure the no-input state of the clock signal CLK, so stopping the counter 450 will reduce power consumption. Can be reduced.

During the idle mode, if the system clock _{CK SYS} is not used, it is possible further to stop the oscillator (oscillator 288 of FIG. 2) for generating a system clock _{CK SYS.}

  In addition, in the state where the stop of the DC motor continues, if the servo is continued without stopping the feedback controller 330 or the drive signal generation unit 340, useless power is consumed. Therefore, the drive IC 200C may stop the energization of the DC motor in the pause mode. In this case, power consumption can be further reduced by stopping the feedback controller 330 and the drive signal generation unit 340.

In an application where an external force is applied to the DC motor, when an external force is applied while the servo is off, the rotor may rotate and may deviate from the target position indicated by the position command value P_TGT. In this case, it is necessary to drive the DC motor to return to the target position. Therefore, the pause mode determination unit 460 monitors the position error value ERR, and enters the pause mode on the condition that the position error value ERR is zero in addition to the fact that the no-input state of the clock signal CLK continues for a predetermined time. You may migrate. The feedback controller 330 and the drive signal generator 340 can be further stopped in a situation where it is not necessary to generate torque during the pause mode.
When the position error value ERR is zero, it is not necessary to drive the DC motor any more, so it is possible to stop other unnecessary circuit blocks in addition to the counter.

  In one embodiment, when the clock signal CLK is not input and the state where the position error value ERR is zero continues for a predetermined time, the sleep mode may be entered.

  In one embodiment, after the first state where the clock signal CLK is not input lasts for a first time, it may be in the sleep mode during a period in which the position error value ERR is zero.

  In one embodiment, when the clock signal CLK is not input for the first time and then the position error value ERR is zero for the second time, the sleep mode may be entered.

  In one embodiment, idle mode determination unit 460 may monitor torque command value T_REF in addition to or instead of position error value ERR. When the position error value ERR continues to be zero, the torque command value T_REF also becomes zero eventually. Therefore, the pause mode determination unit 460 monitors the torque command value T_REF, and enters the pause mode on condition that the torque command value T_REF is zero in addition to the non-input state of the clock signal CLK continuing for a predetermined time. After the transition, the feedback controller 330 and the drive signal generator 340 may be stopped.

  In one embodiment, when the clock signal CLK is not input and the state of the torque command value T_REF is zero continues for a predetermined time, transition to the pause mode is performed, and the feedback controller 330 and the drive signal generation unit 340 are stopped. .

  In one embodiment, the feedback controller 330 and the drive signal generator 340 may be stopped during a period in which the torque command value T_REF is zero after the non-input state of the clock signal CLK continues for the first time.

  In one embodiment, when the state where the clock signal CLK is not input lasts for the first time and the state where the torque command value T_REF is zero continues for the second time, the feedback controller 330 and the drive signal generator 340 are stopped. May be

  In one embodiment, on the condition that both the torque command value T_REF and the position error value ERR are zero, transition to the pause mode may be performed.

  In addition to the feedback controller 330 and the drive signal generator 340, the error detector 310 may be stopped during the pause mode. This can further reduce power consumption.

  Although not illustrated in FIG. 11, the drive IC 200C detects a speed command value based on the frequency (period) of the clock signal CLK (speed command value generation unit 414 in FIG. 13) or the pulse signal EN_A from the encoder. There is also a case where a circuit (speed detection value generation unit 424 in FIG. 13) for detecting the current rotation speed of the motor is provided based on the frequency (period) of EN_B. In this case, these detection circuits may be stopped during the sleep mode.

Subsequently, return from the sleep mode to the normal mode will be described.
In the sleep mode, drive IC 200C may return to the normal mode as soon as the input of clock signal CLK is detected.

  The drive IC 200C may immediately return to the normal mode on condition that the position error value ERR or the torque command value T_REF becomes nonzero.

  At the time of return, it is desirable that at least one of the speed command value and the torque command value can be reset to any value. As a result, the rotational speed and torque immediately after the return can be freely determined, and the DC motor can be smoothly restarted.

(Short brake)
FIG. 13 is a block diagram of a portion of a drive IC 200B having a short brake function. The drive IC 200B includes a brake controller 430 in addition to the error detector 310B, the feedback controller 330, and the drive signal generator 340. The main functions and operations of the error detector 310, the feedback controller 330, and the drive signal generator 340 have already been described with reference to FIG.

  The error detector 310 B includes a first detection circuit 410, a second detection circuit 420, and a subtractor 316. The first detection circuit 410 generates a position command value P_TGT indicating the target position of the rotor and a speed command value V_TGT indicating the target number of rotations of the rotor based on the clock signal CLK. Position command value P_TGT corresponds to position command value TGT in FIG. Speed command value V_TGT is proportional to the frequency of clock signal CLK, in other words, inversely proportional to the cycle of clock signal CLK.

  The second detection circuit 420 generates a position detection value P_FB indicating the current position of the rotor and a speed detection value V_FB indicating the current rotation speed of the rotor based on the pulse signals EN_A and EN_B from the encoder. The position detection value P_FB is simply shown as a feedback value FB in FIG. The speed detection value V_FB is proportional to the frequency of the pulse signals EN_A and EN_B, in other words, inversely proportional to the period of the pulse signals EN_A and EN_B.

  Position command value P_TGT and position detection value P_FB are input to subtractor 316 to generate position error value ERR. Further, the position command value P_TGT and the position detection value P_FB are supplied to the brake controller 430 together with the speed command value V_TGT and the speed detection value V_FB.

  The feedback controller 330 generates the torque command value T_REF so that the position detection value P_FB approaches the position command value P_TGT, that is, the position error value ERR approaches zero. Torque command value T_REF corresponds to command value REF in FIG. The torque command value T_REF is supplied to the drive signal generation unit 340 and is also supplied to the brake controller 430.

  The brake controller 430 performs brake control based on the position detection value P_FB, the position command value P_TGT, the speed detection value V_FB, the speed command value V_TGT, and the torque command value T_REF.

  Specifically, when position detection value P_FB is larger than position command value P_TGT (ie, position excess), speed detection value V_FB is larger than speed command value V_TGT (ie, speed excess), and torque command value T_REF is negative. , Asserts the brake signal BRAKE (for example, high level), and instructs the drive signal generator 340 to apply a short brake.

  If all the conditions for the short brake are not satisfied, that is, if the torque is negative but the position excess is not generated, the output of the driver 106 is made high impedance (slip control).

The conditions for applying the brake are the following three.
(Condition 1) Over position P_FB> P_TGT
(Condition 2) Overspeed V_FB> V_TGT
(Condition 3) T_REF <0

The condition may be set as follows in consideration of the margin.
(Condition 1) Over position P_FB> P_TGT + ΔP
(Condition 2) Overspeed V_FB> V_TGT + ΔV
(Condition 3) T_REF <-ΔT
ΔP, ΔV, ΔT are margins.

  FIG. 14 is a block diagram of the brake controller 430. The brake controller 430 may include a position excess determination unit 432, a speed excess determination unit 434, a negative torque determination unit 436, and a logic gate 438.

  When the condition 1 is satisfied, the position excess determination unit 432 asserts (for example, high) the position excess signal S1. When the condition 2 is satisfied, the overspeed determination unit 434 asserts the overspeed signal S2. When the condition 3 is satisfied, the negative torque determination unit 436 asserts the negative torque determination signal S3. Logic gate 438 is an AND gate, for example, and asserts brake signal BRAKE when three conditions are met simultaneously.

  FIGS. 15A and 15B illustrate the operation of the brake controller 430. FIG. First, the positional excess will be described with reference to FIG. For the sake of simplicity, the position command value P_TGT and the position detection value P_FB are both zero in the initial state. Position command value P_TGT increases for each positive edge of clock signal CLK. The position detection value P_FB increases with each pulse of the pulse signal EN_A (EN_B) from the encoder. If P_FB> P_TGT, that is, if ERR <0, the position excess determination unit 432 asserts the position excess signal S1. The occurrence of position excess may be detected based on the position error value ERR which is the output of the subtractor 316.

Overspeed will be described with reference to FIG. Speed command value V_TGT is proportional to frequency f _CK of clock signal CLK, and inversely proportional to period 1 / f _CK of clock signal CLK. Similarly, the speed detection value V_FB is proportional to the frequency f _FB of the pulse signal EN_A from the encoder and inversely proportional to the period 1 / f _FB of the pulse signal EN_A. The speed excess determination unit 434 compares the frequencies f _CK and f _FB corresponding to each cycle, in other words, the cycles 1 / f _CK and 1 / f _FB , and when f _FB > f _CK , in other words, 1 / f _FB < At 1 / f _CK , the overspeed signal S2 is asserted.

  It returns to FIG. In response to the assertion of the brake signal BRAKE, the drive signal generator 340 turns on all high side transistors of U phase, V phase and W phase and turns off all low side transistors (or vice versa, all low side transistors). The drive signals SUH, SUL, SVH, SVL, SWH, SWL are made to transition so that all the high side transistors are turned off).

The above is the configuration of the drive IC 200B.
In the motor drive system 100, a decrease in the frequency of the clock signal CLK from the host controller means a deceleration command. The drive IC 200B applies a brake not on condition of the reduction of the frequency of the clock signal CLK but on condition of the above-mentioned conditions 1 to 3. Thereby, the DC motor can be decelerated accurately.

  Note that the brake may be applied on the condition that the conditions 1 and 3 are not satisfied but all of the conditions 1 to 3, that is, the position excess and the torque are negative. In this case, a circuit for generating the speed command value and the speed detection value can be omitted.

(PI controller)
In the platform for driving the stepping motor, when the stopped stepping motor is rotated, if the frequency of the clock signal CLK corresponding to the command value of the number of revolutions of the motor is made a high frequency, the motor may be out of step.

Therefore, in many platforms, at the start of rotation of the stepping motor, the frequency of the clock signal CLK is often gradually increased with time. On the other hand, when stopping the stepping motor rotating at a constant speed, the frequency of the clock signal CLK (hereinafter referred to as clock frequency _fCK ) is often gradually decreased with time. Therefore, the clock frequency _fCK often changes in accordance with a trapezoidal wave or a similar waveform (hereinafter simply referred to as a trapezoidal wave) in one cycle of stop, constant speed rotation and stop of the stepping motor.

Even in the platform in which the stepping motor is replaced with the DC motor as in the present embodiment, the clock frequency f _CK from the upper controller 104 is assumed to change in a trapezoidal wave shape. FIG. 16 is a waveform diagram of the frequency f _CK of the clock signal CLK. (I) to (iii) indicate that the rotational speed at constant speed is different.

As mentioned above, the feedback controller 330 includes a PI controller whose control characteristics are defined by the proportional gain K _P and the integral gain K _I. The feedback controller 330 according to the embodiment dynamically changes the control characteristic (at least one of the proportional gain and the integral gain) according to the clock frequency _fCK . Thereby, the followability of the motor can be enhanced as compared with the case where the control characteristic is fixed.

The feedback controller 330 holds, in a memory, a table that holds the relationship between the clock frequency f _CK and the control characteristics (proportional gain, integral gain).

More preferably, after the start of rotation of the DC motor, while the clock frequency f _CK is rising, the integral gain K _I may be fixed and only the proportional gain K _P may be changed according to the clock frequency f _CK . The proportional gain K _P has a positive correlation with the clock frequency f _{CK and} may be monotonically increasing.

FIG. 17 is a diagram showing the number of revolutions of the motor when the motor drive system 100 is started. (I) shows the waveform when the control characteristic is fixed, (ii) shows the waveform when changing only the proportional gain K _P , and (iii) shows both the proportional gain K _P and the integral gain K _I Shows the waveform when changing. (Iv) is a target rotational speed based on the clock frequency f _CK . f ₁ , f ₂ ... indicate threshold values at which the control characteristics are switched.

As shown in (i), when the control characteristic is fixed, it takes a long time for the rotational speed to reach the target rotational speed. On the other hand, as shown in (iii), when both the proportional gain and the integral gain are changed, the integral term accumulated up to that point increases at the timing at which the integral gain K _I is switched. Yes (uneven rotation). Therefore, as shown in (ii), by changing only the proportional gain while keeping the integral gain constant, it is possible to improve the followability while suppressing the rotation unevenness.

Here, the operation for increasing the rotational speed has been described, but the same is true for reducing the rotational speed, and the proportional gain K _P is changed according to the clock frequency f _CK while keeping the integral gain K _I constant. It is good.

(Electronic gear)
Subsequently, the electronic gear will be described. Depending on the specifications of the upper controller 104, the variable range of the frequency f _CK of the clock signal CLK may be restricted. For example, if the upper limit _{f MAX} of the clock frequency _{f CK} is low, the rotational speed of the DC motor is restricted by the upper limit _{f MAX.} When it is desired to rotate the motor at a rotational speed higher than the rotational speed specified by the upper limit frequency f _MAX , conventionally, it has been necessary to use a mechanical gear, which has been a factor in cost increase. In order to solve this problem, the drive IC 200 has the function of an electronic gear.

  FIG. 18 is a view for explaining the function of the electronic gear. As described above, in position command value generation unit 312, the number of edges of clock signal CLK is integrated. In FIGS. 6A to 6C, the target value TGT is incremented or decremented by one for each edge of the clock signal CLK.

  On the other hand, in the logic circuit 300A having an electronic gear, the change amount ΔTGT to be incremented / decremented can be externally set for each edge of the clock signal CLK. FIG. 18 shows the operation when three stages of ΔTGT = 1, 2 and 4 are switched.

  The rotation angle of the rotor per pulse of clock signal CLK can be controlled in accordance with change amount ΔTGT. Therefore, the change amount ΔTGT corresponds to an electronic gear ratio. By implementing the function of the electronic gear, it is possible to reduce or eliminate the mechanical gear, so that the cost and size of the device can be reduced, and the structure of the device can be simplified, thereby reducing the risk of failure. be able to.

FIG. 19 is a block diagram of a drive IC 200A having the function of an electronic gear. The drive IC 200A is provided with a setting pin MODE for setting the electronic gear, and the amount of change ΔTGT is selected according to the state of the setting pin MODE. For example, a resistor can be externally connected to the setting pin MODE, and a voltage V _MODE is generated in the setting pin MODE according to the presence or absence of the resistor or the resistance value of the resistor. The mode voltage V _MODE is detected by the comparator CMP1 or an A / D converter (not shown), and the amount of change _ΔTGT according to the mode voltage V _MODE is selected.

  More specifically, the function of the electronic gear can be implemented in the position command value generation unit 312. The implementation of the function of the electronic gear will be described with reference to FIGS. 6 (a) to 6 (c). For example, in the position command value generation unit 312 of FIG. 6A, the increment and decrement amount of the counter 322 may be changed according to the state of the setting pin MODE.

  In position command value generation unit 312 of FIG. 6B, if the value given to input A of operation unit 324 can be switched in multiple values of 1, 2, 4... According to the state of setting pin MODE. Good.

  In the position command value generation unit 312 of FIG. 6C, the positive and negative two values input to the selector 327 can be switched to 1 ×, 2 ×, 4 ×, etc. according to the state of the setting pin MODE. do it.

The method of setting change amount ΔTGT corresponding to the gear ratio is not limited to the one using setting pin MODE, but may be a register using I ² C (Inter IC) interface, SPI (Serial Peripheral Interface), etc. The set value may be written to

  The value of ΔTGT is not limited to 1, 2, 4... And may be any integer. Alternatively, ΔTGT may be 1/2, 1/4, 1/8 ... or any fraction. By setting ΔTGT <1, deceleration control is possible.

  FIG. 20 is a block diagram of a drive IC 200B having the function of an electronic gear. In the drive IC 200B, the change amount of the target value TGT is constant, and the change amount ΔFB of the feedback value FB per pulse of EN_A, EN_B can be changed. ΔFB can be set to any integer or noninteger value. The rotation speed can be reduced by increasing ΔFB per pulse of EN_A (EN_B signal). Conversely, if ΔFB per pulse of EN_A (EN_B signal) is reduced, the number of rotations can be increased. The gear ratio selection unit 360 is a block corresponding to the comparator CMP1 (or A / D converter) of FIG. 19, and selects ΔFB according to the state of the setting pin MODE.

(Use)
FIG. 21 is a diagram showing an electronic device provided with the motor drive system 100. As shown in FIG. FIG. 21 illustrates a printer as an example of the electronic device 900. The electronic device 900 includes a plurality of DC motors 902 and 904. For example, the DC motor 902 is used for the drive mechanism 912 of the print head 910. The DC motor 904 is used as a paper feed drive mechanism 914.

  The application of the motor drive system 100 is not limited to a printer, and can be used for various OA devices, industrial devices, and industrial machines.

  The present invention has been described above based on the embodiments. It is understood by those skilled in the art that this embodiment is an exemplification, and that various modifications can be made to the combination of each component and each processing process, and such a modification is also within the scope of the present invention. is there. Hereinafter, such modifications will be described.

(Modification 1)
Although the motor drive using a Hall sensor has been described in the embodiment, it may be sensorless. In this case, a comparator for detecting a back electromotive force may be mounted on the drive IC 200.

(Modification 2)
Although the charge pump is used to obtain the gate drive voltage of the high side transistor of the driver 106 in the embodiment, a bootstrap circuit may be incorporated. The high side transistor of the driver 106 may be a P channel, and in this case, the charge pump is unnecessary.

(Modification 3)
In the embodiment, the driver 106 is externally attached to the drive IC 200, but the driver 106 may be integrated into the drive IC 200. On the other hand, although the predriver 250 is integrated in the drive IC 200 in the embodiment, the predriver 250 may be provided outside the drive IC 200. For example, the driver 106 and the predriver 250 may be integrated.

(Modification 4)
In the embodiment, the drive IC is implemented by a logic circuit. However, the present invention is not limited to this. The block indicated by the logic circuit 300 may be configured by a combination of a processor (CPU or microcomputer) and a software program.

100 motor drive system 102 DC motor 104 host controller 106 driver 110 hall sensor 112 encoder 200 drive IC
BUF input buffer HCMP Hall comparator 250 predriver 260 power supply circuit group 262 operational amplifier 264 reference voltage source 266 charge pump 268, 270 power supply circuit 280 protection circuit 300 logic circuit 310 error detector 312 position command value generation unit 314 position detection value generation unit 316 Subtractor 320 Edge detection circuit 322 Up / down counter 324 Operation unit 325 Memory 326 Opcode selector 327 Selector 328 Adder 329 Memory 330 Feedback controller 340 Drive signal generator 342 Pulse width modulator 344 Energizing logic 360 Gear ratio selector

Claims (24)

DC motor drive circuit,
A position error which is a difference between a current position of the rotor of the DC motor based on the pulse signal and a target position of the rotor based on the clock signal in response to a clock signal from the host controller and a pulse signal from the encoder An error detector that produces a value;
A feedback controller, which comprises a logic circuit, and generates a command value so that the position error value approaches zero;
A drive signal generation unit configured by a logic circuit and generating a drive signal according to the command value;
And a driving circuit characterized in that the driving circuit is integrated on one semiconductor substrate.   The drive circuit according to claim 1, wherein the feedback controller includes a PI (proportional integration) controller.   The drive circuit according to claim 2, wherein the control characteristic of the PI controller dynamically changes according to the frequency of the clock signal.   The drive circuit according to claim 3, wherein an integral gain of the PI controller is constant, and a proportional gain changes according to a frequency of the clock signal. The error detector
A position command value generation unit that generates a target value according to an integrated value of the number of edges of the clock signal;
A position detection value generation unit that generates a feedback value indicating the current position of the rotor based on the pulse signal;
A subtractor that generates a difference between the target value and the feedback value;
The drive circuit according to any one of claims 1 to 4, further comprising:   6. The drive circuit according to claim 5, wherein the position command value generation unit can select the amount of change of the target value per edge of the clock signal from a plurality of values.   7. The drive circuit according to claim 5, wherein the position detection value generation unit can select a change amount of the feedback value per one pulse signal from a plurality of values.   8. The drive circuit according to claim 6, further comprising a setting pin for specifying the amount of change.   The drive circuit according to any one of claims 1 to 8, further comprising a predriver for controlling an inverter for driving the DC motor. DC motor,
A driver including an inverter for driving the DC motor;
The drive circuit according to any one of claims 1 to 9, which controls the driver.
An electronic device comprising: A driving circuit for driving a DC motor according to a clock signal from a host controller and a pulse signal indicating the position of a rotor of the DC motor from an encoder,
An error detector that generates a position error value according to a difference between a position command value indicating the target position of the rotor based on the clock signal and a position detection value indicating the current position of the rotor based on the pulse signal;
A feedback controller that generates a torque command value such that the position error value approaches zero;
A drive signal generation unit that generates a drive signal according to the torque command value;
Equipped with
A rotation control mode and a holding mode can be switched, and at least one of a control characteristic of the feedback controller and a method of generating the drive signal in the drive signal generation unit is switched between the rotation control mode and the holding mode. Drive circuit. The feedback controller includes a PI (Proportional Integral) controller,
The drive circuit according to claim 11, wherein at least one of a proportional gain and an integral gain of the PI controller is different between the rotation control mode and the holding mode.   13. The drive circuit according to claim 12, wherein the integral value is reset to zero when the rotation control mode and the holding mode are switched.   The drive circuit according to any one of claims 11 to 13, further comprising a mode determination unit that determines the rotation control mode and the holding mode based on an input state of the clock signal.   The mode determination unit may include a counter that measures a duration of a no-input state of the clock signal, and transitions from the rotation control mode to the holding mode when the no-input state of the clock signal continues for a predetermined time. The drive circuit according to claim 14, wherein   16. The drive circuit according to any of claims 11 to 15, wherein the feedback controller includes a first controller associated with the rotation control mode and a second controller associated with the holding mode.   The drive circuit according to any one of claims 11 to 16, wherein the feedback controller includes a single controller, and gains are changed in the rotation control mode and the holding mode.   The drive signal generation unit determines the rotation direction according to the direction indication signal from the host controller in the rotation control mode, and determines the rotation direction based on the sign of the torque command value in the holding mode. The drive circuit according to any one of claims 11 to 17, characterized by: The drive signal generation unit
A pulse width modulator that generates a PWM (Pulse Width Modulation) signal having a duty ratio corresponding to the torque command value;
Energizing logic that generates the drive signal based on the PWM signal and the output of the Hall comparator;
The drive circuit according to any one of claims 11 to 18, comprising:   The drive circuit according to any one of claims 11 to 19, further comprising a predriver for controlling an inverter for driving the DC motor.   21. The drive circuit according to any one of claims 1 to 20, wherein the drive circuit is integrated on one semiconductor substrate. DC motor,
A driver including an inverter for driving the DC motor;
The drive circuit according to any one of claims 11 to 21, which controls the driver.
An electronic device comprising: A method of driving a DC motor,
Generating a position command value indicating a target position of the rotor of the DC motor based on a clock signal from a host controller;
Generating a position detection value indicating the current position of the rotor based on a pulse signal indicating the position of the rotor of the DC motor from the encoder;
Selecting a rotation control mode and a holding mode;
Generating a torque command value such that an error between the position detection value and the position command value approaches zero, wherein control characteristics differ between the rotation control mode and the holding mode;
A driving method comprising: A method of driving a DC motor,
Generating a position command value indicating a target position of the rotor of the DC motor based on a clock signal from a host controller;
Generating a position detection value indicating the current position of the rotor based on a pulse signal indicating the position of the rotor of the DC motor from the encoder;
Generating a torque command value such that an error between the position detection value and the position command value approaches zero;
Selecting a rotation control mode and a holding mode;
Generating a drive signal that defines the state of the inverter based on the torque command value, wherein the method of generating the drive signal differs between the rotation control mode and the holding mode;
A driving method comprising:

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