JP2020009507A - Semiconductor storage device - Google Patents

Abstract

An object of the present invention is to avoid the occurrence of a malfunction caused by a functional stoppage of a specific circuit block of a semiconductor memory device. A semiconductor memory device includes a power detection circuit, a memory circuit, and a logic circuit. The power detection circuit outputs a power detection signal of a first level when the level of the power supply voltage supplied to the power supply line is higher than a predetermined level, and outputs a first level power detection signal when the level of the power supply voltage is lower than the predetermined level. A power supply detection signal of a second level different from the level is output. The power detection circuit includes a first cutoff circuit that cuts off an internal current path according to a control signal, and a holding circuit that holds the level of the power detection signal at the first level according to the control signal. A memory circuit includes a plurality of memory cells. A logic circuit controls the memory circuit based on the level of the power supply detection signal. [Selection drawing] Fig. 1

Description

  The disclosed technology relates to a semiconductor memory device.

  The following techniques are known as techniques relating to semiconductor memory devices.

  For example, there is known a semiconductor integrated circuit in which a power supply voltage applied from an external power supply is stepped down and applied to an internal main circuit, and has an active mode and a standby mode. The semiconductor integrated circuit includes an internal step-down unit for stepping down a power supply voltage supplied from an external power supply, and a deactivating unit for deactivating the internal step-down unit in a standby mode. The semiconductor device further includes a power supply voltage applying unit for directly applying a power supply voltage applied from an external power supply to the main circuit in the standby mode.

  Further, there is known a semiconductor device including a first reference voltage generation circuit which is inactivated during standby and generates a predetermined reference voltage during an operation during non-standby and outputs the predetermined reference voltage to a reference voltage line. The semiconductor device further includes a second reference voltage generation circuit that generates a reference voltage in standby mode with a through current smaller than that of the first reference voltage generation circuit and outputs the generated reference voltage to a reference voltage line.

  There is also known an internal step-down circuit in which a reference voltage generating circuit and an internal voltage control circuit form an internal step-down voltage obtained by stepping down a power supply voltage and supply the same to a static memory. When the static memory is in the holding state, the internal voltage step-down circuit sets the reference voltage generation circuit and the internal voltage control circuit to the off state, and reduces the data holding voltage by using step-down means having lower power consumption than these circuits. Is configured to obtain.

JP-A-4-47591 JP 2005-50473 A JP-A-2-40195

  As a semiconductor memory device including a memory circuit including a memory cell, a semiconductor memory device having a sleep function is known. In this type of semiconductor memory device, when the sleep function is enabled, at least one of the circuit blocks constituting the semiconductor memory device is in a function stop state, thereby reducing power consumption. However, for example, when a circuit block that outputs a signal necessary for operation control of the semiconductor memory device is brought into a halt state by the sleep function, there is a possibility that the operation control of the semiconductor memory device may not be possible.

  The disclosed technique has, as one aspect, an object to avoid occurrence of an operation failure due to a stoppage of a function of a specific circuit block of a semiconductor memory device.

  A semiconductor memory device according to the disclosed technology includes a power supply detection circuit. The power supply detection circuit outputs a first level power supply detection signal when a power supply voltage level supplied to a power supply line is higher than a predetermined level, and outputs a power supply voltage when the power supply voltage level is lower than the predetermined level. A power detection signal of a second level different from the first level is output. The power supply detection circuit includes a first cutoff circuit that cuts off an internal current path according to a supplied control signal, and a holding circuit that holds the level of the power supply detection signal at the first level according to the control signal. And a circuit. The semiconductor storage device includes a memory circuit including a plurality of memory cells, and a logic circuit that controls the memory circuit based on a level of the power detection signal.

  The disclosed technology has, as one aspect, an effect that it is possible to avoid occurrence of an operation failure due to a stoppage of a function of a specific circuit block of a semiconductor memory device.

FIG. 2 is a circuit block diagram illustrating an example of a configuration of a semiconductor storage device according to an embodiment of the disclosed technology. FIG. 2 is a circuit diagram illustrating an example of a configuration of a reference voltage generation circuit according to an embodiment of the disclosed technology. FIG. 2 is a circuit diagram illustrating an example of a configuration of a power supply detection circuit according to an embodiment of the disclosed technology. 11 is a time chart illustrating an example of an operation of the semiconductor memory device according to the embodiment of the disclosed technology. FIG. 9 is a circuit block diagram illustrating an example of a configuration of a semiconductor memory device according to a first comparative example. FIG. 6 is a circuit diagram illustrating an example of a configuration of a reference voltage generation circuit according to a first comparative example. FIG. 6 is a circuit diagram illustrating an example of a configuration of a power supply detection circuit according to a first comparative example. 9 is a time chart illustrating an example of an operation of the semiconductor memory device according to the first comparative example. FIG. 11 is a circuit block diagram illustrating an example of a configuration of a semiconductor memory device according to a second comparative example. FIG. 9 is a circuit diagram illustrating an example of a configuration of a power detection circuit according to a second comparative example. 9 is a time chart illustrating an example of an operation of the semiconductor memory device according to the second comparative example.

  Hereinafter, an example of an embodiment of the disclosed technology will be described with reference to the drawings. In the drawings, the same or equivalent components and portions are denoted by the same reference numerals.

  FIG. 1 is a circuit block diagram illustrating an example of a configuration of a semiconductor storage device 1 according to an embodiment of the disclosed technology. The semiconductor memory device 1 includes a reference voltage generation circuit 10, a power supply detection circuit 20, a drive voltage generation circuit 30, a logic circuit 40, a level shift circuit 50, and a memory circuit 60.

  The reference voltage generation circuit 10 is, for example, a bandgap reference circuit, is driven by the power supply voltage V1 supplied to the power supply line L1, and generates a reference voltage Vref that is hardly affected by fluctuations in the power supply voltage V1 and the ambient temperature. The reference voltage Vref is supplied to the power supply detection circuit 20 and the drive voltage generation circuit 30, respectively. The level of the power supply voltage V1 is 3.3 V as an example.

  The power supply detection circuit 20 is driven by the power supply voltage V1 supplied to the power supply line L1, and determines the level of the power supply voltage V1 based on the level of the reference voltage Vref generated by the reference voltage generation circuit 10. Specifically, the power supply detection circuit 20 compares the voltage obtained by dividing the power supply voltage V1 with the reference voltage Vref, and outputs a power supply detection signal Sd indicating the comparison result. When the level of the voltage obtained by dividing the power supply voltage V1 is higher than the level of the reference voltage Vref (that is, when the level of the power supply voltage V1 is higher than a predetermined level), the power supply detection circuit 20 outputs a high-level power supply detection signal. Output Sd. On the other hand, when the level of the voltage obtained by dividing the power supply voltage V1 is lower than the level of the reference voltage Vref (that is, when the level of the power supply voltage V1 is lower than a predetermined level), the power supply detection circuit 20 outputs a low-level power supply. The detection signal Sd is output. The power detection signal Sd is supplied to the logic circuit 40.

  The logic circuit 40 controls the operation of the memory circuit 60 by changing the state of the semiconductor memory device 1 to a reset state or a reset release state based on the level of the power supply detection signal Sd. Specifically, when the level of the power supply detection signal Sd is low (that is, when the level of the power supply voltage V1 is lower than a predetermined level), the logic circuit 40 accepts input of various commands supplied from the outside. To a reset state. On the other hand, when the level of the power supply detection signal Sd is at a high level (that is, when the level of the power supply voltage V1 is higher than a predetermined level), the logic circuit 40 is in a reset release state for receiving input of various commands supplied from the outside. Transition to. The logic circuit 40 outputs a digital signal S1 indicating a reset state or a reset release state to the memory circuit 60. In the reset release state, the logic circuit 40 outputs a sleep signal Ss, which will be described later, according to a command supplied from the outside. The logic circuit 40 is driven by the power supply voltage V1 supplied to the power supply line L1.

  The drive voltage generation circuit 30 generates a drive voltage VDD obtained by lowering the power supply voltage V1 based on the reference voltage Vref generated by the reference voltage generation circuit 10. The drive voltage VDD is supplied to the level shift circuit 50 and the memory circuit 60, and is used as a power supply voltage for driving the level shift circuit 50 and the memory circuit 60. The level of the drive voltage VDD is 1.8 V, for example.

  The level shift circuit 50 shifts the level of the digital signal S1 supplied from the logic circuit 40 in a decreasing direction. Specifically, the level shift circuit 50 performs a level shift so that the 3.3 V digital signal S1 supplied from the logic circuit 40 is changed to a 1.8 V digital signal corresponding to the level of the drive voltage VDD. . The level-shifted digital signal S2 is supplied to the memory circuit 60.

  The memory circuit 60 includes a plurality of memory cells (not shown) and a memory control circuit (not shown) that controls writing and reading of data to and from each memory cell. The memory cell may constitute a nonvolatile memory such as an EEPROM (Electrically Erasable Programmable Read-Only Memory) and a FLASH, etc. The memory cell may be an SRAM (Static Random Access Memory) and a DRAM (Dynamic). It may constitute a volatile memory such as a Random Access Memory.

  The memory circuit 60 is driven by the drive voltage VDD. When the state indicated by the digital signal S2 is the reset release state, the memory circuit 60 accepts input of various commands supplied from the outside. In this case, the memory circuit 60 performs, for example, a data write operation and a data read operation in accordance with the received command. On the other hand, when the state indicated by the digital signal S2 is the reset state, the memory circuit 60 stops accepting a command input.

  The semiconductor storage device 1 has a sleep function. A sleep signal Ss for realizing a sleep function is supplied to each of the reference voltage generation circuit 10, the power supply detection circuit 20, and the drive voltage generation circuit 30. The sleep signal Ss is a control signal that instructs each of the reference voltage generation circuit 10, the power supply detection circuit 20, and the drive voltage generation circuit 30 to shift to a non-sleep state or a sleep state. When the low-level sleep signal Ss instructing the transition to the sleep state is supplied, the reference voltage generation circuit 10, the power supply detection circuit 20, and the drive voltage generation circuit 30 transition to the sleep state and stop their functions. Let it.

  FIG. 2 is a circuit diagram showing an example of the configuration of the reference voltage generation circuit 10. The reference voltage generation circuit 10 includes a voltage generation unit 11, an amplification unit 12, an output unit 13, and a switch SW.

  The voltage generator 11 includes resistance elements R1 to R4 and pnp transistors Q1 and Q2 that are diode-connected. The voltage generator 11 has a series circuit in which the resistance elements R2 and R3 and the pnp transistor Q1 are connected in series, and a series circuit in which the resistance element R4 and the pnp transistor Q2 are connected in series. One end of the resistance element R1 is connected to each of the series circuits, and the other end is connected to the output node N1.

  The amplification unit 12 includes p-channel transistors M1 to M3 and n-channel transistors M4 and M5. The gate of the p-channel transistor M2 forming one of the differential pairs is connected to the connection between the resistance elements R2 and R3. The gate of the p-channel transistor M3 forming the other of the differential pair is connected to a connection between the resistance element R4 and the pnp transistor Q2. The p-channel transistor M1 has a source connected to the power supply line L1, a drain connected to the sources of the p-channel transistors M2 and M3, and a gate connected to the bias line L3 to which the bias voltage Vb1 is supplied.

  The output unit 13 includes a p-channel transistor M6 and an n-channel transistor M7 connected in series between the power supply line L1 and the ground line L2. The gate of the p-channel transistor M6 is connected to the terminal t1 of the switch SW. The gate of the n-channel transistor M7 is connected to a connection between the p-channel transistor M3 and the n-channel transistor M5. The connection between the p-channel transistor M6 and the n-channel transistor M7 is used as the output node N1 of the reference voltage generation circuit 10, and the output node N1 outputs the reference voltage Vref.

  The switch SW has terminals t1, t2, and t3. The terminal t1 is connected to the gate of the p-channel transistor M6, the terminal t2 is connected to the power supply line L1, and the terminal t3 is connected to the bias line L3. The switch SW connects the terminal t1 to the terminal t2 or t3 according to the level of the sleep signal Ss. Specifically, when the high-level sleep signal Ss instructing the transition to the non-sleep state is supplied, the terminal t1 is connected to the terminal t3. As a result, the gate of the p-channel transistor M6 is connected to the bias line L3, and the p-channel transistor M6 is turned on. On the other hand, when the low-level sleep signal Ss instructing the transition to the sleep state is supplied, the terminal t1 is connected to the terminal t2. As a result, the gate of the p-channel transistor M6 is connected to the power supply line L1, and the p-channel transistor M6 is turned off. When the p-channel transistor M6 is turned off, the current path via the p-channel transistor M6 is cut off. That is, the switch SW and the p-channel transistor M6 function as a cutoff circuit that cuts off a current path inside the reference voltage generation circuit 10 according to the sleep signal Ss.

  FIG. 3 is a circuit diagram showing an example of the configuration of the power supply detection circuit 20. The power supply detection circuit 20 includes a voltage divider 21, a comparator 22, and an output unit 23.

  The voltage divider 21 includes a p-channel transistor M11 and resistance elements R11 and R12 connected in series between the power supply line L1 and the ground line L2, and an inverter INV1 connected to the gate of the p-channel transistor M11. ing. The sleep signal Ss is supplied to the input terminal of the inverter INV1. After the sleep signal Ss is logically inverted by the inverter INV1, it is supplied to the gate of the n-channel transistor M11. The voltage divider 21 outputs a voltage Vd obtained by dividing the power supply voltage V1 by the resistance elements R11 and R12.

  The comparison unit 22 includes p-channel transistors M12 and M13 and n-channel transistors M14 to M17. The reference voltage Vref is supplied to the gate of the n-channel transistor M14 forming one of the differential pairs. The voltage Vd generated by the voltage divider 21 and obtained by dividing the power supply voltage V1 is supplied to the gate of the n-channel transistor M15 constituting the other of the differential pair. The n-channel transistors M16 and M17 are connected in series. The sleep signal Ss is supplied to the gate of the n-channel transistor M16, and the bias voltage Vb2 is supplied to the gate of the n-channel transistor M17.

  The output unit 23 includes a p-channel transistor M18, n-channel transistors M19 to M21, and an inverter INV2. The p-channel transistor M18 and the n-channel transistors M19 and M20 are connected in series between the power supply line L1 and the ground line L2. The connection between the p-channel transistor M18 and the n-channel transistor M19 is used as the output node N2 of the power supply detection circuit 20, and the power supply detection signal Sd is output from the output node N2. The n-channel transistor M21 has a drain connected to the gate of the p-channel transistor M18, a source connected to the ground line L2, and a gate connected to the output terminal of the inverter INV2. The sleep signal Ss is supplied to the input terminal of the inverter INV2. After the sleep signal Ss is logically inverted by the inverter INV2, it is supplied to the gate of the n-channel transistor M21.

  When a high-level sleep signal Ss instructing the power supply detection circuit 20 to shift to the non-sleep state is supplied, the p-channel transistor M11 and the n-channel transistors M16 and M19 are turned on. On the other hand, when the low-level sleep signal Ss instructing the power supply detection circuit 20 to shift to the sleep state is supplied, the p-channel transistor M11 and the n-channel transistors M16 and M19 are turned off. By turning off the p-channel transistor M11 and the n-channel transistors M16 and M19, a current path passing through each of these transistors is cut off. That is, the p-channel transistor M11 and the n-channel transistors M16 and M19 function as a cutoff circuit that cuts off the current path inside the power supply detection circuit 20 according to the sleep signal Ss.

  When a low-level sleep signal Ss instructing the power supply detection circuit 20 to shift to the sleep state is supplied, the n-channel transistor M21 is turned on, and accordingly, the p-channel transistor M18 is turned on. Become. When the p-channel transistor M18 is turned on, the level of the power supply detection signal Sd output from the output node N2 is maintained at a high level. That is, the p-channel transistor M18 and the n-channel transistor M21 function as a holding circuit that holds the power detection signal Sd at a high level in response to the low-level sleep signal Ss.

  Hereinafter, the operation of the semiconductor memory device 1 will be described. FIG. 4 is a time chart illustrating an example of the operation of the semiconductor memory device 1. When the power supply voltage V1 is applied to the power supply line L1, the semiconductor memory device 1 starts. When the level of the sleep signal Ss is maintained at a high level, each circuit block (the reference voltage generation circuit 10, the power supply detection circuit 20, the drive voltage generation circuit 30, the logic circuit 40, and the level shift circuit) configuring the semiconductor memory device 1 50, the memory circuit 60) is in a non-sleep state, and each circuit block functions effectively.

  When the high-level sleep signal Ss instructing the reference voltage generation circuit 10 to shift to the non-sleep state is supplied, the terminal t1 of the switch SW is connected to the terminal t3. As a result, the gate of the p-channel transistor M6 is connected to the bias line Vb1, the p-channel transistor M6 is turned on, and the current path via the p-channel transistor M6 becomes conductive. As a result, the function of the reference voltage generation circuit 10 becomes effective, and the reference voltage Vref is output from the output node N1.

  When a high-level sleep signal Ss instructing the power supply detection circuit 20 to shift to the non-sleep state is supplied, the p-channel transistor M11 and the n-channel transistors M16 and M19 are turned on. On the other hand, the n-channel transistor M21 is turned off. As a result, the function of the power supply detection circuit 20 is enabled, the voltage Vd obtained by dividing the power supply voltage V1 is compared with the reference voltage Vref, and the power supply detection signal Sd indicating the comparison result is output from the output node N2. I do. When the level of the voltage Vd obtained by dividing the power supply voltage V1 is higher than the level of the reference voltage Vref, the power supply detection circuit 20 outputs a high-level power supply detection signal Sd. On the other hand, when the level of the voltage Vd obtained by dividing the power supply voltage V1 is lower than the level of the reference voltage Vref, the power supply detection circuit 20 outputs a low-level power supply detection signal Sd. The power detection signal Sd is supplied to the logic circuit 40.

  The logic circuit 40 controls the operation of the memory circuit 60 by changing the state of the semiconductor memory device 1 to a reset state or a reset release state based on the level of the power supply detection signal Sd.

  When the high-level sleep signal Ss instructing the drive voltage generation circuit 30 to shift to the non-sleep state is supplied, the function of the drive voltage generation circuit 30 is enabled, and the drive voltage generation circuit 30 generates the drive voltage VDD. The drive voltage VDD is supplied to the level shift circuit 50 and the memory circuit 60.

  The level shift circuit 50 is driven by the drive voltage VDD supplied from the drive voltage generation circuit 30, and shifts the level of the digital signal S1 supplied from the logic circuit 40 in a direction to decrease. The level-shifted digital signal S2 is supplied to the memory circuit 60.

  The memory circuit 60 is driven by the drive voltage VDD supplied from the drive voltage generation circuit 30, and performs, for example, a data write operation and a read operation in response to the received command in the reset release state.

  Thereafter, when the level of the sleep signal Ss transitions to the low level, each circuit block (the reference voltage generation circuit 10, the power supply detection circuit 20, the drive voltage generation circuit 30, the level shift circuit 50, the memory circuit 60) ) Respectively shift to the sleep state, and each circuit block enters the function stop state.

  When the low-level sleep signal Ss instructing the reference voltage generation circuit 10 to shift to the sleep state is supplied, the terminal t1 of the switch SW is connected to the terminal t2. As a result, the gate of the p-channel transistor M6 is connected to the power supply line L1, the p-channel transistor M6 is turned off, and the current path via the p-channel transistor M6 is cut off. As a result, the output of the reference voltage Vref decreases. In the sleep state, the current path via the p-channel transistor M6 is cut off, so that the power consumption of the reference voltage generation circuit 10 is smaller than in the non-sleep state.

  When the low-level sleep signal Ss instructing the power supply detection circuit 20 to shift to the sleep state is supplied, the p-channel transistor M11 and the n-channel transistors M16 and M19 are turned off. On the other hand, the n-channel transistor M21 is turned on. When the p-channel transistor M11 and the n-channel transistors M16 and M19 are turned off, a current path passing through these transistors is cut off. In the sleep state, the current path via the p-channel transistor M11 and the n-channel transistors M16 and M19 is cut off, so that the power consumption in the power supply detection circuit 20 is reduced as compared with the case in the non-sleep state. On the other hand, when the n-channel transistor M21 is turned on, the p-channel transistor M18 is kept on, and as a result, the level of the power detection signal Sd output from the output node N2 is kept at the high level. As described above, the power detection circuit 20 is in the function stop state in the sleep state, but the level of the power detection signal Sd is maintained at the high level.

  When the low-level sleep signal Ss instructing the drive voltage generation circuit 30 to shift to the sleep state is supplied, the drive voltage generation circuit 30 stops its function and stops the output of the drive voltage VDD. When the output of the drive voltage VDD is stopped, power supply to the level shift circuit 50 and the memory circuit 60 is stopped, and the functions of the level shift circuit 50 and the memory circuit 60 are stopped. As a result, the power consumption of the drive voltage generation circuit 30, the level shift circuit 50, and the memory circuit 60 is reduced as compared with the case where the device is in the non-sleep state.

  FIG. 5 is a circuit block diagram illustrating an example of a configuration of a semiconductor memory device 1X according to a first comparative example. FIG. 6 is a circuit diagram illustrating an example of a configuration of the reference voltage generation circuit 10X according to the first comparative example. FIG. 7 is a circuit diagram illustrating an example of a configuration of a power supply detection circuit 20X according to the first comparative example. In the semiconductor memory device 1X according to the first comparative example, the reference voltage generation circuit 10X and the power supply detection circuit 20X do not have a sleep function, and the reference voltage generation circuit 10X and the power supply detection circuit 20X receive a sleep signal Ss. It is configured not to be supplied.

  As illustrated in FIG. 6, the reference voltage generation circuit 10X according to the first comparative example does not include the switch SW included in the reference voltage generation circuit 10 (see FIG. 2) according to the embodiment of the disclosed technology. The gate of the channel transistor M6 is directly connected to the bias line L3.

  As shown in FIG. 7, the power detection circuit 20X according to the first comparative example includes inverters INV1, ONV2, and p-channel transistors M11, n provided in the power detection circuit 20 (see FIG. 3) according to the embodiment of the disclosed technology. It does not include the channel transistors M16, M19 and M21.

  FIG. 8 is a time chart illustrating an example of the operation of the semiconductor memory device 1X according to the first comparative example. In the semiconductor memory device 1X according to the first comparative example, when the sleep signal Ss transitions to a low level, the drive voltage generation circuit 30 stops its function and stops outputting the drive voltage VDD. When the output of the drive voltage VDD is stopped, power supply to the level shift circuit 50 and the memory circuit 60 is stopped, and the functions of the level shift circuit 50 and the memory circuit 60 are stopped. As a result, the power consumption of the drive voltage generation circuit 30, the level shift circuit 50, and the memory circuit 60 is reduced as compared with the case where the device is in the non-sleep state.

  On the other hand, the functions of the reference voltage generation circuit 10X and the power supply detection circuit 20X are enabled in the sleep state as well as in the non-sleep state. Therefore, the power consumption of the reference voltage generation circuit 10X and the power detection circuit 20X is substantially the same as when these circuits are in the non-sleep state.

  As described above, according to the semiconductor memory device 1X according to the first comparative example, since the reference voltage generation circuit 10X and the power supply detection circuit 20X do not have the sleep function, the power consumption is sufficiently reduced in the sleep state. It is difficult to obtain the effect.

  On the other hand, according to the semiconductor memory device 1 according to the embodiment of the disclosed technology, not only the drive voltage generation circuit 30 but also the reference voltage generation circuit 10 and the power supply detection circuit 20 have a sleep function. Therefore, it is possible to obtain a sufficient power consumption reduction effect.

  FIG. 9 is a circuit block diagram illustrating an example of a configuration of a semiconductor memory device 1Y according to a second comparative example. FIG. 10 is a circuit diagram showing an example of the configuration of the power supply detection circuit 20Y provided in the semiconductor memory device 1Y.

  The power detection circuit 20Y according to the second comparative example has a p-channel transistor M11 and an n-channel transistor M16 for realizing a sleep function. On the other hand, the power supply detection circuit 20Y according to the second comparative example does not include the inverter INV2 and the n-channel transistor M21 included in the power supply detection circuit 20 (see FIG. 3) according to the embodiment of the disclosed technology. That is, the power detection circuit 20Y according to the second comparative example does not include a holding circuit that holds the level of the power detection signal Sd at a high level in response to the low-level sleep signal Ss. The configuration of the reference voltage generation circuit 10 according to the second comparative example is the same as that of the reference voltage generation circuit 10 (see FIG. 2) according to the embodiment of the disclosed technology.

  FIG. 11 is a time chart illustrating an example of the operation of the semiconductor memory device 1Y according to the second comparative example. In the semiconductor memory device 1Y according to the second comparative example, when the sleep signal Ss transitions to a low level, the reference voltage generation circuit 10Y, the power supply detection circuit 20Y, and the drive voltage generation circuit 30 are each in the sleep state. Thereby, it is possible to obtain a sufficient power consumption reduction effect. However, the power supply detection circuit 20Y according to the second comparative example does not include a holding circuit that holds the level of the power supply detection signal Sd at the high level in the sleep state. Become. When the power detection signal Sd becomes low level, the logic circuit 40 changes the state of the semiconductor memory device 1Y to the reset state. In the reset state, the logic circuit 40 stops accepting a command input supplied from the outside. Since the logic circuit 40 also stops accepting a command input instructing release of the sleep state, the sleep state cannot be released.

  As described above, according to the semiconductor memory device 1Y according to the second comparative example, when the power supply detection circuit 20Y shifts to the sleep state, the semiconductor memory device 1Y is reset and the operation control of the semiconductor memory device 1Y becomes impossible. .

  On the other hand, according to the semiconductor memory device 1 according to the embodiment of the disclosed technology, the power detection circuit 20 includes the holding circuit that holds the level of the power detection signal Sd at the high level in the sleep state. This can prevent the semiconductor memory device 1 from being reset when the power supply detection circuit 20 shifts to the sleep state. That is, according to the semiconductor storage device 1 according to the embodiment of the disclosed technology, it is possible to avoid occurrence of an operation failure due to stopping a function of a specific circuit block by the sleep function.

  In the above description, the case where the level of the power supply voltage V1 is higher than the predetermined level corresponds to the high level of the power supply detection signal Sd, and the case where the level of the power supply voltage V1 is higher than the predetermined level corresponds to the case where the power supply detection signal Sd However, the present invention is not limited to this mode. The correspondence between the level of the power supply voltage V1 and the level of the power supply detection signal Sd may be opposite to the above. In the above description, the non-sleep state corresponds to the high level of the sleep signal Ss, and the sleep state corresponds to the low level of the sleep signal Ss. However, the present invention is not limited to this mode. The correspondence between the non-sleep state and the sleep state and the level of the sleep signal Ss may be opposite to the above.

  Note that the semiconductor storage device 1 is an example of a semiconductor storage device according to the disclosed technology. The reference voltage generation circuit 10 is an example of a reference voltage generation circuit according to the disclosed technology. The power supply detection circuit 20 is an example of a power supply detection circuit according to the disclosed technology. The drive voltage generation circuit 30 is an example of a drive voltage generation circuit according to the disclosed technology. The logic circuit 40 is an example of a logic circuit according to the disclosed technology. The memory circuit 60 is an example of a memory circuit according to the disclosed technology. The p-channel transistor M11 and the n-channel transistors M16 and M19 are examples of a first cutoff circuit according to the disclosed technology. The switch SW and the p-channel transistor M6 are examples of a second cutoff circuit according to the disclosed technology. The p-channel transistor M18 and the n-channel transistor M21 are examples of a holding circuit according to the disclosed technology. The power detection signal Sd is an example of a power detection signal according to the disclosed technology. The sleep signal Ss is an example of a control signal according to the disclosed technology.

  Regarding the above embodiments, the following supplementary notes are further disclosed.

(Appendix 1)
A power detection signal of a first level is output when the level of the power supply voltage supplied to the power supply line is higher than a predetermined level, and the first level is output when the level of the power supply voltage is lower than the predetermined level. Outputs a power detection signal of a different second level, interrupts an internal current path in response to a supplied control signal, and sets the level of the power detection signal in response to the control signal. A power supply detection circuit comprising: a holding circuit for holding at a first level;
A memory circuit having a plurality of memory cells,
A logic circuit that controls the memory circuit based on a level of the power detection signal;
Semiconductor storage device including:

(Appendix 2)
A reference voltage generation circuit including a second cutoff circuit that generates the reference voltage of the predetermined level used for level determination of the power supply voltage in the power supply detection circuit and cuts off an internal current path according to the control signal; The semiconductor memory device according to claim 1.

(Appendix 3)
3. The semiconductor memory device according to claim 2, further comprising a drive voltage generation circuit that generates a drive voltage for driving the memory circuit and stops generation of the drive voltage in response to the control signal.

(Appendix 4)
When the control signal indicates a transition to a sleep state,
The first cutoff circuit cuts off a current path inside the power supply detection circuit,
The holding circuit holds a level of the power detection signal at the first level,
The second cutoff circuit cuts off a current path inside the reference voltage generation circuit,
4. The semiconductor memory device according to claim 3, wherein the drive voltage generation circuit stops generating the drive voltage.

(Appendix 5)
5. The semiconductor memory according to claim 1, wherein the logic circuit changes a state of the semiconductor storage device to a reset state in which command input is not accepted in response to a second level power supply detection signal. apparatus.

(Appendix 6)
The holding circuit includes: a first transistor connected to a first output node from which the power detection signal is output; and a second transistor connected to a gate of the first transistor;
6. The semiconductor memory device according to claim 1, wherein a signal corresponding to the control signal is supplied to a gate of the second transistor.

(Appendix 7)
7. The semiconductor memory device according to claim 6, wherein the first cutoff circuit includes a third transistor connected to the first output node and having a gate supplied with a signal corresponding to the control signal.

(Appendix 8)
The second cutoff circuit includes a fourth transistor connected to a second output node from which the reference voltage is output, and a switch for switching a gate voltage of the fourth transistor. The semiconductor memory device according to any one of the above.

1, 1X, 1Y Semiconductor memory device 10, 10X Reference voltage generation circuit 20, 20X, 20Y Power supply detection circuit 30 Drive voltage generation circuit 40 Logic circuit 50 Level shift circuit 60 Memory circuit SW Switch Sd Power supply detection signal Ss Sleep signal V1 Power supply voltage L3 Bias line Vb1 Bias voltage Vb2 Bias voltage Vd Voltage VDD Drive voltage Vref Reference voltage

Claims (4)

A power detection signal of a first level is output when the level of the power supply voltage supplied to the power supply line is higher than a predetermined level, and the first level is output when the level of the power supply voltage is lower than the predetermined level. Outputs a power detection signal of a different second level, interrupts an internal current path in response to a supplied control signal, and sets the level of the power detection signal in response to the control signal. A power supply detection circuit comprising: a holding circuit for holding at a first level;
A memory circuit having a plurality of memory cells,
A logic circuit that controls the memory circuit based on a level of the power detection signal;
Semiconductor storage device including: A reference voltage generation circuit including a second cutoff circuit that generates the reference voltage of the predetermined level used for level determination of the power supply voltage in the power supply detection circuit and cuts off an internal current path according to the control signal; The semiconductor memory device according to claim 1. The semiconductor memory device according to claim 2, further comprising: a drive voltage generation circuit that generates a drive voltage for driving the memory circuit and stops generation of the drive voltage according to the control signal. When the control signal indicates a transition to a sleep state,
The first cutoff circuit cuts off a current path inside the power supply detection circuit,
The holding circuit holds a level of the power detection signal at the first level,
The second cutoff circuit cuts off a current path inside the reference voltage generation circuit,
The semiconductor memory device according to claim 3, wherein the drive voltage generation circuit stops generating the drive voltage.