JP2026007731A - Circuit verification device and circuit verification method - Google Patents

Abstract

A circuit verification apparatus and method for accurately verifying a circuit including a programmable device are provided.
[Solution] In a circuit verification device, a verification unit verifies a circuit using a netlist and design information for each IC. The design information includes attribute information describing attributes of each terminal and internal circuit information describing internal circuits connected to each terminal within the IC. When a first terminal of a first IC is specified, the verification unit also detects a second terminal of a second IC electrically connected to the first terminal based on the netlist, identifies a circuit portion to be verified, determines whether the first terminal and the second terminal may be electrically connected based on the attribute information related to the first terminal and the attribute information related to the second terminal, and determines whether resistors are correctly provided in the circuit portion to be verified based on the netlist, the attribute information and internal circuit information related to the first terminal, and the attribute information and internal circuit information related to the second terminal.
[Selected figure] Figure 5

Description

The present invention relates to an apparatus and method for verifying circuits including programmable devices.

When manufacturing various devices, the designed circuits are verified in advance. Meanwhile, in recent years, various devices often use programmable devices to increase design flexibility. Programmable devices have internal configurations that can be set by the user. Therefore, circuit verification takes into account the internal configuration of the programmable device. A method has been proposed for checking the consistency between the internal and external resistances of a programmable logic device (PLD) during circuit design (see, for example, Patent Document 1).

Japanese Patent Application Laid-Open No. 2020-095607

Conventional technology (for example, the method described in Patent Document 1) can detect overlapping or missing pull-up/pull-down resistors, but it cannot verify circuits based on the attributes of each terminal of each integrated circuit (IC). For this reason, it is difficult to accurately verify whether a circuit including a programmable device is properly designed using conventional technology.

An object of one aspect of the present invention is to provide an apparatus and method capable of accurately verifying circuits including programmable devices.

A circuit verification device according to one aspect of the present invention verifies a target circuit including multiple ICs. The circuit verification device includes a first storage unit that stores netlist information representing connections between the multiple ICs, a second storage unit that stores design information for each of the multiple ICs, and a verification unit that verifies the target circuit based on the netlist information and the design information for each of the multiple ICs. The design information includes, for each of the multiple ICs, attribute information representing attributes of each terminal of the IC and internal circuit information representing internal circuits connected to each terminal within the IC. When a first terminal of a first IC of the multiple ICs is specified, the verification unit detects a second terminal of a second IC of the multiple ICs that is electrically connected to the first terminal based on the netlist information. The verification unit detects a portion of the target circuit that is electrically connected to the first terminal based on the netlist information, the internal circuit information related to the first terminal, and the internal circuit information related to the second terminal. The verification unit performs a first determination based on the attribute information related to the first terminal and the attribute information related to the second terminal to determine whether the first terminal and the second terminal may be electrically connected. The verification unit performs a second determination based on the netlist information, the attribute information and internal circuit information related to the first terminal, and the attribute information and internal circuit information related to the second terminal to determine whether resistors are correctly provided in the circuit portion to be verified.

The above-described aspects enable accurate verification of circuits including programmable devices.

FIG. 1 illustrates an example of a circuit to be verified. FIG. 1 illustrates an example of a programmable device. 1 is a diagram illustrating an example of a circuit verification device according to an embodiment of the present invention. FIG. 2 is a diagram illustrating an example of design information of a programmable device. FIG. 10 illustrates an example of verification by a circuit verification device. FIG. 10 is a diagram illustrating an example of a validation rule. FIG. 10 is a diagram (part 1) showing an example of a verification result obtained by the circuit verification device; FIG. 10 is a diagram (part 2) showing an example of a verification result obtained by the circuit verification device; FIG. 10 is a diagram illustrating an example of a circuit format used when verifying a circuit. 10A and 10B are diagrams illustrating examples of display of a verification form and verification results. 10 is a flowchart illustrating an example of a method for registering design information. 10 is a flowchart illustrating an example of processing performed by the circuit verification device. FIG. 10 is a diagram (part 1) showing an example of a procedure for writing necessary information into a verification form. FIG. 10 is a diagram (part 2) showing an example of a procedure for writing necessary information into a verification form. FIG. 10 is a diagram (part 3) showing an example of a procedure for writing necessary information into a verification form. 10 is a flowchart showing an outline of a verification process performed by a verification unit. 10 is a flowchart illustrating an example of a process for verifying a signal name. 10 is a flowchart illustrating an example of a verification process related to an output terminal. 10 is a flowchart illustrating an example of a verification process related to an open-drain input terminal. 10 is a flowchart illustrating an example of a verification process related to an open drain terminal. 10 is a flowchart illustrating an example of a verification process related to a bidirectional terminal. 10 is a flowchart showing an example of a verification process related to an input terminal. FIG. 1 illustrates an example of a hardware configuration of a circuit verification apparatus.

Figure 1 shows an example of a circuit to be verified. In this example, the circuit to be verified comprises three integrated circuits (IC1 to IC3). Terminal B3 of IC1, terminal A2 of IC2, and terminal 4 of IC3 are electrically connected to each other. In addition, a pull-up resistor is provided on the signal line connecting terminal B3 of IC1, terminal A2 of IC2, and terminal 4 of IC3 to each other.

IC1 and IC2 are both programmable devices. That is, IC1 and IC2 each have internal configuration that can be set by the user. Therefore, the user can assign signal names to each terminal of IC1 and IC2 as needed. In this example, the signal name "IO04" is assigned to terminal B3 of IC1, and the signal name "GPIO1_0" is assigned to terminal A2 of IC2. IC3 is a non-programmable device, and the signal names of each terminal are preset by the IC manufacturer. In this example, terminal 4 of IC3 is assigned the signal name "ADDR3." Furthermore, the user assigns the signal name "ADDR[3]" to the signal line (or the signal propagating via that signal line) connecting terminal B3 of IC1, terminal A2 of IC2, and terminal 4 of IC3 to each other.

IC1 is, for example, an FPGA (Field Programmable Gate Array). IC2 is, for example, an SoC (System on Chip) or a CPU (Central Processing Unit). IC3 is, for example, a memory chip.

Figure 2 shows an example of a programmable device. In this example, IC1 and IC2 are programmable devices. A programmable device has internal configurations that can be set by the user.

Connected to the B3 terminal of IC1 are switches S1 and S2, resistors R1 and R2, a buffer BUF, and a tri-state buffer TRIBUF with an OE (Output Enable) terminal. The user can set the on/off states of switches S1 and S2. For example, to pull up the B3 terminal, set switch S1 to the on state and switch S2 to the off state. To pull down the B3 terminal, set switch S1 to the off state and switch S2 to the on state. To fix the B3 terminal to a specified voltage, set switches S1 and S2 to the on state. Note that switches S1 and S2 can also be set to the off state. The user can also set the states of BUF and TRIBUF according to the terminal attributes. For example, when using the B3 terminal as an input terminal, enable BUF and disable TRIBUF. When using the B3 terminal as an output terminal, disable BUF and enable OE at all times to enable TRIBUF. When using the B3 terminal as a bidirectional terminal, enable BUF and make it possible to control the OE terminal of TRIBUF using user logic.

As such, when a circuit includes a programmable device, the internal configuration of the programmable device must also be taken into consideration when verifying the circuit. For example, in the example shown in Figure 2, signal line ADD[3] is pulled up by resistor R3. Now, let's assume that switch S1 in IC1 is set to the on state and switch S2 is set to the off state. In other words, the B3 terminal of IC1 is pulled up by its internal circuit. In this case, the pull-up resistor is duplicated, and the circuit design is determined to be inappropriate.

As the scale of a circuit increases, it is common for multiple people to share the design work of a single circuit. For example, different designers may be responsible for the design of each IC. This can result in, for example, overlapping or unconnected pull-up/pull-down resistors, as described above. Therefore, there is a need for an apparatus and method that can accurately verify circuits that include programmable devices.

Figure 3 shows an example of a circuit verification device according to an embodiment of the present invention. As shown in Figure 3, the circuit verification device 10 according to an embodiment of the present invention includes a netlist storage unit 1, a device design information storage unit 2, a verification unit 3, and a display unit 4. Note that the circuit verification device 10 may also include other functions not shown in Figure 3.

The netlist of the circuit to be verified is stored in the netlist storage unit 1. The netlist represents the connections between the terminals of the components in the circuit. For example, the netlist of the circuit shown in FIG. 2 includes the following connection information:
(1) The B3 terminal of IC1 is connected to the A2 terminal of IC2, the 4th terminal of IC3, and the 2nd terminal of resistor R3.
(2) Connect terminal 1 of resistor R3 to the power supply.

The netlist is written, for example, in HDL (Hardware Description Language). Alternatively, the netlist can be obtained by converting code written in HDL.

The device design information storage unit 2 stores design information for each device used in the circuit under verification. This design information includes signal name information indicating the signal names assigned to the signal lines within the device connected to each terminal, attribute information indicating the attributes of each terminal, and internal circuit information indicating the internal circuits connected to each terminal. Design information for programmable devices is created by the user. For example, design information for FPGAs is created using a place and route tool in accordance with user instructions. Design information for SoCs (CPUs) is created using a PinMux design tool in accordance with user instructions, for example. Design information for non-programmable devices can be used by creating a unique library from data sheets provided by the manufacturer.

Figure 4 shows an example of design information for a programmable device. The design information includes information representing terminal numbers, signal names, attributes, and pull resistors. "Terminal numbers" identify each terminal of the device. Note that in devices with multiple terminals arranged two-dimensionally, such as BGA (Ball Grid Array) modules, the terminal numbers may be positional information representing the coordinates of the locations of each terminal. "Signal names" represent names assigned by the user in programmable devices. For example, in FPGAs, signal names correspond to names written in HDL. In SoCs (CPUs), signal names correspond to names selected by the user from among multiple names provided by the device manufacturer.

"Attribute" indicates whether the terminal is an output terminal, open-drain input terminal, open-drain terminal, bidirectional terminal, or input terminal. "Pull resistor" indicates whether a pull resistor is provided, and if a pull resistor is provided, identifies it as a pull-up resistor, pull-down resistor, or KEEPER circuit. A KEEPER circuit is an example of a voltage holding circuit. Note that "Pull resistor" is an example of internal circuit information that indicates the internal circuit connected to each terminal within the IC.

The design information may also include other information. For example, the design information may include information representing the output drive current, output load capacitance, input capacitance, etc. for each terminal of the IC.

It may be necessary to verify whether the circuit design is valid before the circuit diagram is completed. For example, it may be necessary to verify a circuit including an FPGA during the design stage of that FPGA. Therefore, it is assumed that the design information for the programmable device can be manually entered by the user. Furthermore, even if some items of the design information are not set, it is preferable that the circuit verification device 10 be able to verify the circuit by leaving those items blank.

The verification unit 3 verifies the circuit under verification based on the netlist of the circuit under verification stored in the netlist storage unit 1 and the design information for each device stored in the device design information storage unit 2. At this time, the verification unit 3 may verify, for each terminal of each device, whether the circuit has been designed in accordance with the verification rules.

The display unit 4 displays the verification results obtained by the verification unit 3. At this time, the display unit 4 may highlight any violations of the verification rules. For example, cases where multiple pull-up resistors are provided redundantly for a single signal line, or cases where a required pull-up resistor is not provided for a signal line, may be highlighted. The display unit 4 may also highlight any content that requires attention. For example, cases where the same signal is given different signal names between devices may be highlighted.

Figure 5 shows an example of verification by the circuit verification device 10. In this example, verification is performed on the circuit under verification shown in Figure 5A. In the circuit under verification, terminal A3 of IC1, terminal H6 of IC2, and terminal 5 of IC3 are connected to each other, and the signal line connecting these terminals is given the signal name "GPMC_D[8]". This signal line is also pulled up by resistor R100.

The A3 terminal of IC1 is a bidirectional terminal, and its signal name is "DATA[8]". The H6 terminal of IC2 is a bidirectional terminal, and its signal name is "GPMC_D08". The H6 terminal is also pulled up within IC2. The 5th terminal of IC3 is a bidirectional terminal, and its signal name is "D08".

Figure 5B shows the results of verification performed on the A3 terminal of IC1. By referencing the netlist, the verification unit 3 of the circuit verification device 10 recognizes that the A3 terminal of IC1, the H6 terminal of IC2, and the 5th terminal of IC3 are connected to each other and that the signal line connecting these terminals is pulled up by resistor R100. The verification unit 3 also acquires design information for the A3 terminal of IC1, the H6 terminal of IC2, and the 5th terminal of IC3. The verification unit 3 then verifies whether the circuit under verification has been designed in accordance with the verification rules based on the netlist of the circuit under verification and the design information of each IC.

Figure 6 shows an example of a verification rule. This example shows the error/warning conditions for multi-function (programmable) terminals of a CMOS device. Furthermore, power supply terminals, GND terminals, and dedicated terminals (clock, SerDes, etc.) are excluded from the attributes of the starting terminal.

The validation rules include rule information that indicates combinations of terminal attributes that must not be electrically connected to each other. The validation rules also include rule information that indicates the resistor circuits (pull-up resistors, pull-down resistors, keeper circuits) required for each terminal attribute. The validation rules also include rule information that indicates the resistor circuits that must not be provided for each terminal attribute.

For example, the first rule regarding output terminals states that if one of multiple terminals that are connected to each other is an output terminal, all other terminals must be input terminals. If this rule is violated, the verification unit 3 outputs an error message.

The second rule, which concerns output terminals, states that if one of multiple interconnected terminals is an output terminal, two or more pull-up resistors must not be provided in the circuit containing these terminals. If this rule is violated, the verification unit 3 will also output an error message.

In the example shown in Figure 5, verification is being performed on the A3 terminal of IC1. Here, as shown in Figure 5A, the A3 terminal of IC1 is a bidirectional terminal. The other terminals (terminal H6 of IC2 and terminal 5 of IC3) are also bidirectional terminals. Therefore, the attributes of these three terminals do not violate the verification rules. However, the signal line electrically connected to the A3 terminal of IC1 is provided with pull-up resistor R100 and pull-up resistor Up. In other words, the pull-up resistors are duplicated. Therefore, the verification unit 3 determines that the resistor connection violates the verification rules, and the display unit 4 highlights pull-up resistor R100 and pull-up resistor Up connected to terminal H6 within IC2, as shown in Figure 5B.

In addition, different signal names are assigned to the signals propagating through these signal lines for each device. Therefore, the display unit 4 highlights the signal names used within each device, as shown in Figure 5.

The user (circuit designer) can examine the validity of the circuit under verification by referring to the verification results displayed on the display unit 4. In the example shown in Figure 5, the overlapping pull-up resistors are recognized as a design error. The user then deletes one of the overlapping pull-up resistors (e.g., resistor R100) and re-verifies the circuit under verification. In this case, the error message related to the overlapping pull-up resistors is no longer output.

The verification results also allow users to recognize when different signal names are used for the same signal across devices. This allows users to change signal names as needed.

Figures 7 and 8 show examples of verification results by the circuit verification device 10. Note that in the examples shown in Figures 7 and 8, verification related to the consistency of signal names will not be described.

In the case shown in Figure 7A, terminal A3 of IC1, terminal H6 of IC2, and terminal 5 of IC3 are connected to each other. These terminals are all bidirectional terminals. The signal line electrically connected to terminal A3 of IC1 must not have a pull-up resistor, pull-down resistor, or KEEPER circuit.

According to the verification rules, signal lines connected to bidirectional terminals must be equipped with either a pull-up resistor, pull-down resistor, or KEEPER circuit. Therefore, in this case, an error message is output indicating that a pull-up resistor, pull-down resistor, or KEEPER circuit is not installed. In addition, an "X" mark is displayed in the location where a resistor circuit (pull-up, pull-down, or KEEPER) should be installed.

In the case shown in Figure 7B, terminal A3 of IC1, terminal H6 of IC2, and terminal 5 of IC3 are connected to each other. These terminals are all bidirectional terminals. In IC1, the internal circuit connected to terminal A3 includes a KEEPER circuit (V-Keeper). In IC2, the internal circuit connected to terminal H6 includes a pull-up resistor.

The validation rules prohibit signal lines connected to bidirectional terminals from having two or more of the following: pull-up resistors, pull-down resistors, or KEEPER circuits. Therefore, in this case, an error message is output indicating that the signal line has two or more of the following: pull-up resistors, pull-down resistors, or KEEPER circuits. The parts that violate the validation rules are also highlighted.

In the case shown in Figure 8A, the C2 terminal of IC1, the D9 terminal of IC2, and the 5th terminal of IC3 are connected to each other. The D9 terminal of IC2 is an output terminal, and the C2 terminal of IC1 and the 5th terminal of IC3 are input terminals. A pull-up resistor R101 is provided on the signal line connecting to these terminals.

According to the verification rules, it is necessary to consider whether to install a pull-up resistor, pull-down resistor, or KEEPER circuit on the signal line connected to the output terminal (in Figure 8, terminal D9 of IC2). Therefore, in this case, a warning message is output stating that a pull-up resistor is installed.

In the case shown in Figure 8B, the C2 terminal of IC1, the D9 terminal of IC2, and the 5th terminal of IC11 are connected to each other. The D9 terminal of IC2 is an input terminal, and the C2 terminal of IC1 and the 5th terminal of IC11 are open-drain terminals. The signal lines connected to these terminals do not have pull-up resistors, pull-down resistors, or KEEPER circuits.

According to the verification rules, a pull-up resistor must be installed on the signal line connected to the open drain terminal. Therefore, in this case, an error message indicating that there is no pull-up resistor is output. In addition, an "X" mark is displayed in the location where the pull-up resistor should be installed.

In this way, the circuit verification device 10 takes into account the attributes of the terminals when verifying whether the circuit configuration of each terminal of each device that makes up the circuit under verification is correct. Therefore, the circuit verification device 10 not only checks for overlapping pull-up or pull-down resistors, but also verifies the appropriateness of providing or not providing pull-up resistors, pull-down resistors, or KEEPER circuits for signal lines connected to each terminal. In other words, circuits that include programmable devices can be verified with high accuracy.

Figure 9 shows an example of a circuit format used when verifying a circuit. In this circuit format, multiple devices are electrically connected to one another. That is, the P1 terminal of IC1, the P2 terminal of IC2, the P3 terminal of IC3, and the P9 terminal of IC9 are electrically connected to one another. A pull-up resistor Rup and a pull-down resistor Rdn can be provided on the signal line connecting these terminals. Providing both a pull-up resistor Rup and a pull-down resistor Rdn forms a KEEPER circuit. Damping resistors (Rdu_1 to Rdu_9) can be provided between the set points of the pull-up resistor Rup/pull-down resistor Rdn and each device (IC1 to IC9). Note that Net_0 to Net_9 represent variables for inputting signal names.

The circuit verification device 10 creates a verification form by incorporating the netlist of the circuit to be verified and the design information of each device into this circuit format. The verification form is implemented, for example, using general spreadsheet software, and is used to verify the circuit. Furthermore, the verification form can display the verification results.

Figure 10 shows an example of the verification form and verification results. In this example, the A3 terminal of IC1 shown in Figure 5A is specified, and a verification form corresponding to the circuit electrically connected to that terminal is created.

In this case, by acquiring the netlist of the circuit under verification, the circuit verification device 10 recognizes that a pull-up resistor R100 is provided on the signal line connected to the A3 terminal of IC1. Therefore, as shown in Figure 10, resistor R100 is displayed for pull-up resistor Rup, and "none" is displayed for pull-down resistor Rdn. Furthermore, resistor R10 is displayed as damping resistor Rdu_1.

The circuit verification device 10 acquires design information for the selected terminal (here, terminal A3 of IC1) and the terminals of other devices that are electrically connected to the selected terminal (here, terminal H6 of IC2 and terminal 5 of IC3). Then, as shown in Figure 10, the circuit verification device 10 enters the acquired design information into a verification form. At this time, at least the part number, terminal number, signal name, attribute, and pull resistor are entered. Note that "pull resistor" indicates the presence or absence of a pull-up resistor, pull-down resistor, and KEEPER circuit within the device. The verification form shown in Figure 10 indicates that a pull-up resistor is provided at terminal H6 of IC2.

In this example, the selected terminal (i.e., terminal A3 of IC1) is a bidirectional terminal. Therefore, the circuit verification device 10 verifies the three items for "Bidirectional" shown in Figure 6. First, the other terminals (i.e., terminal H6 of IC2 and terminal 5 of IC3) are both bidirectional terminals, so they do not violate the first item. Next, the signal line electrically connected to terminal A3 of IC1 is equipped with pull-up resistors R100 and Up, which violates the second item (design error). Therefore, as shown in Figure 10, pull-up resistors R100 and Up are each highlighted. As an example, pull-up resistors R100 and Up may be displayed in red. Furthermore, the signal line electrically connected to terminal A3 of IC1 is equipped with pull-up resistors, so they do not violate the third item.

In addition to the above verification, the circuit verification device 10 may also verify signal names. In this example, different signal names are assigned to the same signal or signal line within each device. Therefore, as shown in FIG. 10, the signal names are highlighted. However, even if the signal names do not match, the circuit will operate correctly if the design itself is correct. In other words, a mismatch in signal names is less important than a design error. Therefore, a mismatch in signal names is displayed in a different color (e.g., green) than cases where a design error has occurred.

Figure 11 is a flowchart showing an example of a method for registering design information. The processing of this flowchart is executed, for example, when a circuit to be verified is specified by a user.

In S1, the circuit verification device 10 acquires a netlist of the circuit under verification and stores it in the netlist storage unit 1. The netlist represents the connections between components within the circuit under verification. Therefore, the netlist describes all devices within the circuit under verification.

In S2, the circuit verification device 10 references the netlist and selects one of the devices in the circuit to be verified. At this time, it may select an IC to be verified as a set with the internal circuit of the programmable device.

In S3, the circuit verification device 10 checks whether it can acquire the design information (report file) output from the design tool for the device selected in S2. If the design information can be acquired, in S4 the circuit verification device 10 sets a part number for the device selected in S2. In the example shown in FIG. 4, for example, "IC1" is set. Next, in S5, the circuit verification device 10 reads the design information for the device selected in S2 and stores it in the device design information storage unit 2 in association with the part number set in S4.

If design information cannot be obtained from the design tool, the circuit verification device 10 checks in S6 whether design information created by the user for the device selected in S2 can be obtained. If design information can be obtained, the circuit verification device 10 sets a part number for the device selected in S2 in S7. Next, in S8, the circuit verification device 10 reads the design information for the device selected in S2 and stores it in the device design information storage unit 2 in association with the part number set in S7.

If neither the design information output by the design tool nor the design information created by the user can be obtained, the circuit verification device 10 terminates processing. In this case, the user must create design information for each device.

In S9, the circuit verification device 10 determines whether any unselected devices remain. If so, the circuit verification device 10 returns to S2. That is, it executes the processes of S3 to S8 for each device in the circuit under verification. Once design information for all devices has been acquired and stored in the device design information storage unit 2, the circuit verification device 10 proceeds to the verification procedure.

Figure 12 is a flowchart showing an example of processing by the circuit verification device 10. Note that before executing the processing of this flowchart, the necessary information is registered in the netlist storage unit 1 and the device design information storage unit 2 according to the procedure shown in Figure 11, and the circuit format shown in Figure 9 is prepared in advance. The user then specifies the desired device (here, the desired IC) in the circuit to be verified.

In S11, the verification unit 3 selects one of the multiple terminals provided by the specified device. In the following description, the terminal selected in S11 may be referred to as the "target terminal."

In S12, the verification unit 3 determines whether the target terminal is a power terminal, a GND terminal, or a specified dedicated terminal (e.g., clock, SerDes). If the target terminal is a power terminal, a GND terminal, or a specified dedicated terminal, in S13 the verification unit 3 registers the terminal number identifying the target terminal in a list of unchecked terminals (not shown). After this, the status of the target terminal is managed as "checked."

If the target terminal is not a power supply terminal, GND terminal, or a specified dedicated terminal, the verification unit 3, in S14, references the netlist and detects other devices and resistors electrically connected to the target terminal. Note that in the description of this flowchart, "other devices" refers to devices other than the specified device. Furthermore, "electrically connected to the target terminal" includes a configuration in which the device is connected via a conductor pattern such as a signal line, and a configuration in which the device is connected via a damping resistor. For example, in the example shown in Figure 5A, the target terminal is assumed to be the A3 terminal of IC1. In this case, the H6 terminal of IC2, terminal 5 of IC3, resistor R100 used as a pull-up resistor, and resistor R10 used as a damping resistor are detected.

In S15, the verification unit 3 determines whether the circuit portion electrically connected to the target terminal conforms to the circuit format shown in FIG. 9. The circuit portion electrically connected to the target terminal consists of the device that includes the target terminal (i.e., the device specified by the user) and the other devices and resistors detected in S14. For example, in the example shown in FIG. 5A, if the target terminal is the A3 terminal of IC1, the H6 terminal of IC2, the 5th terminal of IC3, resistor R100, and resistor R10 correspond to the P2 terminal of IC2, the P3 terminal of IC3, resistor Rup, and resistor Rdu_1, respectively, and therefore it is determined that the circuit portion electrically connected to the target terminal conforms to the circuit format shown in FIG. 9.

If the circuit portion electrically connected to the target terminal does not conform to the circuit format shown in Figure 9, the verification unit 3 registers the terminal number identifying the target terminal in an out-of-format terminal list (not shown) in S16. After this, the status of the target terminal is managed as "checked."

If the circuit portion electrically connected to the target terminal conforms to the circuit format shown in FIG. 9, then in S17 the verification unit 3 writes component information representing the component detected in S14 into the verification form. Next, in S18, the verification unit 3 copies the design information for each device (i.e., the IC including the target terminal and other ICs detected in S14) from the device design information storage unit 2 into the verification form.

For example, consider the case where the A3 terminal of IC1 shown in Figure 5A is selected as the target terminal. Here, the verification form is initialized as shown in Figure 13. This state corresponds to the circuit format shown in Figure 9. When the A3 terminal of IC1 is selected as the target terminal, the device (IC1) that includes the target terminal, other devices (IC2, IC3) detected in S14, and resistors (R100, R10) detected in S14 are written into the verification form, as shown in Figure 14. At this time, the signal names are also written into the verification form. Next, as shown in Figure 15, the design information for each device is copied from the device design information storage unit 2 to the verification form.

Once the necessary information has been entered into the verification form as described above, the verification unit 3 executes the verification process in S19. The verification process will be explained in detail later.

In S20, the verification unit 3 checks whether any unchecked terminals remain. If any unchecked terminals remain, the verification unit 3 returns to S11. That is, the verification unit 11 performs steps S12 to S19 on the next terminal of the specified device. When steps S12 to S19 have been performed on all terminals of the specified device, the verification unit 3 terminates its processing.

Figure 16 is a flowchart showing an overview of the verification process performed by the verification unit 3. This process corresponds to S19 in the flowchart shown in Figure 12.

In S31, the verification unit 3 verifies the signal names. In S32, the verification unit 3 verifies the circuit based on verification rules related to output terminals. In S33, the verification unit 3 verifies the circuit based on verification rules related to open-drain input terminals. In S34, the verification unit 3 verifies the circuit based on verification rules related to open-drain terminals. In S35, the verification unit 3 verifies the circuit based on verification rules related to bidirectional terminals. In S36, the verification unit 3 verifies the circuit based on verification rules related to input terminals. Note that the procedure shown in FIG. 16 is an example, and the verification unit 3 may execute the processes of S31 to S36 in any order.

Figure 17 is a flowchart showing an example of a process for verifying a signal name. The process in this flowchart corresponds to S31 shown in Figure 16. This process is also performed on the circuit portion that is electrically connected to the target terminal. In the following description, the circuit portion that is electrically connected to the target terminal may be referred to as the "target circuit portion."

In S41, the verification unit 3 references the verification form in which the necessary information has been entered and compares one or more signal names assigned to signal lines connecting devices in the target circuit portion with the signal names used within each device. If these signal names match, the verification unit 3 outputs a normal message in S52 indicating that there is no problem with the signal name settings. On the other hand, if these signal names do not match, the verification unit 3 outputs a warning message in S53 indicating that there is a problem with the signal name settings. The normal message and warning message may be displayed on the verification form. In the example shown in Figure 10, the signal names do not match, so the warning message "W: Signal names differ" is displayed. "W" stands for warning.

Figure 18 is a flowchart showing an example of verification processing related to output terminals. The processing in this flowchart corresponds to S32 shown in Figure 16 and is executed when the target circuit portion includes an output terminal.

In S51, the verification unit 3 references the design information for each device and determines whether any terminals other than input terminals exist within the target circuit portion. When checking the attributes of each terminal, the verification unit 3 extracts the value entered as "attribute" in the verification form. This procedure is the same in Figures 18 to 22.

Here, if an output terminal exists within the target circuit portion, the other terminals must be input terminals. Therefore, if a terminal other than an input terminal exists within the target circuit portion, the verification unit 3 outputs an attribute error message in S52. In this case, the verification unit 3 may display "E: Includes terminals other than input terminals" as the attribute error message. "E" indicates an error. On the other hand, if all terminals except the target terminal are input terminals, the verification unit 3 outputs a normal message about the attributes in S53. In this case, the verification unit 3 may display "No abnormalities in the terminal attributes" as the normal message.

In S54 and S55, the verification unit 3 detects the number of pull resistors provided in the target circuit portion. Pull resistors include pull-up resistors, pull-down resistors, and KEEPER circuits. Pull resistors also include pull resistors connected to signal lines between devices and pull resistors provided within devices. Furthermore, pull resistors do not include damping resistors.

When detecting pull resistors installed within the target circuit portion, the verification unit 3 extracts the values entered as "Rup," "Rdn," and "pull resistor" in the verification form. This procedure is the same in Figures 18 to 22.

If two or more pull resistors are provided within the target circuit portion, the verification unit 3 determines that the resistor connection is incorrect and outputs a resistor error message in S56. For example, if duplicate pull-up resistors are provided, the verification unit 3 may display the resistor error message "Duplicate pull-up resistors."

When a single pull resistor is provided within the target circuit portion, it is not possible to determine whether the design is correct. Therefore, the verification unit 3 outputs a resistor advice message in S57. In this case, the verification unit 3 may display "Resistor connection needs to be checked" as the resistor advice message.

If a pull resistor is not installed in the target circuit portion, the verification unit 3 outputs a normal message regarding the resistor connection in S58. In this case, the verification unit 3 may display "No problem" as the normal message.

Figure 19 is a flowchart showing an example of verification processing related to an open-drain input terminal. The processing of this flowchart corresponds to S33 shown in Figure 16, and is executed when the target circuit portion includes an open-drain input terminal. In this example, it is assumed that the processing shown in Figure 18 (i.e., verification related to the output terminal) has been completed.

In S61, the verification unit 3 references the design information for each device and determines whether or not a bidirectional terminal exists in the target circuit portion. If a bidirectional terminal exists in the target circuit portion, the verification unit 3 outputs an attribute error message in S62. In this case, the verification unit 3 may display "E: Bidirectional terminal included" as the attribute error message. On the other hand, if a bidirectional terminal does not exist in the target circuit portion, the verification unit 3 outputs a normal message for the attribute in S63.

Note that a design that includes both open-drain input and output terminals within the target circuit is an error. However, verification of the output terminals has already been completed. Therefore, in the flowchart shown in Figure 19, there is no need to determine whether an output terminal exists when verifying the attributes of each terminal.

In S64, the verification unit 3 determines whether two or more pull-ups exist in the target circuit portion. If two or more pull-ups exist in the target circuit portion, the verification unit 3 determines that the resistor connection is incorrect and outputs a resistor error message in S65. In this case, the verification unit 3 may display "Duplicate pull-up resistor" as the resistor error message.

In S66, the verification unit 3 determines whether a pull-down resistor or a KEEPER circuit is present in the target circuit portion. If a pull-down resistor or a KEEPER circuit is present in the target circuit portion, the verification unit 3 determines that the resistor connection is incorrect and outputs a resistor error message in S67. In this case, the verification unit 3 may display the resistor error message "Pull-down or KEEPER circuit present."

In S68, the verification unit 3 determines whether the target circuit portion has a pull-up. If there is no pull-up in the target circuit portion, the verification unit 3 determines that the resistor connection is incorrect and outputs a resistor error message in S69. In this case, the verification unit 3 may display "No pull-up" as the resistor error message. On the other hand, if the target circuit portion has a pull-up, the verification unit 3 determines that the resistor connection is correct and outputs a normal message about the resistor connection in S70.

Figure 20 is a flowchart showing an example of verification processing related to open-drain terminals. The processing in this flowchart corresponds to S34 shown in Figure 16, and is executed when the target circuit portion includes an open-drain terminal. In this example, it is assumed that the processing shown in Figures 18 and 19 (i.e., verification related to output terminals and open-drain input terminals) has been completed.

In S81, the verification unit 3 references the design information for each device and determines whether or not a bidirectional terminal exists in the target circuit portion. If a bidirectional terminal exists in the target circuit portion, the verification unit 3 outputs an attribute error message in S82. In this case, the verification unit 3 may display "E: Includes bidirectional terminal" as the attribute error message. On the other hand, if a bidirectional terminal does not exist in the target circuit portion, the processing of the verification unit 3 proceeds to S83.

Note that a design that includes both open-drain terminals and output terminals within the target circuit is incorrect. However, verification of output terminals has already been completed. Therefore, in the flowchart shown in Figure 20, there is no need to determine whether an output terminal exists when verifying the attributes of each terminal.

In S83, the verification unit 3 references the design information for each device and determines whether or not an input terminal exists within the target circuit portion. If no input terminal exists within the target circuit portion, the verification unit 3 outputs an attribute error message in S84. In this case, the verification unit 3 may display "E: No input terminal" as the attribute error message. On the other hand, if an input terminal exists within the target circuit portion, the verification unit 3 outputs a normal message for the attribute in S85.

The processing of S86 to S92 is essentially the same as S64 to S70 in the flowchart shown in Figure 19. Therefore, a description of S86 to S92 will be omitted.

Figure 21 is a flowchart showing an example of verification processing related to bidirectional terminals. The processing in this flowchart corresponds to S35 shown in Figure 16, and is executed when the target circuit portion includes a bidirectional terminal. In this example, it is assumed that the processing shown in Figures 18 to 20 (i.e., verification related to output terminals, open-drain input terminals, and open-drain terminals) has been completed.

A design that mixes bidirectional terminals with output terminals, open-drain input terminals, or open-drain terminals within the target circuit portion is incorrect. However, verification of output terminals, open-drain input terminals, and open-drain terminals has already been completed. Therefore, in the flowchart shown in Figure 21, verification of the attributes of each terminal is not necessary.

In S101, the verification unit 3 determines whether the target circuit portion has two or more pull resistors. If the target circuit portion has two or more pull resistors, the verification unit 3 determines that the resistor connection is incorrect and outputs a resistor error message in S102. For example, if duplicate pull-up resistors are provided, the verification unit 3 may display the resistor error message "Duplicate pull-up resistors."

In S103, the verification unit 3 determines whether the target circuit portion has a pull resistor. If the target circuit portion does not have a pull resistor, the verification unit 3 determines that the resistor connection is incorrect and outputs a resistor error message in S104. In this case, the verification unit 3 may display "No pull resistor" as the resistor error message. On the other hand, if the target circuit portion has one pull resistor, the verification unit 3 determines that the resistor connection is correct and outputs a normal message about the resistor connection in S105.

Figure 22 is a flowchart showing an example of verification processing related to input terminals. The processing in this flowchart corresponds to S36 shown in Figure 16, and is executed when the target circuit portion includes an input terminal. In this example, it is assumed that the processing shown in Figures 18 to 21 (i.e., verification related to output terminals, open-drain input terminals, open-drain terminals, and bidirectional terminals) has been completed.

In S111, the verification unit 3 references the design information for each device and determines whether all terminals in the target circuit portion are input terminals only. In this example, verification processing for output terminals, open-drain input terminals, open-drain terminals, and bidirectional terminals has been completed. Therefore, if any terminals other than input terminals remain, it is assumed that some kind of abnormality (e.g., a database error) has occurred. Therefore, in this case, the processing of the verification unit 3 is terminated with an abnormal stop.

If all terminals are input terminals, the verification unit 3 proceeds to S112. The processes of S112 to S116 are essentially the same as S101 to S105 in the flowchart shown in Figure 21. However, in S114, the verification unit 3 determines whether the target circuit portion is connected to a pull resistor, power supply, or GND. If the target circuit portion is connected to a pull resistor, power supply, or GND, the verification unit 3 outputs a normal message in S116.

<Hardware configuration>
23 shows an example of the hardware configuration of the circuit verification device 10. The circuit verification device 10 is realized by a computer 100 including a processor 101, a memory 102, a storage device 103, an input/output device 104, a recording medium reader 105, and a communication interface 106.

The processor 101 executes the circuit verification program stored in the storage device 103. The processor 101 executes the circuit verification program, thereby providing the functionality of the verification unit 3 shown in FIG. 3. The memory 102 is used as a working area for the processor 101. The storage device 103 stores the circuit verification program and other programs. The netlist storage unit 1 and the device design information storage unit 2 are realized by the memory 102 or the storage device 103.

The input/output device 104 may include input devices such as a keyboard, mouse, touch panel, and microphone. The input/output device 104 may also include output devices such as a display device and speaker. The recording medium reader 105 can acquire data and information recorded on the recording medium 110. The recording medium 110 is a removable recording medium that can be attached to and detached from the computer 100. The recording medium 110 may be realized, for example, by a semiconductor memory, a medium that records signals optically, or a medium that records signals magnetically. The circuit verification program may be provided to the computer 100 from the recording medium 110. The communication interface 106 provides the function of connecting to a network. When the circuit verification program is stored on the program server 120, the computer 100 may acquire the circuit verification program from the program server 120.

1 Netlist storage unit 2 Device design information storage unit 3 Verification unit 4 Display unit 10 Circuit verification device 101 Processor 102 Memory

Claims (6)

A circuit verification device that verifies a target circuit including a plurality of ICs,
a first storage unit that stores netlist information representing connections between the plurality of ICs;
a second storage unit that stores design information for each of the plurality of ICs;
a verification unit that verifies the target circuit based on the netlist information and design information for each of the plurality of ICs,
the design information includes, for each of the plurality of ICs, attribute information representing attributes of each terminal of the IC, and internal circuit information representing an internal circuit connected to each terminal within the IC;
The verification unit
when a first terminal of a first IC among the plurality of ICs is designated, detecting a second terminal of a second IC among the plurality of ICs that is electrically connected to the first terminal based on the netlist information;
detecting a circuit portion to be verified that is electrically connected to the first terminal based on the netlist information, the internal circuit information related to the first terminal, and the internal circuit information related to the second terminal;
performing a first determination based on the attribute information related to the first terminal and the attribute information related to the second terminal to determine whether or not the first terminal and the second terminal may be electrically connected;
and performing a second determination of whether or not a resistor is correctly provided in the circuit portion to be verified, based on the netlist information, the attribute information and internal circuit information related to the first terminal, and the attribute information and internal circuit information related to the second terminal. the attribute information indicates whether the attribute of each terminal is an output terminal, an open-drain input terminal, an open-drain terminal, a bidirectional terminal, or an input terminal;
The verification unit
2. The circuit verification device according to claim 1, wherein in the first determination, it is determined whether or not the first terminal and the second terminal may be electrically connected based on rule information representing a combination of attributes of terminals that must not be electrically connected to each other, an attribute of the first terminal, and an attribute of the second terminal. the internal circuit information indicates whether a pull-up resistor is connected to each of the terminals, whether a pull-down resistor is connected to each of the terminals, and whether a voltage holding circuit is connected to each of the terminals;
the rule information includes information indicating a resistor circuit required for each attribute of a terminal;
The verification unit
3. The circuit verification device according to claim 2, wherein in the second determination, it is determined whether or not a resistor is correctly provided in the circuit portion to be verified based on the rule information, an attribute of the first terminal, and an attribute of the second terminal. the internal circuit information indicates whether a pull-up resistor is connected to each of the terminals, whether a pull-down resistor is connected to each of the terminals, and whether a voltage holding circuit is connected to each of the terminals;
the rule information includes information indicating a resistor circuit that should not be provided for each attribute of the terminal;
The verification unit
3. The circuit verification device according to claim 2, wherein in the second determination, it is determined whether or not a resistor is correctly provided in the circuit portion to be verified based on the rule information, an attribute of the first terminal, and an attribute of the second terminal. the design information further includes signal name information indicating signal names assigned to each terminal of each of the plurality of ICs;
2. The circuit verification device according to claim 1, wherein the verification unit outputs a result of comparing the signal name assigned to the first terminal with the signal name assigned to the second terminal. A circuit verification method for verifying a circuit including a plurality of ICs based on netlist information representing connections between the plurality of ICs and design information for each of the plurality of ICs, comprising:
the design information includes, for each of the plurality of ICs, attribute information representing attributes of each terminal of the IC, and internal circuit information representing an internal circuit connected to each terminal within the IC;
when a first terminal of a first IC among the plurality of ICs is designated, detecting a second terminal of a second IC among the plurality of ICs that is electrically connected to the first terminal based on the netlist information;
detecting a circuit portion to be verified that is electrically connected to the first terminal based on the netlist information, the internal circuit information related to the first terminal, and the internal circuit information related to the second terminal;
performing a first determination based on the attribute information related to the first terminal and the attribute information related to the second terminal to determine whether or not the first terminal and the second terminal may be electrically connected;
and performing a second determination of whether or not a resistor is correctly provided in the circuit portion to be verified based on the netlist information, the attribute information and internal circuit information related to the first terminal, and the attribute information and internal circuit information related to the second terminal.