JP2503187B2 - 二重シリサイド層配線をもつ半導体装置の製造方法 - Google Patents

二重シリサイド層配線をもつ半導体装置の製造方法

Info

Publication number
JP2503187B2
JP2503187B2 JP5128658A JP12865893A JP2503187B2 JP 2503187 B2 JP2503187 B2 JP 2503187B2 JP 5128658 A JP5128658 A JP 5128658A JP 12865893 A JP12865893 A JP 12865893A JP 2503187 B2 JP2503187 B2 JP 2503187B2
Authority
JP
Japan
Prior art keywords
layer
silicide
polycrystalline silicon
semiconductor device
metal layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP5128658A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0637092A (ja
Inventor
壽鉉 白
珍▲そく▼ 崔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JPH0637092A publication Critical patent/JPH0637092A/ja
Application granted granted Critical
Publication of JP2503187B2 publication Critical patent/JP2503187B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01306—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon
    • H10D64/01308—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal
    • H10D64/0131—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4451—Semiconductor materials, e.g. polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/412—Deposition of metallic or metal-silicide materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/30—Diffusion for doping of conductive or resistive layers
    • H10P32/302—Doping polycrystalline silicon or amorphous silicon layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/064—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying
    • H10W20/066—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying by forming silicides of refractory metals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
JP5128658A 1992-05-30 1993-05-31 二重シリサイド層配線をもつ半導体装置の製造方法 Expired - Lifetime JP2503187B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019920009414A KR950003233B1 (ko) 1992-05-30 1992-05-30 이중층 실리사이드 구조를 갖는 반도체 장치 및 그 제조방법
KR1992P9414 1992-05-30

Publications (2)

Publication Number Publication Date
JPH0637092A JPH0637092A (ja) 1994-02-10
JP2503187B2 true JP2503187B2 (ja) 1996-06-05

Family

ID=19333972

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5128658A Expired - Lifetime JP2503187B2 (ja) 1992-05-30 1993-05-31 二重シリサイド層配線をもつ半導体装置の製造方法

Country Status (6)

Country Link
US (1) US6774023B1 (2)
EP (1) EP0573241B1 (2)
JP (1) JP2503187B2 (2)
KR (1) KR950003233B1 (2)
CN (2) CN1034198C (2)
RU (1) RU2113034C1 (2)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6156630A (en) * 1997-08-22 2000-12-05 Micron Technology, Inc. Titanium boride gate electrode and interconnect and methods regarding same
SE515783C2 (sv) * 1997-09-11 2001-10-08 Ericsson Telefon Ab L M Elektriska anordningar jämte förfarande för deras tillverkning
US7282443B2 (en) * 2003-06-26 2007-10-16 Micron Technology, Inc. Methods of forming metal silicide
US7112483B2 (en) * 2003-08-29 2006-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming a device having multiple silicide types
US7105440B2 (en) * 2005-01-13 2006-09-12 International Business Machines Corporation Self-forming metal silicide gate for CMOS devices
US20100052072A1 (en) * 2008-08-28 2010-03-04 Taiwan Semiconductor Manufacturing Company, Ltd. Dual gate structure on a same chip for high-k metal gate technology
RU2405228C2 (ru) * 2008-12-15 2010-11-27 Белорусский государственный университет Способ формирования силицидов металлов
US8652914B2 (en) 2011-03-03 2014-02-18 International Business Machines Corporation Two-step silicide formation
CN105541337B (zh) * 2015-12-25 2017-12-08 中国科学院上海硅酸盐研究所 一种多金属硅化物粉体及其制备方法
US9837357B1 (en) 2017-02-06 2017-12-05 International Business Machines Corporation Method to reduce variability in contact resistance
TW202429576A (zh) * 2023-01-05 2024-07-16 美商應用材料股份有限公司 藉由鉬與鈦的整合之觸點電阻降低

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4180596A (en) * 1977-06-30 1979-12-25 International Business Machines Corporation Method for providing a metal silicide layer on a substrate
US4285761A (en) * 1980-06-30 1981-08-25 International Business Machines Corporation Process for selectively forming refractory metal silicide layers on semiconductor devices
DE3326142A1 (de) * 1983-07-20 1985-01-31 Siemens AG, 1000 Berlin und 8000 München Integrierte halbleiterschaltung mit einer aus aluminium oder aus einer aluminiumlegierung bestehenden aeusseren kontaktleiterbahnebene
JP2522924B2 (ja) * 1986-11-19 1996-08-07 三洋電機株式会社 金属シリサイド膜の形成方法
US4782380A (en) * 1987-01-22 1988-11-01 Advanced Micro Devices, Inc. Multilayer interconnection for integrated circuit structure having two or more conductive metal layers
US4974056A (en) * 1987-05-22 1990-11-27 International Business Machines Corporation Stacked metal silicide gate structure with barrier
JPS6417471A (en) * 1987-07-13 1989-01-20 Toshiba Corp Semiconductor device
JPS6417470A (en) * 1987-07-13 1989-01-20 Toshiba Corp Semiconductor device
JPH0234967A (ja) * 1988-07-25 1990-02-05 Sony Corp 半導体装置及び半導体装置の製造方法
JPH02262371A (ja) * 1989-04-03 1990-10-25 Toshiba Corp 半導体装置及びその製造方法
US5194405A (en) * 1989-07-06 1993-03-16 Sony Corporation Method of manufacturing a semiconductor device having a silicide layer
JP2616034B2 (ja) * 1989-08-23 1997-06-04 日本電気株式会社 半導体集積回路装置
US5203957A (en) * 1991-06-12 1993-04-20 Taiwan Semiconductor Manufacturing Company Contact sidewall tapering with argon sputtering

Also Published As

Publication number Publication date
RU2113034C1 (ru) 1998-06-10
EP0573241B1 (en) 2000-02-09
CN1121642A (zh) 1996-05-01
EP0573241A2 (en) 1993-12-08
CN1034198C (zh) 1997-03-05
EP0573241A3 (2) 1994-02-16
KR930024089A (ko) 1993-12-21
CN1076866C (zh) 2001-12-26
JPH0637092A (ja) 1994-02-10
CN1081283A (zh) 1994-01-26
US6774023B1 (en) 2004-08-10
KR950003233B1 (ko) 1995-04-06

Similar Documents

Publication Publication Date Title
EP0159935B1 (en) Method for inhibiting dopant out-diffusion
US5970370A (en) Manufacturing capping layer for the fabrication of cobalt salicide structures
US5302552A (en) Method of manufacturing a semiconductor device whereby a self-aligned cobalt or nickel silicide is formed
KR100214036B1 (ko) 알루미늄계 배선형성방법
JP2503187B2 (ja) 二重シリサイド層配線をもつ半導体装置の製造方法
JP2685297B2 (ja) 半導体デバイスの製造方法
US6204173B1 (en) Multiple implantation and grain growth method
US4954852A (en) Sputtered metallic silicide gate for GaAs integrated circuits
WO2000022659A1 (en) Method of forming cobalt-disilicide contacts using a cobalt-carbon alloy thin film
JP2908774B2 (ja) 半導体素子のビットライン及びその製造方法
JPH06163457A (ja) 半導体装置およびその製造方法
JP3419072B2 (ja) 化合物半導体装置の製造方法
JPH0147012B2 (2)
JPH0687501B2 (ja) 半導体装置のゲート電極の製造方法
JP3416205B2 (ja) 半導体装置およびその製造方法
JPS6138264B2 (2)
JPH10223561A (ja) 半導体装置の製造方法
JP2003031522A (ja) 半導体素子の製造方法
JP3537273B2 (ja) 半導体装置の製造方法
JPS639661B2 (2)
JP2650972B2 (ja) 半導体装置の製造方法
KR100447992B1 (ko) 반도체소자의게이트전극형성방법
JPS61135156A (ja) 半導体装置およびその製造方法
KR0168153B1 (ko) 반도체 소자의 티타늄 실리사이드층 형성방법
JPS62206827A (ja) チタン・シリサイド膜の熱処理方法

Legal Events

Date Code Title Description
R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080313

Year of fee payment: 12

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090313

Year of fee payment: 13

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100313

Year of fee payment: 14

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110313

Year of fee payment: 15

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130313

Year of fee payment: 17