JP2618112B2 - Semiconductor test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test apparatus for performing a pass / fail test of a semiconductor device such as an LSI.

[0002]

2. Description of the Related Art A pass / fail test of a semiconductor device such as an LSI is roughly divided into a function test and a DC test. The function test is also called a functional test, and tests whether a DUT (inspected LSI) performs a functional operation according to specifications. The DC test checks whether DC items such as input leak and output voltage satisfy the specifications. test. Where DC
When performing a test, it is necessary to apply the same test pattern to the DUT as in the function test.
A DC test has been performed by applying a test pattern to the DUT by alternately executing the function test unit and the DC test unit.

FIG. 8 is a flowchart showing a processing procedure of a conventional CPU (provided separately from the function test unit and the DC test unit) during the DC test. In a conventional test program, first, various conditions are set in a function test unit, for example, setting of a timing condition, setting of a high / low level of a signal applied to a DUT, setting of a comparison reference voltage of a comparator, and the like. After specifying the stop address, the function test unit is started by executing an instruction described as MEAS FUNC (n41 → n42 → n43). In n43, the function test unit sets and initializes a previously set condition in hardware, sets a start address and a stop address of an area where an input pattern in which the output pin is at a low level is set, and starts. I do. After the start, a test pattern from a start address to a stop address is applied at a timing set by dedicated hardware. After the test pattern is applied by the above processing, various conditions are set in the DC test unit, for example, setting of an applied voltage / current value, setting of a measurement range, and the like. Execute the DC test unit (n44 →
n45 → n46). In n46, the CPU outputs a measurement start signal by executing an instruction described as MEAS ADC, reads the measurement result from hardware when the measurement is completed, compares it with the determination limit, and determines whether the DUT is good or not. judge. As described above, the DC test at the time of setting the low level is completed. Similarly, a high level DC test is performed in n47 to n50.

[0004]

However, in the conventional DC test as described above, the function test unit is activated every time a test pattern is applied to the DUT, and the unit is initialized each time, so that the processing time is reduced. Had the problem of becoming longer. Normally, when the function test unit is started by a signal from the CPU, initialization of the function test unit, setting of start / stop addresses, checking whether the test conditions have not changed, determination work after the end of the function test, and the like. Is done. For example, in the case of the test shown in FIG. 8, in n43 and n48, the function test unit is activated by a signal from the CPU,
Checking of test conditions and the like is also performed in n48. However, the test conditions are not changed between n43 and n48, and the test condition check is useless. n46, n50
The same applies to the execution of the DC test unit at n50. The processing time becomes longer due to useless test condition checks, and the processing time becomes longer as the number of measurements increases and as the number of pins increases.

An object of the present invention is to provide a semiconductor inspection apparatus capable of shortening the time required for a DC test by causing a DC test unit to be executed by a function test unit.

[0006]

SUMMARY OF THE INVENTION The present invention provides a function test unit for applying a test pattern to a semiconductor device to be inspected and checking its function, and a DC test for measuring a DC level of an input / output terminal with the test pattern applied. A test pattern setting completion signal for a DC test is output to the DC test unit to the function test unit, and after the setting completion signal is output, the DC test unit is not terminated. Means for repeating a test pattern setting cycle a predetermined number of times for waiting for a measurement completion signal from the DC test unit, the DC test unit receiving the setting completion signal, starting the DC level measurement, and measuring the DC level in a test pattern applied state. After comparing the result with the standard value, the quality Characterized in that the DC test check cycle for outputting a measurement completion signal to the unit is provided with means for repeating a predetermined number of times.

[0007]

The operation will be described below with reference to the block diagram of the present invention shown in FIG.

The function test unit and the DC test unit are initialized by the setting process of the CPU.
The C test is performed. In the DC test, first, the function test unit applies a DC test pattern stored in advance to the DUT, and at the same time, outputs a setting completion signal to the DC test unit. The DC test unit waits for a setting completion signal, and starts the measurement process of the DC level of the input / output terminal by this signal. Then, the quality of the DUT is determined based on the measured DC level. When the measurement processing is completed, a measurement completion signal is output to the function test unit, and the process returns to the setting completion signal waiting state.

On the other hand, the function test unit which has output the test pattern setting completion signal waits for a measurement completion signal, and upon receiving this signal, applies the next test pattern or executes all of the stored test patterns. Is completed, the control is returned to the CPU. When a plurality of test patterns are stored in the function test unit, the function test unit continues processing without returning control to the CPU until all the test patterns are executed. That is, the function test unit and the DC test unit continue to be activated until all the test patterns are completed, and during this time, processing such as unit initialization and test condition check is not performed. When all test patterns are completed, the CPU
Performs termination processing of the function test unit and the DC test unit.

[0010]

FIG. 2 is a block diagram of a semiconductor test apparatus.
A tester controller (CPU) 1 controls a function test unit 2, a DC test unit 3, and pin electronics 4, for example, setting conditions for hardware,
The processing based on the measurement results of the function unit 2 and the DC test unit 3 is performed. The function test unit 2 applies a test pattern to the DUT. Further, it sets a determination limit, outputs a setting completion signal (measurement start signal) to the DC test unit 3, receives a measurement end signal from the DC test unit 3, and the like. D
The C test unit 3 includes a plurality of circuits for voltage applied current measurement / current applied voltage measurement, compares the measured value of the circuit with the determination limit, and outputs the result to the function test unit 2 or the tester controller 1. The pin electronics 4 drives a signal from the function test unit 2 by a driver and applies the signal to the DUT, and sends a signal from the DUT to the function test unit 2 and the DC test unit 3.

FIG. 3 shows a configuration example of the DC test unit 3. The DC test unit is controlled by the controller 31. The controller 31 receives signals from the function test unit 2, the CPU 1, and the like to operate each operation unit, and outputs a measurement result and the like to the function unit 2, the CPU 1, and the like. The DC test unit has a plurality of measurement units 32-1 to 32-n. Each measurement unit 32 has a function of measuring a voltage applied current / current applied voltage, and is connected to an output pin of the DUT. The voltage measured by each measurement unit 32 is converted into a digital value by the AD converter 33, and is compared by the comparator 34 with the judgment limit upper limit value or the judgment limit lower limit value. The comparator 34 outputs “0” when the measured voltage value is within the range of the judgment limit upper limit value / judgment limit lower limit value, and outputs “1” when the measured voltage value exceeds the judgment limit upper limit value / judgment limit lower limit value. . The upper limit and the lower limit of the judgment limit to be compared are sent from the function test unit 2 (see FIG. 1), the upper limit of the judgment limit is stored in the register 35, and the lower limit of the judgment limit is stored in the register 36. . The result of the comparison by the comparator 34 is input to the OR circuit 37. The OR circuit 37 outputs “1” when at least one of the inputs from the plurality of comparators is “1”. The output value from the OR circuit 37 is input to the controller 31. In the conventional device, only the measurement unit and the AD converter, which are enclosed by a broken line in the figure, are configured as DC test units.
It was input to the PU and the quality of the DUT was determined.

FIG. 4 is a diagram showing a configuration of a pattern program of the function test unit. A pattern address is assigned to the pattern program, and each address has a pattern control area and a pattern data area. The pattern control area controls the reading of pattern data such as loops and jumps.
The setting completion signal (measurement start signal) and the function of waiting for measurement according to the present invention also belong to this area. The pattern data area is an area in which a pattern for setting the state of the DUT is described. In this embodiment, there are two types of pattern data, that is, pattern data for setting all pins of the DUT to low level and pattern data for setting all pins of the DUT to high level. Is described.

The processing procedure of the DUT test performed by the semiconductor inspection apparatus configured as described above will be described. 5 is a diagram showing a processing procedure of the CPU of the device, FIG. 6 is a diagram showing a processing procedure of the function test unit of the device, and FIG. 7 is a diagram showing a processing procedure of the DC test unit of the device. . In this embodiment, for the sake of simplicity, a description will be given of a case where two types of test patterns are applied, that is, a case where all pins are at a low level and a case where all pins are at a high level.

The tester controller (CPU) 1 sets the condition of the function test and the condition of the DC test, and specifies the start address and the stop address of the program of the function test unit 2 shown in FIG. 4 (n1 → n2). → n3). Then, an inspection process is executed (n4).

The function test unit 2 has a CPU
When an inspection execution signal is received from, an inspection process is performed according to the pattern program shown in FIG. First, a test pattern is applied to the DUT so that the outputs of all pins become low level, and a function test is executed (n
11). At the same time, a setting completion signal is output to the DC test unit 3, and then a measurement completion signal from the DC test unit 3 is waited (n12 → n13).

On the other hand, when the DC test unit 3 receives the measurement start signal (setting completion signal), the output voltage is measured by each measurement unit 32, and the quality of the DUT is determined based on the measured voltage (n21 → n22 → n23). If the outputs of all pins are within the limit range, a measurement completion signal is output to the function test unit 2 (n24 →
n25). If at least one of the pins exceeds the limit (if the output of the OR circuit 37 is “1”), the processing is interrupted and a DUT failure signal is output to the CPU 1. Similarly, n14 to n16 and n26 to n3
At 1, the pattern is applied to the DUT so that the outputs of all the pins become high level, and the function test and the DC test are performed.

In this manner, a plurality of test patterns described between the start address and the stop address of the function test unit are applied to the DUT, and
The C level is measured. The function test unit is in a standby state while the DC test unit is measuring, and the DC test unit is in a standby state when the function test unit is performing application processing on the DUT. For this reason, the function test unit and the DC test unit do not end until the measurement of all test patterns is completed, and the processing time for the conventional end, initialization, check of test conditions, and the like required for each setting is conventionally performed. Can be omitted.

In the function test unit,
If a function capable of changing the applied voltage / applied current, the voltage and the like in real time and more finely is added, various DC tests can be performed in one operation in a short time. Further, if a memory for storing data of measurement results is provided in the DC test unit, it is possible to statistically process the DC test results several times.

[0019]

As described above, according to the present invention, the function test unit outputs a test pattern setting completion signal indicating the start of measurement to the DC test unit,
The function test unit is in a standby state during the measurement, and the function test unit and the DC test unit are not terminated every time a test pattern is set and measured. For this reason, it is possible to save time for checking and judging processing of test conditions required at the time of setting and terminating the unit, and there is an advantage that the processing time as a whole can be shortened.

[Brief description of the drawings]

FIG. 1 shows a configuration of the present invention.

FIG. 2 is a block diagram of a semiconductor test apparatus according to an embodiment of the present invention.

FIG. 3 is a configuration example of a DC test unit.

FIG. 4 is a diagram showing a configuration of a pattern program of a function test unit.

FIG. 5 is a view showing a processing procedure of a CPU of the semiconductor test apparatus.

FIG. 6 is a view showing a processing procedure of a function test unit of the semiconductor test apparatus.

FIG. 7 is a view showing a processing procedure of a DC test unit of the semiconductor test apparatus.

FIG. 8 is a diagram showing a processing procedure of a CPU of a conventional semiconductor test apparatus.

[Explanation of symbols]

 1 Tester Controller 2 Function Test Unit 3 DC Test Unit 4 Pin Electronics

Claims (1)

(57) [Claims] A function test unit for applying a test pattern to a semiconductor device to be inspected to check its function; and a DC test unit for measuring a DC level of an input / output terminal in a state where the test pattern is applied. A test pattern setting completion signal for a DC test is output to the DC test unit to the test unit, and after the setting completion signal is output, the process waits for a measurement completion signal from the DC test unit without terminating the processing. A means for repeating a test pattern setting cycle a predetermined number of times is provided. The DC test unit receives the setting completion signal, starts the DC level measurement, and compares the DC level measurement result in a test pattern applied state with a standard value. Judge pass / fail and send a measurement completion signal to the function test unit. The semiconductor test apparatus being characterized in that a means for repeating predetermined times a DC test check cycle for outputting.