JP2627112B2 - Vector generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a vector for writing luminance data into a video memory corresponding to each pixel of a display screen in order to display a vector (line) having a line width by inputting initial position information and inclination information. It relates to a generator.

[0002]

2. Description of the Related Art FIG. 7 shows a conventional vector generator.
Xs, Y of XY coordinates (Xs, Ys) of initial position (start point)
s are stored in the X register 11 and the Y register 12, respectively, and the inclination information ΔX and ΔY are stored in the ΔX register 13 and the Y register 12, respectively.
It is stored in the ΔY register 14. Xs of X register 11
Is added by the adder 15, and the result of the addition is stored in the X register 11. Therefore Xs
Is cumulatively added to. Similarly, ΔY of the ΔY register 14 is added to Ys of the Y register 12 by the adder 1.
6, and the result of the addition is stored in the Y register 12.

Each time the addition is performed by the adders 15 and 16, each integer part of the addition result is preset in an X address counter 17 and a Y address counter 18, respectively. Further, when ΔX> ΔY in the multiplexer 19, the fractional part of the output of the adder 16 is used, and when ΔX <ΔY, the adder 1 is used.
The fractional parts of the output of 5 are each selected. In memory write sequencer 21, each performing addition in adder 15, [Delta] X <half the X address counter 17 of the number of pixels of line width when the [Delta] Y, after down-count, 1 a time until
When ΔX> ΔY, the same operation is performed on the Y address counter 18.

The count number PXCNT of the up-count from the memory write sequencer 21 to the address counter 17 or 18 and the output of the multiplexer 19 are given to the luminance table 22 as an address. The luminance table 22 stores the maximum luminance data at the center of the count number PXCNT, and luminance data whose luminance decreases in accordance with the maximum luminance data, whichever is smaller or larger. The luminance data read from the luminance table 22 is written to the video memory 23 using the count values of the address counters 17 and 18 as addresses. The above control is performed by the arithmetic control sequencer 24. The end point of the vector is the data in the arithmetic control sequencer 24 and is determined by stopping the addition control for the adders 15 and 16.

[0005]

In the conventional vector generating apparatus shown in FIG. 7, when a vector having a line width is generated, as shown in FIG. Deteriorates.

[0006]

According to the present invention, the luminance table has luminance data corresponding to each pixel of the line width in the same manner as in the prior art, and the center of the line width is the maximum luminance, and the luminance decreases as approaching both ends. In addition, in addition to providing a normal region with the lowest luminance at both ends, a rounded region is provided, and the rounded region is composed of a plurality of regions each having luminance data corresponding to each pixel of the line width, and these regions are sequentially arranged with respect to the normal region. When arranged, the brightness of the corresponding pixel decreases as the distance from the normal area increases.

[0007] In the luminance table, an area is selected depending on whether it is at the end of the generated vector. At the beginning of the vector, the start point is shifted in the opposite direction of the vector for the X or Y component by half the line width, the start point processing is performed, the end point of the vector is held, the end point is held, and the held end point is Is the starting point of the vector. In addition, in the start point processing of the next vector, before writing the luminance data, the video memory is read at that address, and if the read luminance data is larger than the luminance data read from the luminance table, the writing is prohibited.

[0008]

FIG. 1 shows an embodiment of the present invention, in which parts corresponding to those in FIG. 7 are denoted by the same reference numerals. In this example, the data ΔX and ΔY of the ΔX register 13 and ΔY register 14 are supplied to adders 15 and 16 via shifters 26 and 27, respectively. The contents of the X register 11 and the Y register 12 can be stored in the holding registers 28 and 29, respectively. Output of adder 15 and holding register 2
8 is selected by the multiplexer 31 and stored in the X register 11, and one of the output of the adder 16 and the output of the holding register 29 is selected by the multiplexer 32 and
The data can be stored in the register 12.

Prior to writing to the video memory 23, the video memory 23 is read at the address at that time,
The read luminance data is stored in the read register 33, and the data of the read register 33 and the luminance data (data to be written) read from the luminance table 22 are compared by the comparator 34. When it is larger, the output of the comparator 34 is supplied to the video memory 23 as a write command.

As shown in FIG. 2A, the luminance table 22 is provided with a rounded area 37 for processing a vector end in addition to a normal area 36 for giving a normal line width. The normal region 36 is the number of pixels of the line width of the vector, in this example, 6
Has a luminance data of the pixel, the maximum luminance is the central pixel P _0, is the F hexadecimal in FIG its neighboring pixels P _-1, P
₊₁ is 7, D, respectively, and the pixels P _-2 , P ₊₂ , which are further away, are 1, 7 respectively, and the pixel P
The luminance of ₊₃ is 1. That is, as shown in FIG. 2B, the luminance distribution in the line width direction of the normal vector based on the normal area 36 is the maximum luminance at the center pixel P ₀ , the luminance decreases as the distance from the center pixel P ₀ increases, and both ends P ₋₂ , P ₊₃ Then, the brightness becomes the lowest.

The rounded area 37 is an area of half the number of pixels of the vector line width, in this example, three areas 37a, 37
b and 37c, each having the number of pixels of the line width, in this example, six luminance data. These areas 37a,
When the pixels 37b and 37c are sequentially arranged with the normal area 36, the brightness of the corresponding pixel decreases as the distance from the normal area 36 increases. In this example, pixels P _-2 , P _-1 , P ₀ , P ₊₁ , P ₊₂ ,
For P ₊₃ , the area 37a has luminances 1, 5, 8, and
9, 5, 1 and the area 37b have the brightness of 0, 1, 3, respectively.
2, 1, 0, and the area 37c has a luminance of 0, 0, 1, 1, respectively.
0,0,0 is provided. That is, as for the pixel P ₀ , the luminance sequentially decreases to F, B, 3, 1 and the luminance also decreases to D, 9, 2, ₀ for the pixel P _{+ 1} . Area 3
The luminance distributions of 7a, 37b and 37c are shown in FIG.
D and E are as shown in FIG. The regions 36, 37a, 37b,
TSEL0, TSEL1, TSEL2, TSEL3
And This address TSELi (i = 0, 1, 2, 3) is given to the luminance table 22 from the arithmetic control sequencer 24 in FIG.

Next, to generate a vector, the data X
s, Ys, ΔX, ΔY are registers 11, 12,
When these are set to 13 and 14, in the present invention, first, a start point process is executed. This process is performed, for example, according to the flow shown in FIG. First, i of the address TSELi of the luminance table 22 is set to 3
(S ₁ ), then check whether the absolute value of ΔX is greater than the absolute value of ΔY (S ₂ ), and | ΔX |> | Δ
Y | a mule Xs - the (ΔX × 8 × LW / 2 ) is stored in the X register 11 (S _3). Lw is the line width of the vector, X, fractional part of Y is the case of 3 bits, would be shifted only in the vector direction opposite half value of the line width of the X step S _3. If | ΔX |> | ΔY | is not Ys
- a (ΔY × 8 × LW / 2 ) and stored in Y register 12, shifted by the vector direction opposite half of the line width value of Y (S _4). In FIG. 1, the shifters 26 and 27 are shifted upward by 3 bits to multiply ΔX and ΔY by 8 respectively.

At this time, the X register 11 and the Y register 1
2 are preset in the X address counter 17 and the Y address counter 18, and writing to the video memory 23 is performed under the control of the memory writing sequencer 21 as in the conventional case. However, before each write, the video memory 23 is read at the address at that time, the read luminance data is held in the read register 33, and the read luminance data from the luminance table 22 and the comparator 3
4 is compared. The luminance table 22 is read from the area 37c in the order of the pixels P _-2 , P _-1 , P ₀ , P ₊₁ , P ₊₂ , and P ₊₃ , and for each read, the video memory 23 is also read, The comparison in the comparator 34 is performed. If the direction of the luminance read from the video memory 23 is large, writing to the video memory 23 is prohibited. Thus performing writes to video memory 23 for 6 pixels in the region 37c with (S _5).

[0014] address TSELi a -1, and TSEL2 (S _6). It is checked whether or not | ΔX |> | ΔY | (S ₇ ),
If | ΔX |> | ΔY |, X + ΔX × 8 is stored in the X register 11 (S ₈ ). If | ΔX |> | ΔY |, Y + ΔY × 8 is stored in the Y register 12 (S ₉ ). .
i = 0 or checked (S _10), returns to i = 0 unless step S _5, similarly writes to the video memory 23 for the area 37b, is written to the video memory 23 for further regions 37a When,
i = 0, and normal vector drawing processing is performed. In normal vector drawing processing, the shifters 26 and 27 simply pass through without shifting.

When the vector reaches the end point, the termination processing shown in FIG. 4 is performed. First, the X register 11 and the Y register 1
2 are stored in holding registers 28 and 29, respectively.
CPx, and CPy (S _11), then | ΔX |> | ΔY
| Is checked (S ₁₂ ), and if so, X + ΔX × 8
Is stored in the X register 11 (S ₁₃ ), and | ΔX |> | ΔY
If not |, Y + ΔX × 8 is stored in the Y register 12 (S ₁₄ ). Next, i of the address TSELi is incremented by 1, that is,
Since Until was i = 0, and TSEL1 (S _15),
Writes to video memory 23 for that region 37a (S _16). Also in this case, the video memory 23 is read prior to each writing, and writing is performed only when the luminance read from the luminance table 22 is higher than the read luminance. Then address TSELi is checked whether a TSEL3 (S _17), if i = not 3, the process returns to step S _12. Thus, each area 37 of the rounding area
Writing to the video memory 23 is sequentially performed for a, 37b, and 37c. and it becomes i = 3, transfer the contents held in the holding register 28, 29 in the X register 11, Y register 12, respectively (S _18). Therefore, when drawing the next vector continuously, after the termination processing,
Return to the point before the termination processing, and this is set as the starting point.

Since processing is performed as described above, | ΔX |>
In the case of | ΔY |, for example, as shown in FIG. 5A, starting point processing is performed on the starting points X _S and Y _s from the point moved in the X direction, in this example, in the direction opposite to the vector 38 for three pixels. 38 is rounded at the beginning. After the start processing, the vector 38 is formed by the usual processing, and the end processing is performed at the end points Xe and Ye, and the roundness 41 is added. If | ΔX |> | ΔY | is not satisfied, for example, as shown in FIG. 5B, roundnesses 39 and 41 projecting in the Y direction are provided at both ends of the vector 38, respectively.

As shown in FIG. 6, to the end point X _1, Y ₁ vector 42 A, starting X _1, Y ₁ vector 4 B
3 is connected, the end of the vector 42 is rounded. On the other hand, when the vector 43 is connected with the starting point rounded 45, it is stored in the video memory 23 first as described above. Since writing is performed only with a luminance higher than the luminance, a portion shaded as shown by C in the connected state is the comparison writing thereof, and the luminance of the overlapping portion of the roundnesses 44 and 45 is as shown in the figure. Therefore, when the present invention is applied to the vector graphic shown in FIG. 8A, as shown in FIG.
The end point 47 is rounded, and the connecting portion 48 also has rounded continuity, so that the image quality is good.

[0018]

As described above, according to the present invention, the line width is added to the vector, and the start point and the end point of the vector are rounded, so that the display quality is improved. In particular, the connection between the vectors is rounded, and the display quality is significantly improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2A shows an example of the contents of the luminance table 22 and B to D.
Is a diagram showing a luminance distribution of each region.

FIG. 3 is a flowchart illustrating an operation example of a start process.

FIG. 4 is a flowchart showing an operation example of termination processing.

FIG. 5 is a diagram showing an example of a vector generated according to the present invention.

FIG. 6 is a diagram for explaining an operation when two vectors are connected.

FIG. 7 is a block diagram showing a conventional vector generator.

8A is a diagram showing a plurality of continuous vectors drawn by a conventional device, and FIG. 8B is a diagram drawn by a device of the present invention with respect to corresponding vectors.

Claims (2)

(57) [Claims] An inclination information is added to an initial position information for each of an X component and a Y component, and an integer part of each accumulated addition value is assigned to an X address counter for each of the X component and the Y component. And the Y address counter are preset, and both address counters are incremented by the pixel clock for the line width, and the short axis side (the absolute values of the X component and the Y component of the tilt information are small)
Axis), a decimal part of each of the cumulative addition values is selected, a luminance table is read out based on the selected decimal part and the count value of the pixel clock, and the count values of both address counters are used as an address for each pixel clock. In a vector generation device that writes luminance data read from a luminance table to a video memory, the luminance table has luminance data corresponding to each pixel of the line width, and the center of the line width has the highest luminance, as the line width approaches both ends. The brightness decreases, and both ends have a normal area with the lowest brightness and brightness data corresponding to each pixel of the above line width.
The center of the line width is the highest brightness, and the brightness becomes closer to both ends.
From but lowered, both ends of a plurality of regions of the lowest luminance, the sequentially arranged in this perpendicular direction against the above general area as the distance from the normal region, the rounding brightness of a corresponding pixel is lower respectively region Wherein the luminance table is given an area selection address according to whether or not it is the end of the generated vector. 2. A means for shifting the starting point of a vector by half the line width in the opposite direction of the vector for the X component or the Y component, holding the end point of the vector, and after processing the end point, sets the held end point to the starting point of the next vector. In the starting point processing of the next vector, before writing to the video memory, the video memory is read at the address, and if the read brightness data is larger than the brightness data read from the brightness table, 2. The vector generating apparatus according to claim 1, further comprising means for prohibiting writing to the video memory.