JP2752995B2 - Integral processing unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to an integration processing device with a small quantization error suitable for use in a digital adaptive filter or the like.

(Prior Art) An adaptive filter is widely used as a main component of an echo canceller device, an equalizer device, and the like. FIG. 2 shows a basic example of use of this type of adaptive filter. For example, in the case of an echo canceller,
For the unknown system 1 forming a path (echo path), the adaptive filter 2 functions as a system for generating a pseudo echo signal.
Then, the subtractor 3 subtracts the pseudo echo signal _(k) generated by the adaptive filter 2 from the echo signal y _(k) output through the unknown system 1 with respect to the input signal x _(k) . By
The echo signal y _(k) is canceled. Here, the identification of the unknown system 1 is performed by changing the tap coefficient of the adaptive filter 2 so as to minimize the power of the output residual signal e _(k) of the subtractor 3 by a learning identification method, for example.

FIG. 3 shows a general configuration example of the adaptive filter 2, where 4 (4a, 4b, to 4n) is a tap delay line, and 5 (5a, 5b, to 5n).
+1) is a multiplier for multiplying the tap output of the tap delay line 4 by the tap coefficient hi _(k) obtained by the tap coefficient estimator (EST) 6, and 7 is the sum of the outputs of the multiplier 5 An accumulator that generates a pseudo echo signal _(k) .

In the adaptive filter 2 thus configured, the impulse response of the unknown system 1 is H = (h ₁ , h ₂ ,..., H _N ) ^T [where T indicates transposition. The unknown system 1 is estimated as follows using, for example, a learning identification method. That is, the output signal _(k) of the adaptive filter 2 is obtained by converting the input signal sequence X _(k) obtained as the tap output of the tap delay line 4 into X _(k) = (x _(k) , x _(k-1) ,. x _{(k−N + 1)} ) _Let ^T be the tap coefficient H _(k) output from the accumulator 6
Is given by _(k) = (h1 _(k) , h2 _(k) ,... HN _(k) ) ^T , _(k) = _(k) ^T · X _(k) (1) It is determined by executing the following calculation. Then, the residual signal e _(k) for the output y _(k) of the unknown system 1 is _obtained as e _(k) = y _(k) − _(k) ... (2). [However, 0 <α <2. ], The tap coefficient is corrected (updated) for each sample, and the estimation is performed.

The learning process proceeds as described above, and the tap coefficients converge as _(k) → H, and the unknown system 1 is identified.

In recent years, various attempts have been made to realize this type of adaptive filter 2 using a digital signal processor (DSP). Thus, the arithmetic unit of the DSP is usually configured by adopting a floating-point method in order to cover a wide dynamic range with a small word length.

FIG. 4 shows a configuration example of a digital multiplier of the floating-point system, which is composed of a decimal point multiplier 11, an adder 12, and normalization circuits 13 and 14 for normalizing the respective outputs. In this digital multiplier, two input data X and Y to be multiplied are, for example, an exponent part E and a mantissa part M, and X = 2E _(X) * M _(X) and Y = 2E _(Y) * M _{( Y)} , the operation of the mantissa part is performed as M _(Z) ′ = M _(X) * M _{(Y) by the} decimal point multiplier 11, and the operation of the exponent part is performed by the adder 12 as E _(Z) '= E _(X) + E _(Y) . Thereafter, the mantissa part is normalized (decimal point adjustment) in the normalization circuit 13, and the information is normalized below the exponent part in the normalization circuit 14, and the exponent part E _{(Z) of} the multiplication value Z is calculated. The mantissa M _(Z) is obtained, and the multiplication process is performed.

Thus, when such floating point multiplication is performed, the number of bits of data obtained by the decimal point multiplier 11 is doubled, and it is necessary to limit the word length in order to unify the data format. This word length restriction is performed by, for example, a rounding process or a round-down (round-up) process.
A quantization error occurs as shown in FIG. Although the quantization error in the rounding process shown in FIG. 5A is smaller than the quantization error in the truncation process shown in FIG. 5B, the rounding process is performed after the decimal point multiplier 11. It is necessary to provide a new rounding circuit in the stage. In this regard,
Since the truncation process only needs to block the output of the redundant bits from the decimal point multiplier 11, the truncation process is often employed exclusively in the above-mentioned floating-point multiplication. However, the quantization error generated by this truncation processing has the following problems.

That is, the tap coefficient correction processing shown in Expression (3) at the i-th tap in the above-described adaptive filter 2 (tap coefficient estimating unit 6) is performed as an integral operation in the DSP, for example, as shown in FIG. It can be expressed as an operation model composed of a coefficient memory 15, a floating point adder 16, and a floating point multiplier 17. Furthermore, the above floating point adder
16, the quantization errors δ _{h (k)} and δ _{d (k)} are considered when the quantization errors generated in the floating point multiplier 17 are considered.
The arithmetic model for the tap coefficient correction processing can be expressed as shown in FIG.

The tap coefficient h _(k) of the i-th tap stored in the tap coefficient memory 15 by such an arithmetic model is Will be executed as Then, generally, when e _(k) becomes zero (o) due to the convergence of the first item of the above equation, the tap coefficient correction processing here stops.

However, although the average value of the noise component shown in the second item is usually zero (o), it does not become zero in the case of the above-described truncation processing, which poses a serious problem. That is, the noise component δ _(k) (= δ _{h (k)} + δ _{d (k)} ) of the second term diverges due to the convergence of the tap coefficients.

Specifically, assuming that the tap coefficients converge by (k → ∞), the component of the quantization error at that time is (However, is the average value) and diverges in the negative direction. And the value may be larger than the tap coefficient h _(k) .

(Problems to be Solved by the Invention) As described above, in the conventional integration operation by the DSP, for example, the tap coefficient correction processing, there is a disadvantage that the quantization error is cumulatively increased by the truncation processing. Therefore, there is a problem that the conversion error increases accumulatively. Therefore, in the digital integration processing used for the tap coefficient correction processing and the like, there is a problem in adopting a simple truncation processing of the processing procedure.

The present invention has been made in view of such circumstances,
An object of the present invention is to provide an integration processing device that realizes an effective digital integration operation while suppressing the divergence of a quantization error without causing a complicated processing procedure.

(Means for Solving the Problems) An integration processing device according to the present invention includes an integration accumulator for storing integration data, and subtracting the integration data read by the integration accumulator from the integrand data. A floating-point subtractor that outputs integration data whose polarity is alternately inverted for each subtraction and stores the integration data in the integration accumulator; and Sometimes, the polarity of the integrand data is set to negative polarity and supplied to the floating-point subtractor. On the other hand, when the polarity of integral data supplied from the integration accumulator to the floating-point subtractor is negative, the integrand data is set. And an integrand data supply circuit for setting the polarity of the data to a positive polarity and supplying the data to the floating-point subtractor. It is.

That is, the present invention is characterized in that the integration operation conventionally performed by addition is realized by subtraction and alternate inversion of the polarity of the integrand data.

(Operation) According to the present invention, since the polarity of the integrand data is inverted in accordance with the polarity of the integration data stored in the integration accumulator and then the subtraction process is performed, the data obtained by this subtraction is one. The polarity is inverted each time the subtraction process is performed. However, if attention is paid to the absolute value, the integrand data is sequentially added, and the integration operation is realized here.

At this time, since the quantization error caused by the rounding-down processing of the integration processing is also inverted every time, the rounding-up and rounding-up processing is substantially repeated alternately. The addition and subtraction of the quantization error component generated by the integration process are repeated each time.
On average, it is zero (0), so that it does not diverge as in the prior art. As a result, the occurrence of the quantization error can be effectively suppressed, and the integration operation can be easily and effectively executed.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing an operation model in an integration processing device according to an embodiment of the present invention, and shows an example applied to the tap coefficient correction processing described above.

This tap coefficient correction operation realizes essentially the same operation function as the operation process shown in FIG. 7, but uses a floating point subtractor 21 instead of the floating point adder 16, and It is characterized in that the data supplied to the floating-point multiplier 17 is inverted via the switch 22 for each integration process.

That is, the floating-point subtractor 21 subtracts the integral data stored in the tap coefficient memory 15 from the integrand data given from the floating-point multiplier 17, and uses the subtracted value as new integral data in the tap coefficient memory 15. Is to be stored. The adder 18 represents the quantization error Δh _(k) generated by the floating-point subtractor 21 as a model, and the adder 19 generates the quantization error Δd _(k) generated by the floating-point multiplier 17. Is expressed as a model.

When the integrated data (tap coefficient (hi _(k) ) read from the tap coefficient memory 15 to the floating point subtractor 21 has a positive polarity, the switch 22 has a negative polarity as data to be given to the floating point multiplier 17. Data (−αe _(k) / ‖X _(k) ‖
² ) is selected, and the polarity of the integrand data given from the floating point multiplier 17 to the floating point subtractor 21 is negative. Conversely, integrated data (tap coefficient hi _(k) ) read from the tap coefficient memory 15 to the floating point subtractor 21
There when a negative polarity, the floating select positive data _{(αe (k) / ‖X (} k) || ²⁾ as data to be given to point multiplier 17, the floating point subtractor floating-point multiplier 17
The polarity of the integrand data given to 21 is positive.

According to such an integral operation model, when one integral operation is performed by the floating-point subtractor 21, the new integral data obtained by this operation has the polarity inverted. Therefore, the integration data (tap coefficient hi _(k) ) stored in the tap coefficient memory 15 is inverted every time. Then, the polarity of the data selected by the switch 22 is alternately inverted according to the integration data. As a result, the value (absolute value) of the integral data is inverted while the polarity is inverted, and the value is stored in the tap coefficient memory 15.
, And the integration process is realized here.

Here, the quantization error caused by the line segment operation model is considered as follows. That is, the correction operation of the tap coefficient by the above-described integral operation model is Can be expressed as This expression is Can be transformed as The quantization error component here is (-1) ^k (δ _{d (k)} + δ _{h (k)} ) = (− 1) ^k δ _(k) shown in the third term, and the tap coefficient h ₍ The value of the quantization error when _k) converges, assuming that the quantization error δ _(k) that occurs each time is stationary. Becomes That is, it is possible to prevent the divergence of the quantization error and to keep its value on average zero (0). In other words, 1
The quantization error caused by the rounding process in the first integration operation is compensated (canceled) by the polarity-reversed rounding (rounding up) in the next integration operation, and the quantization error due to the rounding process is reduced to zero (0) on average. It can be suppressed.

As described above, according to the present apparatus, when performing the integration operation using the truncation process, the occurrence (increase; divergence) of the quantization error can be effectively suppressed, so that the integration operation accuracy is sufficiently increased. be able to. Moreover, since the rounding processing is not required unlike the related art, the processing function configuration can be made very simple, and it can be easily applied to the arithmetic processing by the DSP. Therefore, the present invention can be effectively applied to various digital integration calculations including the tap coefficient correction calculation described above.

Note that the present invention is not limited to the above-described embodiment. Here, the correction operation of the tap coefficient has been described as an example.
Basically, the integration process can be realized only by inverting the polarity of the integrand data input to the floating-point subtractor 21. The integration operation including the polarity inversion processing can be realized not only by dedicated hardware but also by software. In addition, the present invention can be variously modified and implemented without departing from the gist thereof.

[Effects of the Invention] As described above, according to the present invention, an integration operation using a truncation process can be performed with high accuracy without causing an increase in quantization error due to the truncation process,
For example, the present invention has a great practical effect, such as being able to be effectively applied to a tap coefficient correction operation in an echo canceller device.

[Brief description of the drawings]

FIG. 1 is a diagram showing an operation function model of an integration processing device according to an embodiment of the present invention, FIG. 2 is a diagram showing a use model of a general adaptive filter, and FIG. 3 is a configuration example of an adaptive filter. FIG. 4 is a diagram showing a configuration example of a floating point multiplier, FIG. 5 is a diagram showing a quantization error characteristic in floating point multiplication, and FIGS. 6 and 7 are arithmetic functions of a conventional digital integrator. It is a figure showing a model. 15 Tap memory (accumulator for integration), 17
...... Floating point multiplier, 18, 19 ... Adder, 21 ... Floating point subtractor, 22 ... Switch (polarity inversion processing).

 ──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Hiroshi Oikawa Nippon Telegraph and Telephone Corporation, 1-6-1, Uchisaiwai-cho, Chiyoda-ku, Tokyo (56) References JP-A-62-111514 (JP, A) 54-2053 (JP, B2) JP-B 55-24728 (JP, B2)

Claims (1)

(57) [Claims] An integration accumulator for storing integration data; subtracting the integration data read by the integration accumulator from the integrand data; A floating-point subtractor that outputs integration data whose polarity is alternately inverted for each subtraction and stores the integration data in the integration accumulator; If the polarity of the integrated data supplied to the floating-point subtractor from the integrating accumulator is negative, the polarity of the integrand data is set to negative polarity and supplied to the floating-point subtractor. An integrated data supply circuit for setting the polarity of the integrated data to positive polarity and providing the integrated data to the floating-point subtractor. Integrating process and wherein the.