JP2882102B2 - Electronic components - Google Patents
Electronic componentsInfo
- Publication number
- JP2882102B2 JP2882102B2 JP3170968A JP17096891A JP2882102B2 JP 2882102 B2 JP2882102 B2 JP 2882102B2 JP 3170968 A JP3170968 A JP 3170968A JP 17096891 A JP17096891 A JP 17096891A JP 2882102 B2 JP2882102 B2 JP 2882102B2
- Authority
- JP
- Japan
- Prior art keywords
- leads
- electronic component
- tab
- directions
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5366—Shapes of wire connectors the bond wires having kinks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明は電子部品に係り、2方向
にリードを有する2個のTABチップを積み重ねて、4
方向にリードを有する電子部品としたものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic component, in which two TAB chips having leads in two directions are stacked,
This is an electronic component having leads in the directions.
【0002】[0002]
【従来の技術】電子部品として、図4に示すように、モ
ールド体101から2方向にリード102が延出する電
子部品P1(一般にSOPと呼ばれる)や、図5に示す
ように、モールド体103から4方向にリードが延出す
る電子部品P2(一般にQFPと呼ばれる)が知られて
いる。2. Description of the Related Art As an electronic component, as shown in FIG. 4, an electronic component P1 (generally called an SOP) in which leads 102 extend from a molded body 101 in two directions, or as shown in FIG. There is known an electronic component P2 (generally referred to as QFP) having leads extending in four directions.
【0003】[0003]
【発明が解決しようとする課題】QFPの方がSOPよ
りも集積度が高く、したがって基板の高集積化の点にお
いて、SOPはQFPよりも不利である。The QFP has a higher degree of integration than the SOP. Therefore, the SOP is disadvantageous to the QFP in terms of the higher integration of the substrate.
【0004】そこで本発明は、2方向のリードを有する
チップにより、QFPと同様の4方向のリードを有する
電子部品が得られる手段を提供することを目的とする。Accordingly, an object of the present invention is to provide means for obtaining an electronic component having the same four-way leads as a QFP using a chip having two-way leads.
【0005】[0005]
【課題を解決するための手段】このために本発明は、2
方向にリードを有する2個のTABチップを互いに表裏
反転させるとともに、相対的に90°水平回転させて積
み重ね、これらのTABチップをモールド体にてモール
ドして一体化したものである。For this purpose, the present invention provides a method for producing
Two TAB chips having leads in the directions are turned upside down and rotated horizontally by 90 ° to be stacked, and these TAB chips are integrated by molding in a mold.
【0006】[0006]
【作用】上記構成によれば2方向にリードを有する2個
のTABチップを一体化して、実質的に4方向のリード
を有する電子部品を形成できる。According to the above construction, two TAB chips having leads in two directions can be integrated to form an electronic component having leads in four directions.
【0007】[0007]
【実施例】次に、図面を参照しながら本発明の実施例を
説明する。Next, an embodiment of the present invention will be described with reference to the drawings.
【0008】図1は本発明に係る電子部品Pを示してい
る。また図2(a)(b)は、図1のX−X,Y−Y断
面を示している。この電子部品Pは、2個のTABチッ
プ1A,2Aを積み重ね、モールド体5でモールドして
一体化したものである。FIG. 1 shows an electronic component P according to the present invention. FIGS. 2 (a) and 2 (b) show cross sections taken along line XX and YY of FIG. This electronic component P is obtained by stacking two TAB chips 1A and 2A, molding them with a mold body 5, and integrating them.
【0009】このTABチップ1A,2Aは、半導体チ
ップ1B,2Bから2方向にリード1C,2Cを有する
SOPと同様のものであって、各々の半導体チップ1
B,2Bとリード1C,2Cは、フィルムキャリヤを打
ち抜いて形成されたリード1D,2Dにより接続されて
いる。この電子部品Pは、TABチップ1A,2Aを後
述する手段により2個積み重ねることにより、4方向に
リード1C,2Cを有するQFPと同様の電子部品にな
っている。a,bは各々の半導体チップ1B,2Bの回
路形成面である。The TAB chips 1A, 2A are similar to SOPs having leads 1C, 2C in two directions from the semiconductor chips 1B, 2B.
B, 2B and leads 1C, 2C are connected by leads 1D, 2D formed by punching a film carrier. This electronic component P is the same electronic component as a QFP having leads 1C and 2C in four directions by stacking two TAB chips 1A and 2A by means described later. a and b are circuit forming surfaces of the respective semiconductor chips 1B and 2B.
【0010】図3は上記電子部品Pの製造方法を示して
いる。図3(a)において、まず一方のTABチップ2
Aのリード2Dをリードフレーム2C’に着地させ、リ
ード2Dをリードフレーム2C’に熱溶着する。熱溶着
手段としては、熱圧着子をリード2Dに押し付ける手段
や、レーザ光をリード2Dに照射する手段が知られてい
る。FIG. 3 shows a method of manufacturing the electronic component P. In FIG. 3A, first, one TAB chip 2
The lead 2D of A is landed on the lead frame 2C ', and the lead 2D is thermally welded to the lead frame 2C'. As the thermal welding means, there are known means for pressing a thermocompressor against the lead 2D and means for irradiating the lead 2D with a laser beam.
【0011】次いでこのTABチップ2Aを垂直方向に
180°回転させて表裏反転させるとともに、90°水
平回転させる(図3(b))。Next, the TAB chip 2A is turned 180 ° in the vertical direction to be turned upside down and turned 90 ° horizontally (FIG. 3B).
【0012】次いで図3(c)に示すように、もう一方
のTABチップ1AをTABチップ2Aの上方から積み
重ね、リード1Dをリードフレーム1C’に熱溶着させ
る。このようにして、2個のTABチップ1A,2Aを
積み重ねたならば、モールドプレス手段によりモールド
体5を形成するとともに、リードフレーム1C’,2
C’を打ち抜いてリード1C,2Cをフォーミングする
ことにより、図1、図2に示す電子部品Pが得られる。Next, as shown in FIG. 3C, the other TAB chip 1A is stacked from above the TAB chip 2A, and the lead 1D is thermally welded to the lead frame 1C '. When the two TAB chips 1A and 2A are stacked in this way, the molded body 5 is formed by the mold pressing means, and the lead frames 1C 'and 2 are formed.
By punching C 'and forming the leads 1C and 2C, the electronic component P shown in FIGS. 1 and 2 is obtained.
【0013】すなわち本手段は、2方向にリードを有す
るTABチップを一体化して、4方向にリードを有する
1個の電子部品Pとしているので、従来2個基板に実装
していたものを、1個の電子部品Pを実装すればよいこ
ととなり、したがって基板をそれだけ小形高集積化でき
るとともに、実装時間も半減できる。In other words, the present means integrates a TAB chip having leads in two directions into one electronic component P having leads in four directions. It suffices to mount the electronic components P, so that the substrate can be made smaller and highly integrated, and the mounting time can be reduced by half.
【0014】ところで、TABチップ以外の通常の電子
部品は、半導体チップの電極とリードフレームの電極と
を、ワイヤにより接続して形成される。この接続(ワイ
ヤリング)は、ワイヤボンダのキャピラリツールをUS
振動させながら、ワイヤを上記電極に押し付けることに
より行われる。この場合、US振動を有効に働かせるた
めには、リードフレームを下方からバックアップしてい
なければならない。ところがTABチップでない通常の
チップを図3(b)に示すように積み重ねてワイヤリン
グしようとしても、下側のチップが存在するために、リ
ードフレームをバックアップできず、したがってキャピ
ラリツールのUS振動は有効に働かず、ワイヤリングは
出来ないこととなる。By the way, ordinary electronic components other than the TAB chip are formed by connecting electrodes of a semiconductor chip and electrodes of a lead frame with wires. This connection (wiring) uses the capillary tool of the wire bonder to US
This is performed by pressing the wire against the electrode while vibrating. In this case, in order to effectively use the US vibration, the lead frame must be backed up from below. However, even if a normal chip that is not a TAB chip is stacked and wired as shown in FIG. 3B, the lead frame cannot be backed up due to the presence of the lower chip, so that the US vibration of the capillary tool is effectively reduced. It doesn't work and wiring is not possible.
【0015】これに対し、本発明のように、チップとし
てTABチップを使用すれば、リード1D,2Dとリー
ドフレーム1C’,2C’はUS振動が不要な熱溶着手
段やレーザ手段により接続できるので、上記電子部品P
を製造することが可能となる。On the other hand, if a TAB chip is used as the chip as in the present invention, the leads 1D, 2D and the lead frames 1C ', 2C' can be connected by heat welding means or laser means which does not require US vibration. , The electronic component P
Can be manufactured.
【0016】[0016]
【発明の効果】以上説明したように本発明は、2方向に
リードを有する2個のTABチップを互いに表裏反転さ
せるとともに、相対的に90°水平回転させて積み重
ね、これらのTABチップをモールド体にてモールドし
て一体化して電子部品を形成しているので、2方向にリ
ードを有するTABチップにより、4方向にリードを有
する電子部品を得ることができ、実質的な高集積化を図
れる。As described above, according to the present invention, two TAB chips having leads in two directions are turned upside down and horizontally rotated by 90 ° to be stacked, and these TAB chips are molded. Since the electronic components are integrated by molding with the above, an electronic component having leads in four directions can be obtained by a TAB chip having leads in two directions, and substantial high integration can be achieved.
【図1】本発明に係る電子部品の平面図FIG. 1 is a plan view of an electronic component according to the present invention.
【図2】本発明に係る電子部品の断面図FIG. 2 is a sectional view of an electronic component according to the present invention.
【図3】本発明に係る電子部品の製造工程図FIG. 3 is a manufacturing process diagram of an electronic component according to the present invention.
【図4】従来のSOPの平面図FIG. 4 is a plan view of a conventional SOP.
【図5】従来のQFPの平面図FIG. 5 is a plan view of a conventional QFP.
1A TABチップ 2A TABチップ 1C リード 2C リード 5 モールド体 P 電子部品 1A TAB chip 2A TAB chip 1C lead 2C lead 5 Molded body P Electronic component
Claims (1)
プを互いに表裏反転させるとともに、相対的に90°水
平回転させて積み重ね、これらのTABチップをモール
ド体にてモールドして一体化したことを特徴とする電子
部品。1. A method in which two TAB chips having leads in two directions are turned upside down and rotated by 90 ° horizontally to be stacked, and these TAB chips are integrated by molding in a mold. Electronic components characterized by the following.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3170968A JP2882102B2 (en) | 1991-07-11 | 1991-07-11 | Electronic components |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3170968A JP2882102B2 (en) | 1991-07-11 | 1991-07-11 | Electronic components |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0521702A JPH0521702A (en) | 1993-01-29 |
| JP2882102B2 true JP2882102B2 (en) | 1999-04-12 |
Family
ID=15914705
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3170968A Expired - Fee Related JP2882102B2 (en) | 1991-07-11 | 1991-07-11 | Electronic components |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2882102B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4097403B2 (en) * | 1998-12-02 | 2008-06-11 | 株式会社ルネサステクノロジ | Semiconductor device |
-
1991
- 1991-07-11 JP JP3170968A patent/JP2882102B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0521702A (en) | 1993-01-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4412439B2 (en) | Memory module and manufacturing method thereof | |
| US5554886A (en) | Lead frame and semiconductor package with such lead frame | |
| JP2882102B2 (en) | Electronic components | |
| US5310701A (en) | Method for fixing semiconductor bodies on a substrate using wires | |
| JPS62142341A (en) | Semiconductor device and manufacture thereof | |
| JPH0322544A (en) | Semiconductor device | |
| JPS6180842A (en) | Semiconductor device | |
| JPH0349246A (en) | Semiconductor integrated circuit device | |
| JPH06104295A (en) | Soldering of hybrid ic | |
| JPS6352455A (en) | Lead frame for sealed semiconductor device | |
| JPH1140563A (en) | Semiconductor device and method for changing electrical characteristics thereof | |
| JPS6332269B2 (en) | ||
| JP2913858B2 (en) | Hybrid integrated circuit | |
| JPS61225827A (en) | Mounting structure of semiconductor element | |
| JP2692904B2 (en) | Semiconductor device with built-in diode chip and manufacturing method thereof | |
| JPH04237179A (en) | Semiconductor laser device | |
| JP2507271Y2 (en) | Semiconductor device | |
| JPH0266965A (en) | Manufacture of semiconductor device | |
| JPH06244313A (en) | Semiconductor package and mounting method | |
| JPH0636586Y2 (en) | Heat sink tape structure for semiconductor chip mounting | |
| JPS6339970Y2 (en) | ||
| JPS624353A (en) | Face-to-face junction type integrated circuit device | |
| JPH05343559A (en) | Package for semiconductor device | |
| JPH04326785A (en) | Optical semiconductor device | |
| JPH02181465A (en) | Packaging method of semiconductor chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |