JP2926344B2 - Method for manufacturing field effect transistor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure and a manufacturing method of an insulated gate field effect transistor, and more particularly to a channel stopper for effectively preventing punch-through and a short channel effect in a channel region. The present invention relates to a region configuration and a formation method.

[Conventional technology]

Conventionally, a source region and a drain region formed separately in a semiconductor substrate surface, a channel region formed between these regions, and a gate electrode formed on the channel region via a gate insulating film An insulated gate field effect transistor composed of the following is known. With the advance of integrated circuit technology, the miniaturization of transistors has progressed,
The length of the channel region is becoming shorter and shorter. Therefore, the depletion layers existing at both ends of the channel region are close to each other, causing a so-called short channel effect and punch-through. In order to prevent such a short channel effect and punch-through, a method of forming a channel stopper region has been proposed. The channel stopper region is a high-concentration impurity layer disposed below the channel region and prevents the depletion layer from spreading in the channel direction.

[Problems to be solved by the invention]

However, since the channel stopper region is a high-concentration impurity disposed below the channel region, its formation is extremely difficult and complicated. That is, an effective channel stopper region cannot be formed by the conventional ion implantation technique or impurity diffusion technique. In addition, conventionally, only a channel stopper region including a high-concentration impurity layer containing N-type impurity arsenic is known, and a channel stopper region including a P-type high-concentration impurity layer is not known.

[Means to solve the problem]

The present invention has been made in view of the above-described problems of the related art, and has a method of manufacturing an insulated gate field effect transistor capable of efficiently forming a channel stopper region, and a structure of an insulated gate field effect transistor having a P-type channel stopper region. The purpose is to provide.

In order to achieve the above object, a method of manufacturing an insulated gate field effect transistor according to the present invention includes a first step of removing an oxide film covering a first semiconductor layer of a first conductivity type and exposing a chemically active surface. And a second step of supplying a gas having a first conductivity type impurity component to the active surface to form an adsorption layer made of the first conductivity type impurity element, and having a predetermined thickness on the impurity layer. The method includes a third step of adding a second semiconductor layer, and a fourth step of sequentially forming a gate insulating film and a gate electrode on the added second semiconductor layer. Further on,
By selectively introducing a second conductivity type impurity into a semiconductor layer to a depth exceeding a horizontal position of the impurity layer with respect to a pair of regions planarly separated by a gate electrode to form a source region and a drain region A fifth region for defining a channel region on the surface of the second semiconductor layer between the source region and the drain region, and disposing a channel stopper region made of the first conductivity type impurity layer below the channel region; Process.

Preferably, in the second step, a gaseous diborane having a P-type impurity component, boron, is supplied to the active surface of the first semiconductor layer made of a P-type silicon substrate under heating of the substrate to cause the adsorption of boron to generate a P-type impurity. Forming a boron impurity layer. The third step is a step of forming a second semiconductor layer made of silicon on the impurity layer by epitaxial growth. The fifth step is a step of forming an N-type source region and a drain region by introducing an N-type impurity made of arsenic into a P-type semiconductor layer made of silicon by ion implantation.

The field-effect transistor manufactured by the above-described manufacturing method is defined between a P-type silicon semiconductor substrate, N-type source and drain regions formed on the surface of the semiconductor substrate, and between the source and drain regions. A channel stopper region formed of a P ⁺ -type impurity layer containing boron disposed below the channel region and above the bottom of the source region and the drain region, and a gate insulating film formed on the channel region. And a gate electrode formed on the gate insulating film.

[Action]

According to the present invention, first, the oxide film covering the surface of the semiconductor substrate is removed to expose the chemically active surface. A gas having an impurity component, for example, diborane is supplied to and adsorbed to the exposed active surface to form a P-type impurity layer. This adsorption is performed by heating the substrate, and an extremely stable thin P-type impurity layer is formed. The thickness of the impurity layer can be optimally set by adjusting the vapor pressure of the supplied gas and the supply time. Subsequently, a single crystal semiconductor layer is formed over the impurity layer by using, for example, an epitaxial growth method. further,
A gate insulating film and a gate electrode are sequentially formed over the single crystal semiconductor layer, and a source region and a drain region are formed in the semiconductor layer by a technique such as ion implantation using the gate electrode as a mask. At this time, it is necessary to appropriately set the acceleration voltage in the ion implantation and implant ions to a depth exceeding the horizontal position of the P-type impurity layer. As a result, a channel region is formed below the gate electrode that has not been irradiated with ions, and a P-type impurity layer is disposed below the channel region, so that a channel stopper region is formed. Can do things.

〔Example〕

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a process chart showing a method for manufacturing an insulated gate field effect transistor according to the present invention. First, as shown in FIG. 1A, a silicon single crystal substrate 1 is prepared.
The surface of the substrate 1 is usually covered with a natural oxide film 2.

In the step shown in FIG. 1B, the natural oxide film 2 is removed, and the active surface 3 of the silicon single crystal substrate 1 is exposed. This natural oxide film removing step is performed, for example, on the silicon single crystal substrate 1.
Is heated to 850 ° C. and maintained in a vacuum state of 10 ⁻⁴ Pa or less. At this time, when hydrogen gas is introduced, removal of the native oxide film 2 is promoted.

In the step shown in FIG. 1C, diborane gas (B ₂ H ₆ ) is supplied to the active surface 3. At this time, the substrate 1 is 80
It is heated to 0 ° C, and diborane is
50% at a vapor pressure of 1 × 10 ^-2 Pa
For a second. As a result, a P-type impurity layer 4 containing impurity boron at a high concentration is formed on the active surface 3 of the substrate 1. The film thickness was 100 ° or less. The P-type impurity layer 4 is firmly adsorbed on the active surface, and a part of boron diffuses into the semiconductor because the substrate is heated, thereby forming a stable impurity diffusion layer.

In the step shown in FIG. 1D, a silicon single crystal layer 5 is formed on P-type impurity layer 4. The formation of the silicon single crystal layer 5 is performed by, for example, an epitaxial growth method.
Grow on. In this embodiment, silane gas (Si
H ₄ ) was introduced at a vapor pressure of 0.1 Pa, and the substrate was heated to 800 ° C. to grow a silicon single crystal. In addition, as the epitaxial growth technique, a molecular layer epitaxial growth method, a molecular beam epitaxial growth method, a chemical vapor deposition method, or the like can be used.

In the step shown in FIG. 1E, a gate oxide film 6 is formed on silicon single crystal layer 5. The gate oxide film 6 is formed, for example, by heating the substrate 1 to 800 ° C. and simultaneously introducing oxygen gas and hydrogen gas to perform wet oxidation.

In the step shown in FIG. 1 (F), gate electrode 7 is formed on gate oxide film 6. The gate electrode 7 is obtained, for example, by forming a silicon polycrystalline layer on the entire surface of the gate oxide film 6 and performing etching according to a predetermined pattern. The silicon polycrystalline layer is formed, for example, by chemical vapor deposition.
Deposited on the gate oxide film with a thickness of 00Å to 4000Å.

In the step shown in FIG. 1 (G), a source region 8 and a drain region 9 are formed. These regions are formed by selectively injecting an N-type impurity, for example, arsenic into a pair of regions separated in a plane by the gate electrode 7. Arsenic is implanted, for example, by ion implantation. The conditions are, for example, arsenic ion acceleration voltage 90ke
V, the dose amount is 7 × 10 ¹⁵ / cm ² . This ion implantation is performed for a predetermined time. The implanted arsenic is made to reach a depth exceeding the horizontal position of the P-type impurity layer 4. As a result, the source region 8 and the drain region 9 are formed by the implanted N-type impurity arsenic, and the P-type impurity layer 4 existing in these regions is neutralized by the implanted N-type impurity arsenic. Virtually disappears. Since arsenic ion implantation is performed using the gate electrode 7 as a mask, a P ⁻ type channel region 10 is formed under the gate electrode 7. Further, under the channel region 10, the P-type impurity layer 4 is left as it is.
Is stored and becomes the channel stopper region 11.

In the step shown in FIG.
Heat treatment is performed for 0 minutes to diffuse and activate the impurity boron contained in the channel stopper region 11 into the upper and lower semiconductor layers 10 and 1. As a result, the channel stopper region 11 becomes a P ⁺ type high concentration impurity diffusion layer. By this heat diffusion treatment, the channel stopper region 11 has a layer thickness expanded to 500 to 1000 ° and an impurity boron concentration of 1 to 1.
It is about 0 ¹⁷ / cm ² . Note that this heat diffusion treatment is not always necessary, and the absorbed P-type impurity layer 4 has undergone a thermal history in each step, and therefore, the impurity diffusion between the upper and lower semiconductor layers to some extent has occurred. it is conceivable that.

Finally, as shown in FIG. 1 (I), an interlayer insulating film is formed on the substrate 1.
12 are formed, and a contact hole is formed by etching. The wiring film 13 is formed thereon.

According to the manufacturing method of the present invention, the channel stopper region 11 can be formed by a simple method below the channel region. The channel stopper region limits the spread of the depletion layer existing at both ends of the channel region, and can effectively prevent punch-through and short channel effects. Therefore,
Since the channel length can be reduced as compared with the related art, the transistor element can be further miniaturized.

As is clear from the above description, the main parts of the manufacturing method according to the present invention are a substrate surface cleaning step (FIG. 1 (B)), an impurity layer adsorption step (FIG. 1 (C)), and a silicon unit. It is in a series of processes of a crystal layer epitaxial growth step (FIG. 1 (D)). Hereinafter, the main part of the present invention will be described in more detail. FIG. 2 is an example of an actual process sequence chart corresponding to this series of processing. The horizontal axis in FIG. 2 is time,
The vertical axis indicates the substrate temperature. Substrate temperature 850
After the temperature is raised to ℃ and stabilized, the substrate surface is cleaned to expose the active surface. Then raise the substrate temperature to 800 ° C
Then, a diborane gas is introduced to form a boron impurity adsorption layer. Subsequently, a silicon single crystal layer is epitaxially grown on the adsorption layer.

FIG. 3 is a block diagram of an apparatus used for the above series of processing. As shown in the drawing, the silicon single crystal substrate 1 is disposed near the center of the inside of a quartz chamber 22. Substrate 1
Is maintained at a predetermined temperature by controlling a heating system 23 using an infrared lamp heating method or a resistance heating method. The inside of the chamber 22 can be evacuated using a high vacuum evacuation system 24 composed of a plurality of pumps using a turbo molecular pump as a main evacuation pump. The degree of vacuum inside the chamber 22 is measured by a pressure gauge 25. The transfer of the silicon substrate 1 is performed by a gate valve 26 between a load chamber 27 connected to the chamber 22 via a gate valve 26a and the chamber 22.
This is performed using the transport mechanism 28 with a opened. The load chamber 27 is normally evacuated to a high vacuum by the load chamber exhaust system 29 with the gate valve 26b opened except when the silicon substrate 1 enters and leaves the load chamber 27 and during transport. A gas supply source 31 is connected to the chamber 22 via a gas introduction control system 30. The gas supply source 31 includes a plurality of gas cylinders for storing various source gases used for a series of processes. The type, amount, and duration of gas introduced from the gas supply source 31 to the chamber 22 are controlled using the gas introduction control system 30.

An example in which a series of processes are performed using the manufacturing apparatus shown in FIG. 3 according to the process sequence chart shown in FIG. 2 will be described. The silicon substrate 1 is set at the center of a vacuum chamber 22 evacuated to a background pressure of 1 × 10 ⁻⁴ Pa or less. Next, the substrate temperature was increased to 850 using the heating system 23.
C. and hydrogen gas is introduced from the gas supply source 31 for a certain period of time under conditions such that the pressure inside the chamber becomes 1.3 × 10 ⁻² Pa, for example. As a result, the natural oxide film formed on the surface of the silicon substrate 1 is removed, and the chemically active silicon surface is exposed. After the cleaning of the substrate surface is completed, the introduction of hydrogen gas is stopped and the substrate temperature is set to, for example, 800 ° C. After the temperature reaches the set temperature and becomes stable, diborane, which is a compound gas containing boron, is supplied from the gas supply source 31 to the active surface of the silicon substrate 1. The pressure in chamber 22 is 6.5
By introducing for a certain period of time under the condition of × 10 ^-4 Pa,
An adsorption layer of boron or a compound containing boron is formed. This adsorption layer is firmly fixed to the active surface and is extremely stable. At the same time as the formation of the boron adsorption layer, it is considered that boron is diffused into the bulk in a fixed case determined by the substrate temperature and the diborane introduction pressure during diborane introduction.

As shown in FIG. 4, the peak concentration of boron in the adsorption diffusion layer is proportional to the introduction pressure and introduction time of diborane gas. Therefore, by appropriately setting these parameters, an optimum boron peak concentration can be obtained.

Finally, with the substrate temperature kept at 800 ° C., a silicon single crystal layer in which silane gas (SiH ₄ ) or dichlorosilane gas (SiH ₂ Cl ₂ ) is introduced from the gas supply source 31 into the chamber 22 is epitaxially grown. Note that an epitaxial growth layer of silicon may be formed on the active surface of the silicon substrate as a base treatment before forming the boron adsorption layer.

In the embodiment described above, diborane gas is used to form a P-type channel stopper region inside a silicon semiconductor. However, to form a P-type impurity adsorption layer, for example, trimethylgallium (TMG),
A gaseous compound of a group III element represented by boron trichloride (BCl ₃ ) is also effective. The gaseous compound used to form the N-type impurity adsorption layer of the active surface of the silicon semiconductor addition, arsine (A _S H _3), phosphorus trichloride (PC
l ₃ ), antimony pentachloride (SbCl ₅ ), phosphine (PH ₃ )
Etc. are available.

In the above-described embodiments, typical values of the substrate temperature are 850 ° C. in the surface cleaning treatment, 800 ° C. in the impurity adsorption treatment, and 800 ° C. in the epitaxial growth treatment. The inventors have found in the previous studies that the substrate temperature in the surface cleaning treatment is preferably in the range of 800 ° C. to 1200 ° C., including the relationship between the background pressure and the atmospheric gas. It has been confirmed that the temperature is preferably in the range of 400 ° C. to 950 ° C., and the substrate temperature in the epitaxial growth process is preferably in the range of 800 ° C. to 1100 ° C.

〔The invention's effect〕

According to the present invention, the channel stopper region can be formed very efficiently under the channel region of the insulated gate field effect transistor by a series of steps of the cleaning process of the semiconductor substrate, the adsorption process of the impurity layer, and the epitaxial growth process of the semiconductor layer. This has the effect. By providing this channel stopper region, punch-through or short channel effect of the channel region can be effectively prevented,
As a result, there is an effect that the transistor element can be further miniaturized.

[Brief description of the drawings]

1 (A) to 1 (I) are manufacturing process diagrams of an insulated gate field effect transistor, FIG. 2 is a process sequence chart of the manufacturing process, FIG. 3 is a schematic diagram of a manufacturing apparatus used in the manufacturing process, and FIG. The figure is a graph showing the dependency of the impurity diffusion concentration on the source gas introduction pressure and the introduction time. DESCRIPTION OF SYMBOLS 1 ... Silicon single crystal substrate, 2 ... Natural oxide film 3 ... Active surface, 4 ... P-type impurity layer 5 ... Silicon single crystal layer, 6 ... Gate oxide film 7 ... Gate electrode, 8 ... Source region 9: drain region, 10: channel region 11: channel stopper region

Claims (4)

(57) [Claims] A step of removing an oxide film covering a surface of a p-type silicon substrate to expose a chemically active surface; and supplying a gas having a p-type impurity component containing boron to the active surface. Adsorbing the impurity component element or the compound of the impurity component while heating to form a P-type impurity layer containing boron having a thickness of 100 ° or less; and forming the impurity with a predetermined thickness on the impurity layer. A step of forming a silicon layer by epitaxial growth thicker than a layer, a step of sequentially forming a gate insulating film and a gate electrode on the silicon layer, and a pair of steps on a surface of the silicon substrate separated in plane by the gate electrode. Forming a source region and a drain region selectively by introducing an N-type impurity into the silicon substrate to a depth exceeding a horizontal position of the impurity layer with respect to the region. A channel stopper is defined between the source region and the drain region on a surface portion of the silicon layer, and a channel stopper formed of the P-type impurity layer that is thinner than the thickness of the channel region below the channel region. A method for manufacturing a field effect transistor, comprising arranging regions. 2. The method according to claim 1, further comprising a heating step of diffusing impurities contained in the impurity layer into the upper and lower silicon substrates and the silicon layer and activating them. 3. The method according to claim 1, wherein the gas having a P-type impurity component containing boron is diborane. 4. The method according to claim 1, wherein the step of forming the source region and the drain region is a step of forming an N-type impurity made of arsenic into the silicon layer by ion implantation. Method.