JP2988815B2 - Liquid crystal drive - Google Patents
Liquid crystal driveInfo
- Publication number
- JP2988815B2 JP2988815B2 JP28328893A JP28328893A JP2988815B2 JP 2988815 B2 JP2988815 B2 JP 2988815B2 JP 28328893 A JP28328893 A JP 28328893A JP 28328893 A JP28328893 A JP 28328893A JP 2988815 B2 JP2988815 B2 JP 2988815B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- liquid crystal
- gradation
- correction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Liquid Crystal (AREA)
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は液晶駆動装置に係り、詳
細には階調信号補正回路を内蔵し、液晶セルの特性に応
じて輝度信号のパルス幅を制御し階調特性を均等にし得
る液晶駆動装置に係る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal driving device, and more particularly, to a liquid crystal driving device having a built-in gradation signal correction circuit, which can control the pulse width of a luminance signal in accordance with the characteristics of a liquid crystal cell to equalize gradation characteristics. The present invention relates to a liquid crystal driving device.
【０００２】[0002]
【従来の技術】図６は従来の液晶駆動装置の構成の一例
を示す図、図７は従来の階調基本信号を示す図である。2. Description of the Related Art FIG. 6 is a diagram showing an example of the configuration of a conventional liquid crystal driving device, and FIG. 7 is a diagram showing a conventional gradation basic signal.
【０００３】図６において、２０は基本階調信号生成回
路、２１は階調デ−タメモリ、２２はラインデ−タメモ
リ、２３は階調信号選択回路、２４は液晶駆動回路であ
る。図６において、Ｎビットの階調デ−タＫＤ0 〜ＫＤ
Nは読み込み信号１によって階調デ−タメモリ２１にＮ
ビット単位で順次書き込まれ、１走査線分のデ−タが揃
った時点でロ−ド信号によりラインデ−タメモリ２２に
転送され、次のロ−ド信号が入力されるまで１走査線分
のデ−タが保持され、この階調デ−タが階調信号選択回
路２３に転送される。In FIG. 6, reference numeral 20 denotes a basic gradation signal generation circuit, 21 denotes a gradation data memory, 22 denotes a line data memory, 23 denotes a gradation signal selection circuit, and 24 denotes a liquid crystal driving circuit. In FIG. 6, N-bit gradation data KD 0 to KD
N is stored in the gradation data memory 21 by the read signal 1
The data is sequentially written in bit units, and when the data for one scanning line is completed, the data is transferred to the line data memory 22 by a load signal, and the data for one scanning line is input until the next load signal is input. , And this gradation data is transferred to the gradation signal selection circuit 23.
【０００４】基本階調信号生成回路２０では、基本クロ
ックに同期して動作するカウンタにより、図７に示すよ
うな１走査期間を階調数に応じて分割した基本階調信号
Ｋ0〜Ｋn を生成する。そして、階調信号選択回路２３
では階調デ−タに応じた基本階調信号Ｋ0 〜Ｋn を選択
し、液晶駆動回路２４に伝え輝度信号として出力してい
る。In the basic gray scale signal generation circuit 20, basic gray scale signals K 0 -K n obtained by dividing one scanning period according to the number of gray scales as shown in FIG. Generate Then, the gradation signal selection circuit 23
Selects the basic gradation signals K0 to Kn according to the gradation data, transmits them to the liquid crystal drive circuit 24, and outputs them as luminance signals.
【０００５】[0005]
【発明が解決しようとする課題】図８は液晶セルの電気
的光学特性を示す図、図９は従来の階調レベルと印加電
圧との関係を示す図である。FIG. 8 is a diagram showing the electrical and optical characteristics of a liquid crystal cell, and FIG. 9 is a diagram showing the relationship between a conventional gradation level and an applied voltage.
【０００６】図８は液晶セルの印加電圧に対する透過率
の特性例であり、実線で示した特性１と破線で示した特
性２が環境等の変化で変動する範囲である。FIG. 8 shows an example of the characteristics of the transmittance with respect to the applied voltage of the liquid crystal cell, in which the characteristic 1 indicated by a solid line and the characteristic 2 indicated by a broken line vary in a change in environment or the like.
【０００７】例えば、特性１が通常環境下での特性、特
性２が環境等の変化で変動した特性とすると、透過率５
０％の階調レベルにしたい場合、特性１では液晶セルに
印加する電圧を電圧Ｖm に、特性２では電圧ＶＨm にし
なければならないことは図８から自明である。For example, if the characteristic 1 is a characteristic under a normal environment and the characteristic 2 is a characteristic fluctuating due to a change in an environment or the like, the transmittance 5
It is obvious from FIG. 8 that the voltage applied to the liquid crystal cell should be set to the voltage Vm in the case of the characteristic 1 and the voltage VHm in the case of the characteristic 2 when the gradation level should be 0%.
【０００８】従来の技術では、図７に示すように１走査
期間を階調数に応じて分割したパルスを階調信号として
使用していたため、図９に示すように階調レベルに対応
した印加電圧が固定されてしまい、液晶セルの特性に応
じた電圧を印加することはできない。In the prior art, as shown in FIG. 7, a pulse obtained by dividing one scanning period in accordance with the number of gray scales is used as a gray scale signal. Therefore, as shown in FIG. Since the voltage is fixed, it is impossible to apply a voltage according to the characteristics of the liquid crystal cell.
【０００９】従って、従来技術では液晶材料や使用環境
により液晶セルの印加電圧に対する透過率の特性が変わ
った場合、階調レベルを均等に得ることができなかっ
た。Therefore, in the prior art, when the characteristics of the transmittance with respect to the applied voltage of the liquid crystal cell change depending on the liquid crystal material and the use environment, it is not possible to obtain a uniform gradation level.
【００１０】本発明の目的は、液晶セルの印加電圧に対
する透過率の特性が変化しても階調レベルを均等に得る
ことができる液晶駆動装置を提供することにある。It is an object of the present invention to provide a liquid crystal driving device capable of obtaining a uniform gradation level even if the characteristics of transmittance with respect to an applied voltage of a liquid crystal cell change.
【００１１】[0011]
【課題を解決するための手段】本発明の液晶駆動装置
は、１走査期間内における選択期間と非選択期間とのパ
ルス幅の比率に関して調整自在な信号を出力する補正回
路と、補正回路から出力される信号に基づいて液晶を駆
動する手段とを具備する液晶駆動装置であって、補正回
路は、１走査期間を階調数に応じて分割し、異なったパ
ルス幅比率の信号を生成する基本階調信号生成回路と、
パルス幅比率を階段的に補正するｎビットの補正データ
を記憶する補正データ記憶回路と、補正データ記憶回路
に記憶されているｎビットの補正データに応じて、２ ｎ
段階の範囲で、基本階調信号生成回路の出力信号のパル
ス幅を調整するパルス幅制御回路とを含むことを特徴と
する。A liquid crystal driving device according to the present invention comprises a correction circuit for outputting a signal which can be adjusted with respect to a pulse width ratio between a selection period and a non-selection period within one scanning period, and an output from the correction circuit. based on a signal to a liquid crystal driving device and means for driving the liquid crystal, the correction times
The path divides one scanning period according to the number of gradations, and
A basic gradation signal generation circuit for generating a signal having a pulse width ratio;
N-bit correction data for correcting the pulse width ratio stepwise
Data storage circuit for storing data and correction data storage circuit
2 n according to the n-bit correction data stored in
In the range of steps, the pulse of the output signal of the basic gradation signal generation circuit is
And a pulse width control circuit for adjusting the pulse width .
【００１２】[0012]
【作用】補正回路が１走査期間内における選択期間と非
選択期間とのパルス幅の比率に関して調整自在な信号を
出力し、液晶を駆動する手段が補正回路から出力される
信号に基づいて液晶を駆動する。その際、補正回路は、
補正データ記憶回路に記憶されているｎビットの補正デ
ータに応じて、２ ｎ 段階の範囲で出力信号のパルス幅を
調整するので、液晶材料や使用環境により変わる液晶セ
ルの印加電圧に対する透過率の特性に応じて、パルス幅
比率を制御して印加電圧を補正することにより階調レベ
ルを均等に維持し得る。The correction circuit outputs a signal that can be adjusted with respect to the pulse width ratio between the selection period and the non-selection period within one scanning period, and the means for driving the liquid crystal controls the liquid crystal based on the signal output from the correction circuit. Drive. At that time, the correction circuit
The n-bit correction data stored in the correction data storage circuit
Depending on the chromatography data, the pulse width of the output signal in the range of 2 n stages
Since the adjustment is performed, the gradation level can be maintained uniformly by controlling the pulse width ratio and correcting the applied voltage in accordance with the characteristics of the transmittance to the applied voltage of the liquid crystal cell, which varies depending on the liquid crystal material and the use environment.
【００１３】[0013]
【実施例】本発明の液晶駆動装置の実施例は、１走査期
間内で選択期間と非選択期間のパルス幅比率を変えるこ
とにより階調制御を行うパルス幅変調方式の液晶駆動回
路において、階調信号パルス幅を段階的に調整すること
ができる階調信号補正回路を具備することを特徴とし、
１走査期間を階調数に応じて分割し、異なるパルス幅比
率の信号を生成する基本階調信号生成回路、パルス幅比
率を段階的に補正するためのデ−タを記憶する補正デ−
タ記憶回路、該基本階調信号生成回路の出力信号パルス
幅を該補正デ−タ記憶回路の内容に応じて制御するパル
ス幅制御回路を含む階調信号補正回路を具備することを
特徴とし、電源遮断時においても補正デ−タを保持して
おく記憶手段として、不揮発性のメモリから構成される
補正デ−タ記憶回路を具備することを特徴としている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the liquid crystal driving device according to the present invention is a pulse width modulation type liquid crystal driving circuit which performs gradation control by changing a pulse width ratio between a selection period and a non-selection period within one scanning period. A tone signal correction circuit capable of adjusting a tone signal pulse width stepwise,
A basic gradation signal generation circuit that divides one scanning period according to the number of gradations and generates signals with different pulse width ratios, and correction data that stores data for correcting the pulse width ratio stepwise.
A gradation signal correction circuit including a data storage circuit and a pulse width control circuit for controlling an output signal pulse width of the basic gradation signal generation circuit in accordance with the contents of the correction data storage circuit. As a storage means for holding the correction data even when the power is turned off, a correction data storage circuit composed of a nonvolatile memory is provided.
【００１４】以下本実施例を図面を参照して詳細に説明
する。This embodiment will be described below in detail with reference to the drawings.
【００１５】図１は本発明の液晶駆動装置の実施例の構
成を示す図、図２は本実施例により補正した階調基本信
号を示す図、図３は補正デ−タと読み込みクロックとの
関係を示す図、図４は本実施例により補正した階調レベ
ルと印加電圧との関係を示す図、図５は図８の電気的光
学特性例に対して、階調レベルが均等に得られるように
本実施例により、印加電圧を補正した階調レベルと印加
電圧との関係を示す図である。FIG. 1 is a diagram showing a configuration of an embodiment of a liquid crystal driving device according to the present invention, FIG. 2 is a diagram showing a gradation basic signal corrected by the embodiment, and FIG. 3 is a diagram showing correction data and a read clock. FIG. 4 is a diagram showing a relationship between a gradation level corrected according to the present embodiment and an applied voltage. FIG. 5 is a diagram showing a gradation level obtained uniformly with respect to the example of the electro-optical characteristics in FIG. FIG. 7 is a diagram showing a relationship between a gradation level obtained by correcting an applied voltage and an applied voltage according to the embodiment.
【００１６】図１において、１０は基本クロック、ｎビ
ットの補正デ−タＨＤ0 〜ＨＤn 及び読み込み信号２が
供給され、補正デ−タに基づき補正された基本階調信号
ＨＫ0 〜ＨＫn を出力する階調信号補正回路である。該
階調信号補正回路１０は、基本クロックが入力され、基
本階調信号を生成する基本階調信号生成回路１１、補正
デ−タＨＤ0 〜ＨＤn 及び読み込み信号２が供給され、
読み込み信号２に応答して補正デ−タを記憶する補正デ
−タ記憶回路１２及びこれらの出力が供給され補正デ−
タに基づき補正された基本階調信号ＨＫ0 〜ＨＫn を外
部に出力するパルス幅制御回路１３からなる。１４は外
部からのＮビットの階調デ−タＫＤ0 〜ＫＤN 及び読み
込み信号１が供給される１走査線分の階調デ−タが順次
書き込まれる階調データメモリである。１５は階調デ−
タメモリからの出力及びロード信号が供給され、ロード
信号に応答して一括で１走査線分の階調データ（階調デ
−タメモリからの出力）が転送されるラインデ−タメモ
リである。１６は前記階調信号補正回路１０からの補正
された基本階調信号及びラインデ−タメモリからの出力
が入力され、ラインデ−タメモリからのデータに基づき
基本階調信号のいずれかを選択し出力する一走査線分の
階調信号選択回路である。１７は階調信号選択回路１６
からの出力に基づき一走査線分の液晶駆動出力を出力す
る液晶駆動回路である。階調デ−タメモリ１４、ライン
デ−タメモリ１５、階調信号選択回路１６、および液晶
駆動回路１７が液晶を駆動する手段を構成する。[0016] In FIG. 1, 10 basic clock correction data of n bits - data HD 0 ~HD n and read signal 2 is supplied, the correction de - Basic was based on data corrected gradation signal HK 0 ~HK n Is output. The gradation signal correction circuit 10, the basic clock is input, the basic tone signal generation circuit 11 for generating a reference tone signal, the correction de - data HD 0 ~HD n and read signal 2 is supplied,
A correction data storage circuit 12 for storing correction data in response to the read signal 2;
And a pulse width control circuit 13 for outputting the basic gradation signals HK 0 to HK n corrected based on the data to the outside. 14 the gradation data of N bits from the outside - is the tone data memory data are sequentially written - gradation data of one scanning line of data KD 0 ~KD N and read signal 1 is supplied. 15 is gradation data
This is a line data memory to which an output from a data memory and a load signal are supplied, and grayscale data for one scanning line (output from the grayscale data memory) is transferred collectively in response to the load signal. Reference numeral 16 denotes a circuit to which the corrected basic tone signal from the tone signal correction circuit 10 and the output from the line data memory are input, and selects and outputs one of the basic tone signals based on the data from the line data memory. This is a gradation signal selection circuit for scanning lines. 17 is a gradation signal selection circuit 16
Is a liquid crystal drive circuit that outputs a liquid crystal drive output for one scanning line based on the output from the LCD. The gradation data memory 14, the line data memory 15, the gradation signal selection circuit 16, and the liquid crystal driving circuit 17 constitute a means for driving the liquid crystal.
【００１７】本実施例においては、 Ｎビットの階調デ
−タＫＤ0 〜ＫＤNが読み込み信号１によって階調デ−
タメモリ１４にＮビット単位で順次書き込まれる。１走
査線分の階調デ−タが階調デ−タメモリ１４に揃った時
点でロ−ド信号によりラインデ−タメモリ１５に転送さ
れ、次のロ−ド信号が入力されるまでの間１走査線分の
デ−タが保持される。この階調デ−タが階調信号選択回
路１６に伝えられる。ｎビットの補正デ−タに応じて階
調信号補正回路１０で２n 段階の範囲内（例えばｎ＝８
ビットの場合、階調信号パルス幅を２５６段階の範囲内
で微調整できることになる）で補正された図２の基本階
調信号ＨＫ0 〜ＨＫn が階調デ−タに応じて階調信号選
択回路１６で選択され、液晶駆動回路１７に伝えられ、
輝度信号として出力される。In the present embodiment, the gradation data of N bits - data KD 0 ~KD N gradation de by reading signals 1 -
The data is sequentially written to the data memory 14 in N-bit units. When the gradation data for one scanning line is prepared in the gradation data memory 14, it is transferred to the line data memory 15 by a load signal, and one scan is performed until the next load signal is input. Line segment data is retained. This gradation data is transmitted to the gradation signal selection circuit 16. In accordance with the n-bit correction data, the gradation signal correction circuit 10 has a range of 2 n steps (eg, n = 8).
In the case of bits, the gradation signal pulse width can be finely adjusted within a range of 256 steps.) The basic gradation signals HK 0 to HK n of FIG. 2 corrected in accordance with the gradation data Selected by the selection circuit 16 and transmitted to the liquid crystal drive circuit 17,
It is output as a luminance signal.
【００１８】本実施例に具備された階調信号補正回路１
０では、図３に示すタイミングで基本階調信号ＨＫ0 〜
ＨＫn に対応するｎビットの補正デ−タＨＤ0 〜ＨＤn
が階調レベルごとに設けられた補正デ−タ記憶回路１２
にｎビット単位で順次書き込まれる。即ち、読み込み信
号２の第１クロックで基本階調信号ＨＫ0 に対応した補
正デ−タが、対応する階調レベルの補正デ−タ記憶回路
１２に書き込まれ、読み込み信号２の第２クロックで基
本階調信号ＨＫ1 に対応した補正デ−タが、対応する階
調レベルの補正デ−タ記憶回路１２に書き込まれ、以降
同様に第ｌクロックまでで基本階調信号ＨＫn までに対
応した補正デ−タが階調レベルごとに設けられた補正デ
−タ記憶回路１２にそれぞれｎビット単位で順次書き込
まれる。このようにして書き込まれた補正デ−タはパル
ス幅補正回路１３に伝えられる。A gradation signal correction circuit 1 provided in this embodiment
0, the basic gradation signals HK 0 to HK 0 to
Correction data of n bits corresponding to HK n - data HD 0 ~HD n
Is a correction data storage circuit 12 provided for each gradation level.
Are sequentially written in units of n bits. That is, the correction data corresponding to the basic gradation signal HK 0 at the first clock of the read signal 2 is written to the correction data storage circuit 12 of the corresponding gradation level, and at the second clock of the read signal 2 correction de corresponding to the basic tone signal HK 1 - data is correct data of the corresponding gradation level - written in the data storage circuit 12, corresponding to up to the basic tone signal HK n until the l clock similarly later Correction data is sequentially written in the correction data storage circuit 12 provided for each gradation level in units of n bits. The correction data written in this way is transmitted to the pulse width correction circuit 13.
【００１９】基本階調信号生成回路１１は、各階調レベ
ル毎の基本階調信号を従来例と同様、基本クロックに同
期して動作するカウンタにより生成する。この各階調レ
ベル毎の基本階調信号のパルス幅をパルス幅制御回路１
３で、補正デ−タ記憶回路１２からの補正デ−タに応じ
て、１〜２n まで段階的に制御することにより階調信号
を補正し、階調信号選択回路１６に伝える。The basic gradation signal generation circuit 11 generates a basic gradation signal for each gradation level by a counter which operates in synchronization with the basic clock, as in the conventional example. The pulse width of the basic gradation signal for each gradation level is determined by the pulse width control circuit 1.
In step 3, the gradation signal is corrected by controlling stepwise from 1 to 2 n according to the correction data from the correction data storage circuit 12 and transmitted to the gradation signal selection circuit 16.
【００２０】図４は本実施例に用いることにより各階調
レベル毎の基本階調信号のパルス幅を１（最小補正）に
したときの階調レベルと印加電圧との関係、パルス幅を
２n（最大補正）にしたときの階調レベルと印加電圧と
の関係であり、その範囲内で各階調レベル毎の印加電圧
を補正できることを示している。FIG. 4 shows the relationship between the gradation level and the applied voltage when the pulse width of the basic gradation signal for each gradation level is 1 (minimum correction), and the pulse width is 2 n when used in this embodiment. This is the relationship between the gradation level and the applied voltage when (maximum correction) is set, and shows that the applied voltage for each gradation level can be corrected within that range.
【００２１】図５については、図８に示した環境等によ
り変化した液晶セルの印加電圧に対する透過率の特性
を、本実施例を用いて階調レベルが均等に得られるよう
基本階調信号のパルス幅を制御し、印加電圧を補正した
ことを示したものである。Referring to FIG. 5, the characteristics of the transmittance with respect to the applied voltage of the liquid crystal cell changed by the environment and the like shown in FIG. 8 are set so that the gradation level of the basic gradation signal can be uniformly obtained by using this embodiment. This shows that the pulse width was controlled and the applied voltage was corrected.
【００２２】階調補正回路１０に具備された補正デ−タ
記憶回路１２は、フラッシュメモリ、ＯＴＰ、ＥＥＲＯ
Ｍ等の不揮発性のメモリから構成され、一度記憶した補
正デ−タは電源が遮断されても保持する。The correction data storage circuit 12 provided in the gradation correction circuit 10 includes a flash memory, an OTP, an ERO
The correction data, which is composed of a non-volatile memory such as M, and is stored once, is retained even when the power is turned off.
【００２３】前述のごとく本実施例によれば液晶材料や
使用環境により変わる液晶セルの印加電圧に対する透過
率の特性に応じて、パルス幅比率を制御することにより
印加電圧を補正できる液晶駆動装置を提供することがで
きる。As described above, according to the present embodiment, there is provided a liquid crystal driving device which can correct the applied voltage by controlling the pulse width ratio in accordance with the characteristics of the transmittance to the applied voltage of the liquid crystal cell which varies depending on the liquid crystal material and the use environment. Can be provided.
【００２４】また、本実施例の階調信号補正回路によれ
ば、補正デ−タのビット数に応じた補正デ−タ記憶回路
を備えることにより、各階調レベル毎の基本階調信号を
夫々段階的にしかも微妙に補正することができ、各階調
レベルに最適な印加電圧を供給することができる。Further, according to the gradation signal correction circuit of the present embodiment, the correction data storage circuit corresponding to the number of bits of the correction data is provided, so that the basic gradation signal for each gradation level is provided. The correction can be performed stepwise and finely, and an optimum applied voltage can be supplied to each gradation level.
【００２５】本実施例の補正デ−タ記憶回路によれば、
液晶表示装置の製造時等において、電気的光学特性のば
らつきを階調信号補正により補正する場合、電源遮断時
においてもデ−タを保持することができるので、補正デ
−タを再設定する必要がなくなる。According to the correction data storage circuit of this embodiment,
When correcting variations in electrical and optical characteristics by gradation signal correction at the time of manufacturing a liquid crystal display device or the like, the data can be retained even when the power is turned off. Therefore, it is necessary to reset the correction data. Disappears.
【００２６】[0026]
【発明の効果】補正回路が１走査期間内における選択期
間と非選択期間とのパルス幅の比率に関して調整自在な
信号を出力し、液晶を駆動する手段が補正回路から出力
される信号に基づいて液晶を駆動する。その際、補正回
路は、補正データ記憶回路に記憶されているｎビットの
補正データに応じて、２ ｎ 段階の範囲で出力信号のパル
ス幅を調整するので、液晶材料や使用環境により変わる
液晶セルの印加電圧に対する透過率の特性に応じて、パ
ルス幅比率を制御して印加電圧を補正することにより階
調レベルを均等に維持し得る。The correction circuit outputs a signal that can be adjusted with respect to the pulse width ratio between the selected period and the non-selected period in one scanning period, and the means for driving the liquid crystal is based on the signal output from the correction circuit. Drive the liquid crystal. At that time,
The path is the n-bit data stored in the correction data storage circuit.
Depending on the correction data, the output signal in the range of 2 n stages Pal
Since adjusting the scan width, depending on the characteristics of the transmittance with respect to the applied voltage of the liquid crystal cell vary according to the liquid crystal material and use environment, to maintain uniform gradation level by correcting the applied voltage to control the pulse width ratio obtain.
【図１】本発明の液晶駆動装置の実施例の構成を示す図
である。FIG. 1 is a diagram showing a configuration of an embodiment of a liquid crystal driving device of the present invention.
【図２】本発明の実施例により補正した階調基本信号を
示す図である。FIG. 2 is a diagram showing a gradation basic signal corrected according to an embodiment of the present invention.
【図３】補正デ−タと読み込みクロックとの関係を示す
図である。FIG. 3 is a diagram showing a relationship between correction data and a read clock.
【図４】本発明の実施例により補正した階調レベルと印
加電圧との関係を示す図である。FIG. 4 is a diagram illustrating a relationship between a gradation level corrected according to an embodiment of the present invention and an applied voltage.
【図５】印加電圧を補正した階調レベルと印加電圧との
関係を示す図である。FIG. 5 is a diagram illustrating a relationship between a gradation level obtained by correcting an applied voltage and an applied voltage.
【図６】従来の液晶駆動装置の構成の一例を示す図であ
る。FIG. 6 is a diagram illustrating an example of a configuration of a conventional liquid crystal driving device.
【図７】従来の階調基本信号を示す図である。FIG. 7 is a diagram showing a conventional gradation basic signal.
【図８】液晶セルの電気的光学特性を示す図である。FIG. 8 is a diagram showing electrical and optical characteristics of a liquid crystal cell.
【図９】従来の階調レベルと印加電圧との関係を示す図
である。FIG. 9 is a diagram showing a conventional relationship between a gradation level and an applied voltage.
１０ 階調信号補正回路 １１ 基本階調信号生成回路 １２ 補正デ−タ記憶回路 １３ パルス幅制御回路 １４ 階調デ−タメモリ １５ ラインデ−タメモリ １６ 階調信号選択回路 １７ 液晶駆動回路 Reference Signs List 10 gradation signal correction circuit 11 basic gradation signal generation circuit 12 correction data storage circuit 13 pulse width control circuit 14 gradation data memory 15 line data memory 16 gradation signal selection circuit 17 liquid crystal drive circuit
Claims (2)
期間とのパルス幅の比率に関して調整自在な信号を出力
する補正回路と、前記補正回路から出力される信号に基
づいて液晶を駆動する手段とを具備する液晶駆動装置で
あって、前記補正回路は、１走査期間を階調数に応じて
分割し、異なったパルス幅比率の信号を生成する基本階
調信号生成回路と、パルス幅比率を階段的に補正するｎ
ビットの補正データを記憶する補正データ記憶回路と、
前記補正データ記憶回路に記憶されているｎビットの補
正データに応じて、２ ｎ 段階の範囲で、前記基本階調信
号生成回路の出力信号のパルス幅を調整するパルス幅制
御回路とを含むすることを特徴とする液晶駆動装置。 1. A correction circuit that outputs a signal that can be adjusted with respect to a pulse width ratio between a selection period and a non-selection period within one scanning period, and a unit that drives a liquid crystal based on a signal output from the correction circuit. in the LCD driving apparatus including bets
The correction circuit sets one scanning period according to the number of gradations.
Base floor to split and generate signals with different pulse width ratios
Tone signal generation circuit and n for stepwise correcting the pulse width ratio
A correction data storage circuit for storing bit correction data,
The complement of the n bits stored in the correction data storage circuit
According to the positive data, the basic gradation signal is provided in a range of 2n steps.
Pulse width system that adjusts the pulse width of the output signal of the signal generation circuit
A liquid crystal drive device comprising a control circuit.
モリを具備することを特徴とする請求項１に記載の液晶
駆動装置。2. The method according to claim 1, wherein the correction data storage circuit includes a nonvolatile memory.
The liquid crystal driving device according to claim 1, characterized in that it comprises a memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28328893A JP2988815B2 (en) | 1993-11-12 | 1993-11-12 | Liquid crystal drive |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28328893A JP2988815B2 (en) | 1993-11-12 | 1993-11-12 | Liquid crystal drive |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07134282A JPH07134282A (en) | 1995-05-23 |
| JP2988815B2 true JP2988815B2 (en) | 1999-12-13 |
Family
ID=17663510
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28328893A Expired - Fee Related JP2988815B2 (en) | 1993-11-12 | 1993-11-12 | Liquid crystal drive |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2988815B2 (en) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3672586B2 (en) | 1994-03-24 | 2005-07-20 | 株式会社半導体エネルギー研究所 | Correction system and operation method thereof |
| US5767823A (en) * | 1995-10-05 | 1998-06-16 | Micron Display, Inc. | Method and apparatus for gray scale modulation of a matrix display |
| JP3281298B2 (en) | 1997-09-22 | 2002-05-13 | シャープ株式会社 | Driving device for liquid crystal display element |
| JP2002091379A (en) * | 2000-09-20 | 2002-03-27 | Tohoku Pioneer Corp | Driving method of capacitive light emitting device display and control device therefor |
| JP3520863B2 (en) | 2000-10-04 | 2004-04-19 | セイコーエプソン株式会社 | Image signal correction circuit, correction method thereof, liquid crystal display device, and electronic device |
| KR100430087B1 (en) * | 2001-09-10 | 2004-05-03 | 엘지전자 주식회사 | Apparatus of driving flat display panel and driving method thereof |
| KR100486909B1 (en) * | 2002-04-29 | 2005-05-03 | 엘지전자 주식회사 | Driving method and apparatus of electro-luminescence display panel |
| KR100451899B1 (en) * | 2002-06-12 | 2004-10-08 | 주식회사 엘리아테크 | Apparatus of current boosting for driving Organic Electro Luminescent Display Device |
| KR20040021753A (en) * | 2002-09-04 | 2004-03-11 | 권오경 | Organic electro-luminescent DISPLAY apparatus and driving method thereof |
| JP2006195306A (en) * | 2005-01-17 | 2006-07-27 | Sony Corp | LIGHT EMITTING DEVICE DRIVE METHOD, LIGHT EMITTING DEVICE DRIVE DEVICE, AND DISPLAY DEVICE |
| JP4892864B2 (en) * | 2005-05-10 | 2012-03-07 | セイコーエプソン株式会社 | Display controller, display system, and display control method |
| JP5353929B2 (en) * | 2011-03-24 | 2013-11-27 | セイコーエプソン株式会社 | Display controller, display system, and display control method |
| US20140078196A1 (en) * | 2011-05-31 | 2014-03-20 | Sharp Kabushiki Kaisha | Drive circuit and drive method for display device |
-
1993
- 1993-11-12 JP JP28328893A patent/JP2988815B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07134282A (en) | 1995-05-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5327824B2 (en) | Display with multiple pixels to achieve modulation between saturation voltage and threshold voltage | |
| JP2010286846A (en) | Method for achieving modulation between saturation and threshold voltages, and display with multiplexed pixels | |
| JP4295567B2 (en) | Display response speed increasing device | |
| JP4621649B2 (en) | Display device and driving method thereof | |
| US6762739B2 (en) | System and method for reducing the intensity output rise time in a liquid crystal display | |
| US7847771B2 (en) | Display device capable of adjusting divided data in one frame | |
| JP2988815B2 (en) | Liquid crystal drive | |
| KR100915234B1 (en) | Driving apparatus of liquid crystal display for varying limits selecting gray voltages and method thereof | |
| US20040196304A1 (en) | Mixed mode grayscale method for display system | |
| US6801177B2 (en) | Liquid crystal display device | |
| US7173591B2 (en) | Liquid crystal driving device | |
| US6072452A (en) | System and method for using forced states to improve gray scale performance of a display | |
| KR20080042433A (en) | Display device and driving device thereof | |
| JP2005049418A (en) | Liquid crystal display device and optimum gradation voltage setting device thereof | |
| JP4902116B2 (en) | Liquid crystal display | |
| JP5098619B2 (en) | Display driving device and display device including the same | |
| TWI427599B (en) | Video system including a liquid crystal display with improved addressing method | |
| US20090040214A1 (en) | Signal processor, liquid crystal display device including the same, and method of driving liquid crystal display device | |
| JPH10341358A (en) | Image quality control system | |
| JP2009518673A (en) | Sequential color matrix liquid crystal display | |
| KR101002938B1 (en) | LCD and its driving method | |
| JPH04358197A (en) | Gradation driving circuit of liquid crystal display | |
| JPH09179530A (en) | Drive circuit for liquid crystal panel and liquid crystal display device using the drive circuit | |
| JP2008250222A (en) | Liquid crystal drive device and liquid crystal display device | |
| JPH05216436A (en) | Liquid crystal display |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20071008 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081008 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 9 Free format text: PAYMENT UNTIL: 20081008 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 10 Free format text: PAYMENT UNTIL: 20091008 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 10 Free format text: PAYMENT UNTIL: 20091008 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 11 Free format text: PAYMENT UNTIL: 20101008 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 12 Free format text: PAYMENT UNTIL: 20111008 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121008 Year of fee payment: 13 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131008 Year of fee payment: 14 |
|
| LAPS | Cancellation because of no payment of annual fees |