JP2995231B2 - Method for manufacturing analog polysilicon capacitor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to an analog (ana)
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a polycapacitor (poly) for storing information of various states.
capacitor, that is, polysilicon capacity
And a method for manufacturing the same.

[0002]

2. Description of the Related Art Generally, an analog semiconductor device has only two pieces of information, a low level state and a high level state.
Unlike a so-called binary-state digital semiconductor device, it has a circuit configuration in which a capacitor or a resistor is added to each required electrode in order to store information in various states. However, when the change in the voltage applied to the analog semiconductor element is large, the capacitance of the capacitor and the resistance of the resistor must also change greatly. Therefore, a metal oxide semiconductor field effect transistor (MOSFE)
In an analog semiconductor device in which T) and a polysilicon capacitor are combined, a capacitor oxide film having a uniform thickness is required.

[0003] FIG. 2A~-2D is, Anna according to the prior art
In order to explain a method of manufacturing a log polysilicon capacitor , the manufacturing steps are sequentially shown. FIG.
In A, an element isolation film 2 is formed in a predetermined region of the semiconductor substrate 1 by an oxidation step, and then a sacrificial oxide film 3 is formed in an active region defined by the element isolation film 2. The sacrificial oxide film 3 prevents the semiconductor substrate 1 from being damaged in the subsequent steps. Then, the capacitor under the whole of the upper
A silicon film 7 for a part electrode and a capacitor oxide film 8 are formed respectively, and a first photoresist pattern 9 is formed on the capacitor oxide film 8 on the element isolation film 2 to form a capacitor lower electrode. You.

In FIG. 2B, the capacitor oxide film 8 and the capacitor lower electrode silicon film 6 are patterned by an etching process, and then the first photoresist pattern 9 is removed. As a result, the capacitor lower electrode 7 'is formed on the element isolation film 2, a capacitor
A capacitor oxide film 8 is formed on lower electrode 7A. Next, the sacrificial oxide film 3 is removed. Thereafter, a gate oxide film 4 is formed on the active region by an oxidation process. At this time, a thin oxide film is formed on a sidewall of the capacitor lower electrode adjacent to the active region.

[0005] In Figure 2C, the entire upper gate electrode and the capacitor upper electrode conductive layer 10 is deposited, the gate electrode 5 and upper capacitor over conductive layer 10
A second photoresist pattern 11 for forming an electrode 12 is formed.

In FIG. 2D, a gate electrode is formed on the active region of the device by an etching process, and a capacitor upper electrode 12 is formed on capacitor oxide film 8. After that, the second photoresist pattern 11 is removed. In the above-mentioned etching process, adjacent to the active region
The oxide film on the side wall of the capacitor lower electrode is also removed.
Next, impurity ions are implanted into both substrates of the gate electrode 5, and the implanted impurities are driven in a heat treatment step, thereby forming the source / drain regions 6.

However, according to the mentioned polysilicon calibration <br/> Pashita manufacturing method, during the oxidation process for forming the gate oxide film 4 while the capacitor oxide film 8 was exposed <br/> capacitor oxide film 8 is likely to damage, thereby, characteristics of the polysilicon capacitor is reduced, the productivity of the analog type semiconductor device is reduced.

[0008]

An object of the present invention is to provide a, during the process for forming the gate oxide film, polysilicon analog which can solve the problems capacitor oxide film is damaged
Another object of the present invention is to provide a method for manufacturing a capacitor .

Another object of the present invention is to form a capacitor oxide film and a gate oxide film at the same time, thereby simplifying a polysilicon capacitor manufacturing process and making the thickness of the capacitor oxide film uniform. Te, analog polysilicon which can improve the characteristics of the polysilicon <br/> capacitor
An object of the present invention is to provide a method for manufacturing a capacitor .

[0010]

Therefore, in the present invention,
First, providing a semiconductor substrate having a polysilicon pattern doped with an impurity for a capacitor lower electrode on a field oxide film for element isolation, thermally oxidizing the semiconductor substrate, and forming a capacitor upper electrode and a gate. A step of depositing a conductive layer for use on a thermally oxidized semiconductor substrate, and a step of patterning the deposited conductive layer to form a capacitor upper electrode pattern and a gate pattern in each selected region. It is characterized by including.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a method for manufacturing an analog polysilicon capacitor according to the present invention will be described with reference to FIG.
This will be described in detail with reference to FIGS.

Referring to FIG. 1A, an isolation film 22 is formed on a predetermined portion of a semiconductor substrate 21 by an oxidizing process in order to separate semiconductor devices.
2, a silicon film 26 for a capacitor lower electrode is formed. This polysilicon film 26 has boron as a P-type impurity and phosphorus (Phosphoru) as an N-type impurity.
s) or selected from one of arsenic (As),
Doped at a concentration of 5 × 10 ²⁰ atoms / cm ³ or more
That is a P-type or N-type polysilicon film. Further, because of the polysilicon film 26 for the capacitor lower electrode ,
Any of silicon, germanium, and argon having a large atomic weight is contained in polysilicon at 5 × 10 ¹⁴ atoms / cm 2.
Additional ion implantation can be performed under the condition of ^{3 to} 5 × 10 ¹⁶ ions / cm ² .

In FIG. 1B, in order to form gate oxide film 23 and capacitor oxide film 27, 750-8
At 50 ° C., a wet oxidation step is performed. As a result, calibration
A capacitor oxide film 27 is formed on the lower capacitor electrode 26 , and a gate oxide film 23 is formed in an active region of the element defined by the element isolation film 22. Normally, the oxidation rate is high at a high impurity concentration, so that a thicker oxide film is formed at a high impurity concentration. The capacitor lower electrode 26, has a higher impurity concentration than the semiconductor substrate 21, which is also greater than 2.5 times the oxidation of the semiconductor substrate 21. On the other hand, the oxidation rate of the capacitor oxide film 27 is
There are some differences depending on the amount of impurity implantation and oxidation conditions,
5 × 10 ²⁰ atoms / cm ^{3 on the} capacitor lower electrode 26
Implanted with arsenic impurity having a concentration of
When wet oxidation is performed at 850 ° C., the oxidation rate of the semiconductor substrate 1 can be increased up to 10 times.

[0014] Then, the gate electrode and the calibration of the predetermined thickness
Pashita conductive layer 28 for forming the upper electrode is deposited on the entire <br/> portion, the photoresist pattern 29 is formed on the conductive layer 28. Here, the gate oxide film 2
Immediately after forming the capacitor oxide film 27 and the capacitor oxide film 27,
Since the gate electrode and the conductive layer 28 for the capacitor upper electrode are formed thereon, the exposure time of the capacitor oxide film 27 is reduced. The thickness of the capacitor oxide film 27 more this is kept constant, whereby it is possible to improve the characteristics of the capacitor oxide film 27. For the conductive layer 28 described above, polysilicon, silicide, or metal is used.

In FIG. 1C, the gate electrode 24 and
To form the capacitor top electrode 30, the conductive layer 28
After patterning, the gate electrode 24 is etched on the semiconductor substrate 21 using the photoresist pattern 29.
And the upper part of the capacitor on the capacitor oxide film 27.
An electrode 30 is formed. After that, the photoresist pattern 29 is removed. Next, impurities are ion-implanted into the exposed portions of the semiconductor substrate 21. The impurity ions are driven in the heat treatment step, and the source /
A drain junction region 25 is formed.

[0016]

As described above, according to the present invention, by simultaneously forming the capacitor oxide film and the gate oxide film, the manufacturing process of the polysilicon capacitor can be simplified. Furthermore, since the capacitor conductive layer is formed immediately after the capacitor oxide film is formed, the characteristics of the capacitor can be improved.

[Brief description of the drawings]

FIGS. 1A to 1C are explanatory diagrams sequentially showing a manufacturing process of an analog polysilicon capacitor for describing an embodiment of the present invention.

FIGS. 2A to 2D are explanatory views sequentially showing the steps of manufacturing a conventional analog polysilicon capacitor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 21 Semiconductor substrate 22 Element isolation film 23 Gate oxide film 24 Gate electrode 25 Source / drain junction region 26 Capacitor lower electrode 27 Capacitor oxide film 28 Conductive layer 30 Capacitor upper electrode

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 27/04 H01L 21/822 H01L 21/8242 H01L 27/108

Claims (13)

(57) [Claims] A step of thermally oxidizing the semiconductor substrate; a 1. A polysilicon pattern doped with impurities for the capacitor lower electrode, process and to provide a semiconductor substrate having the isolation field oxide film on the capacitor upper electrode Depositing conductive layers for the gate and the gate on the thermally oxidized semiconductor substrate; patterning the deposited conductive layer to form an upper capacitor pattern and a gate pattern in each selected region; A method for manufacturing an analog polysilicon capacitor comprising: 2. An analog polysilicon capacitor according to claim 1, wherein said impurity is N-type.
The method of production. 3. An analog poly-poly according to claim 2, wherein said N-type impurity is selected from phosphorus and arsenic.
A method for manufacturing a silicon capacitor . Wherein in the polysilicon doped with the impurity, A according to claim 2, wherein the doping concentration of the N-type impurity is 5 × 10 ²⁰ atoms / cm ³
A method for manufacturing a polysilicon capacitor for analog . 5. The analog polysilicon capacitor according to claim 1, wherein said impurities are P-type.
The method of production. In 6. the polysilicon doped with the impurity, A according to claim 5, wherein the doping concentration of the P-type impurity is 5 × 10 ²⁰ atoms / cm ³
A method for manufacturing a polysilicon capacitor for analog . 7. Polysilicon for the capacitor lower electrode
, The group consisting of silicon, germanium and argon
The polysilicon for an analog according to claim 5, wherein one selected from the group consisting of: is additionally ion-implanted.
Manufacturing method of capacitor . 8. The ion implantation concentration of the P-type impurity is 5
Method for producing analog polysilicon capacitor according to claim 5, characterized in that a × 10 ¹⁶ ions / cm ^2. 9. The polysilico for analog according to claim 1, wherein the thermal oxidation step is a wet oxidation step.
Manufacturing method of capacitor . 10. The wet oxidation step is performed at 750-850 ° C.
A according to claim 9, which comprises carrying out at a temperature
A method for manufacturing a polysilicon capacitor for analog . 11. An upper part of the gate electrode and the capacitor.
2. The analog polysilicon capacitor according to claim 1, further comprising a step of forming source / drain junction regions on both sides of the gate electrode after the step of forming the electrode.
Manufacturing method of pasita . 12. The analog polysilicon capacitor according to claim 1, wherein said conductive layer is selected from the group consisting of polysilicon and polycide.
Method of manufacturing data. 13. The analog polysilicon of claim 1, wherein said conductive layer is polysilicon.
A method for manufacturing a capacitor .