JP2995254B2 - Semiconductor device and method of forming the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a DR having a stacked memory cell structure.
The present invention relates to a semiconductor device for forming a capacitor such as an AM or an SRAM and a method for forming the same.

<Prior Art> A memory cell pattern of a DRAM stack type will be described with reference to a layout pattern diagram shown in FIG.

As shown in the figure, the memory cell pattern of the DRAM stack format is composed of an underlayer 502 formed on a semiconductor substrate 501 and an underlayer.
And a capacitor 503 provided on the 502.

The base layer 502 is composed of a plurality of element regions 505 provided on the semiconductor substrate 501 and word lines 506 provided two at a time substantially orthogonal to each of the element regions 505.

The capacitor 503 stores a memory charge,
Storage electrodes 511 provided on both sides of the element region 505
And an insulating film (not shown) provided so as to cover at least each storage electrode 511, and a plate electrode (not shown) formed on the insulating film.

On the element region 505, a bit contact formation region 504 is provided between two word lines 506 straddling the element region 505. Further, cell contacts 507 connected to the storage electrodes 511 are provided on both sides of the element region 505.
Is provided.

Next, a method of forming the capacitor 503 having the memory cell pattern will be described.

To form the capacitor 503, first, a storage electrode material is formed on the entire surface of the underlayer 502. Next, the storage electrode material is etched by a photolithography technique and an etching technique. Then, a storage electrode 511 is formed.

After that, an insulating film material is formed on the base layer 502 including the storage electrode 511. Further, a plate electrode material is formed on the insulating film material. Next, the plate electrode material and the insulating film material are removed by etching using a photolithography technique and an etching technique. Then, an insulating film and a plate electrode are formed on the storage electrode 511.

In the above memory cell pattern, the storage electrode 511 is formed as close as possible to increase the degree of integration.
The area of the storage electrode 511 is formed as large as possible in order to prevent a soft error or to improve the operation sensitivity of a sense amplifier circuit corresponding to a signal from a bit line.

<Problems to be Solved by the Invention> However, in the conventional memory cell pattern, the insulating film and the plate electrode are designed in consideration of the mask alignment margin with respect to the bit contact formation region, and at the same time, the storage electrode is formed with the bit contact. The design is made in consideration of the mask alignment allowance for the region. Therefore, the area of the storage electrode is reduced by a margin for mask alignment for aligning the storage electrode with the bit contact region.

When the storage electrodes are formed close to each other in order to increase the degree of integration, when forming a resist pattern for forming the storage electrodes, the bottom of the step where the word line is close (the fifth step described above). Residual resist is generated in the hatched area in the figure). When etching is performed in this state, adjacent storage electrodes are short-circuited. To eliminate this short circuit, over-exposure is performed at the time of forming the resist pattern. Alternatively, over-etching is performed at the time of etching.

In this case, as shown in FIG. 6, the size of the formed storage electrode 511 is smaller than the size of the photomask pattern 512.

As described above, in the conventional memory cell pattern, since the area of the storage electrode is reduced, the memory charge stored in the insulating film on the storage electrode is reduced, and a soft error occurs. Therefore, the reliability is greatly reduced.

The present invention has been made in order to solve the above-described problems, and has as its object to provide a semiconductor device having excellent reliability and a method for forming the same.

<Means for Solving the Problems> The present invention has been made to achieve the above object, and a method for forming a semiconductor element extends in a predetermined direction while widening or narrowing a gap between the semiconductor elements. Forming a capacitor on a semiconductor substrate having first and second word lines and two cell contacts facing each other with the first and second word lines interposed therebetween. Forming a storage electrode on the two cell contacts and on the first and second word lines, forming a capacitor insulating film, a plate electrode, and an etching mask on the storage electrode sequentially; Up,
And the first and second portions where the distance between each other is widened
Forming an opening in the etching mask between the word lines, and etching the plate electrode, the capacitor insulating film, and the storage electrode sequentially using the etching mask with the opening formed as a mask,
Dividing the storage electrode between the first and second word lines at locations where the mutual interval is widened.

A semiconductor device includes a semiconductor substrate having an element formation region,
A first element extending in a predetermined direction on a semiconductor substrate including the element forming region while the distance between the first element and the second element is increased or decreased;
And a second word line formed on the semiconductor substrate including the element formation region, the first word line and the second word line, and sandwiching the first and second word lines therebetween. An intermediate insulating film having two cell contacts on an element formation region, storage electrodes formed on the intermediate insulating film including the two cell contacts, and a capacitor insulating film formed on the storage electrode, And a plate electrode formed on the capacitor insulating film, and a bit contact formation region is arranged between the first and second word lines at locations where the distance between each other is widened. The side surfaces of the storage electrode, the capacitor insulating film, and the plate electrode facing each other are configured to form a continuous surface.

<Operation> In the semiconductor device having the above structure and the method of forming the same, the first and second word lines are etched by etching the plate electrode, the capacitor insulating film, and the storage electrode using a one-layer etching mask provided with an opening. The side surfaces of the storage electrode, the side surfaces of the capacitor insulating film, and the side surfaces of the plate electrode, which face the region corresponding to the place where the distance between them is wide, for example, the bit contact formation region, are arranged so as to form continuous surfaces Is done.

Further, when the storage electrode is formed separately in the bit contact formation region where the distance between the first and second word lines is large, the portion where the word line between the storage electrodes is close when the window pattern (opening) is formed. Since the area of the window pattern (the portion indicated by 127 in FIG. 2 described later) is wider than the bottom of the step (the hatched portion in FIG. 5) of FIG. In addition, the overexposure amount and the overetch amount are reduced.

Therefore, the photolithographic mask 512 shown in FIG.
In the present invention, the storage electrode 111 is formed by the photolitho mask 128 and the window pattern mask 129, as shown in FIG.
The storage electrode can be formed large by the area of 130.

As a result, a sufficient area of the storage electrode is ensured.

<Example> First, the structure of an example according to the semiconductor device of the present invention will be described with reference to the plan view shown in FIG. 1A and the AA shown in FIG.
The description will be given with reference to the line cross-sectional view.

As shown in the figure, a memory cell pattern 100 is formed by a base layer 102 and a capacitor 103 provided on a semiconductor substrate (not shown).
And

On the underlayer 102, a bit contact formation region 104
Is provided.

The capacitor 103 includes a storage electrode 111 formed on the base layer 102, a capacitor insulating film 112 formed on at least the storage electrode 111, and a plate electrode 113 formed on the capacitor insulating film 112.

Furthermore, the side surface 111a of the storage electrode 111, the side surface 112a of the capacitor insulating film 112, and the side surface of the plate electrode 113, facing the bit contact formation region 104
Each of 113a is arranged to form a continuous surface. Moreover, each of the side surfaces 111a, 112a, 113a is formed substantially perpendicular to the underlayer 102.

The storage electrode 111 is a polycrystalline silicon film and is formed in a substantially rectangular island pattern. The capacitor insulating film 112 is formed of a material having a high relative dielectric constant such as silicon oxide or silicon nitride. The plate electrode 113 is formed of a polycrystalline silicon film.

Next, a method of forming the capacitor 103 will be described with reference to FIGS.

As shown in FIG. 2, a storage electrode material 121 is formed on the entire surface of a base layer (not shown).
An etching mask pattern 124 is formed in the shape of 21 by photolithography. The etching mask pattern 124 has a shape in which storage electrodes described later are two-connected in the longitudinal direction, and is formed of a resist.

Subsequently, the exposed storage electrode material 121 is etched away by an etching technique. Further, the etching mask pattern 124 is removed. Then, a storage electrode material pattern 125 shown in FIG. 2 is obtained.

Next, as shown in FIG.
A capacitor insulating film material (not shown) is formed on the entire surface on the 125 side. Further, a plate electrode material 123 (a region marked with x in the figure) is formed on the capacitor insulating film material. Subsequently, an etching mask 126 (shaded area in the figure) formed of a resist is provided on the plate electrode material 123. This etching mask 126 is formed by photolithography technology.
A window pattern 127 is provided. The window pattern 127 is the storage electrode material pattern 1 at the center of the storage electrode material pattern 125.
It is formed larger than the width of 25.

Subsequently, the plate electrode material 123 exposed from the window pattern 127 is removed by etching using an etching technique. Further, the capacitor insulating film material exposed by the etching and the storage electrode material pattern 125 are removed by etching. After that, the etching mask 126 is removed. Then, as shown in FIG.
A plate electrode 113 and a capacitor insulating film (not shown) having the same shape as the plate electrode 113 are obtained.

Moreover, as shown in FIG. 1 (b), each of the side surfaces (111a), (112a), and (113a) is arranged so as to form a continuous surface.

In the above-described forming method, the shape of the window pattern 127 was substantially square. However, as shown in FIG. 3A, the window pattern 127 may be formed in an octagonal shape, and FIG.
As shown in FIG. 2, the window pattern 127 may be formed by rotating the square shape shown in FIG. 2 by 45 °.

In these cases, the area of the storage electrode 111 can be further increased.

Therefore, the amount of memory charge that can be stored in the capacitor insulating film from the storage electrode 111 increases.

Next, a method of forming a semiconductor device having a memory cell structure of a stack type using the above-described forming method is shown in FIG.
This will be described with reference to layout pattern diagrams shown in FIGS.

As shown in FIG. 4 (i), a semiconductor substrate (not shown)
On the top, similar to the prior art described above, a plurality of element regions
105, a first and second word lines 106, 106 and an underlying layer 10 formed by an intermediate insulating film (not shown) covering them.
Two are provided. Further, a bit contact formation region is provided in a portion of each element region 105 where the distance between the first and second word lines 106, 106 is wide. Also, the element region 10
Cell contacts 107 are provided on the intermediate insulating film on both sides of 5.

First, a storage electrode material 121 is formed on the entire surface of the underlayer 102 (intermediate insulating film). Then, an etching mask pattern 124 (shaded area in the figure) is formed in the same manner as described with reference to FIG. The etching mask pattern 124 is formed so as to cover the element region 105.

Subsequently, the exposed storage electrode material 121 is removed by etching. Further, the etching mask pattern 124 is removed. And the storage electrode material pattern shown in FIG. 4 (ii)
Get 125.

Next, in the same manner as described with reference to FIG. 2, a capacitor insulating film material (not shown) and a plate electrode material 123 are formed on the entire surface on the storage electrode material pattern 125 side as shown in FIG. (The area marked with x in the figure) and the etching mask 126
(Shaded areas in the figure) are formed in order. Then, the storage electrode material pattern 125 including the bit contact formation region 104
A window pattern 127 is provided on an etching mask 126 at the center of the pattern. This window pattern 127 corresponds to the storage electrode material pattern 125.
Is formed to be larger than the width.

Since the window pattern 127 is formed in a portion where the distance between the first and second word lines 106 and 106 is wide as described above, when the window pattern 127 is formed, a step in a portion where the word lines between the storage electrodes are close to each other is formed. The region of the window pattern 127 may be wider than the bottom (the hatched portion in FIG. 5), and is not affected by the steps due to the first and second word lines 106, 106. Therefore, no pattern remains in the window pattern 127.

Subsequently, the plate electrode material 123 exposed from the window pattern 127 is etched. Further, using the window pattern 127, the capacitor insulating film material (not shown) and the storage electrode material pattern 125 are removed by etching. Then,
The etching mask 126 is removed. Then, FIG. 4 (i
v) As shown in FIG.
And a capacitor insulating film (not shown) having the same shape as the plate electrode 113 is obtained.

Therefore, the side surface of the storage electrode 111 facing the bit contact formation region 104, the side surface of the capacitor insulating film, and the side surface of the plate electrode 113 are arranged so as to form the same plane.

<Effect of the Invention> As described above, according to the present invention, each of the side surface of the storage electrode, the side surface of the capacitor insulating film, and the side surface of the plate electrode facing the bit contact formation region is a continuous same surface. Are arranged to form
Therefore, the area of the storage electrode can be designed to be large.

Further, since the storage electrode is formed by separating the storage electrode material pattern in the bit contact formation region where the distance between the first and second word lines is large, the bottom of the step where the word line between the storage electrodes is close to each other is formed. The area of the window pattern (for example, a portion indicated by 127 in FIG. 2) may be wider than the area of the window pattern (for example, the hatched portion in FIG. 5), and the window pattern is not affected by the step due to the word line. No pattern residue occurs during formation. Therefore, the amount of over-exposure or over-etching is significantly reduced, so that the size of the storage electrode is reduced.

Therefore, the area of the storage electrode can be ensured to be sufficiently large, so that the memory charge can be sufficiently stored in the capacitor insulating film. Therefore, the occurrence of a soft error can be prevented, and the reliability can be significantly improved.

[Brief description of the drawings]

1 (a) is a plan view of the embodiment, FIG. 1 (b) is a longitudinal sectional view taken along line AA in FIG. 1, FIG. 2 and FIG. 3 (A) and 3 (B) are explanatory diagrams of a window pattern, FIGS. 4 (i) to (iv) are layout pattern diagrams of a forming method of an embodiment, FIG. 5 is a conventional layout pattern diagram, FIG. 6 is an explanatory diagram of the problem, and FIG. 7 is an explanatory diagram of the operation. 100: Memory cell pattern, 102: Underlayer, 103: Capacitor, 104: Bit contact formation region, 111: Storage electrode, 111a Side surface (of storage electrode), 112: Capacitor insulating film, 112a …… side surface (of the capacitor insulating film), 113 …… plate electrode, 113a …… side surface (of the plate electrode), 121 …… storage electrode material, 123 …… plate electrode material, 124 …… etching mask pattern, 125 …… Storage electrode material pattern, 126 ... etching mask, 127 ... window pattern.

Claims (2)

(57) [Claims] 1. A first and second word line extending in a predetermined direction while increasing or decreasing the interval between two first and second word lines, and two opposed word lines interposing the first and second word lines therebetween. A method for forming a semiconductor element, wherein a capacitor is formed on a semiconductor substrate having a cell contact, the method comprising: forming a storage electrode on the two cell contacts and on the first and second word lines; Forming a capacitor insulating film, a plate electrode, and an etching mask sequentially on the substrate; and forming an opening in the etching mask between the first and second word lines on the plate electrode and at a location where the distance between each other is widened. And etching the plate electrode, the capacitor insulating film, and the storage electrode sequentially using the etching mask in which the opening is formed as a mask. Dividing the storage electrode between the first and second word lines at a location where the distance between the first and second word lines is widened. 2. A semiconductor substrate having an element forming region, and a first substrate extending in a predetermined direction on the semiconductor substrate including the element forming region while increasing or decreasing the distance between the semiconductor substrate and the semiconductor substrate.
And a second word line, formed on the semiconductor substrate including the element formation region, the first word line and the second word line, and sandwiching the first and second word lines therebetween. An intermediate insulating film having two cell contacts on the element formation region, storage electrodes respectively formed on the intermediate insulating film including the two cell contacts, and a capacitor insulating film formed on the storage electrode; And a plate electrode formed on the capacitor insulating film, wherein a bit contact formation region is disposed between the first and second word lines at locations where the distance therebetween is widened. A semiconductor element, wherein the side surfaces of the storage electrode, the capacitor insulating film, and the plate electrode that face each other form a continuous surface.