JP3142343B2 - Mask pattern forming method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a mask pattern such as a diffusion mask necessary for manufacturing a light emitting portion of an LED device, and more particularly to a method for preventing photolithographic defects.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional method of forming a mask pattern with reference to a manufacturing process drawing of a light emitting portion of a light emitting diode (LED) element. Here, as one example, a P-type impurity is diffused into an N-type wafer, which is one of the semiconductor substrates, and L-type impurities are diffused.
A process for manufacturing the ED element will be described.

First, as shown in FIG. 3A, a diffusion mask 2 is formed on an N-type wafer 1. The film 2 plays a role of blocking impurities in a diffusion step described later, and is generally a nitride film (SiN) or alumina (Al ₂ O).
₃ ) is used. Next, as shown in FIG. 3B, a resist 4 is coated on the diffusion mask 2 by a spinner or the like. In the case of a negative resist, a mask 5 for photolithography (hereinafter abbreviated as "photolitho"), in which a portion to be etched is shaded, is used, as shown in FIG. When it is developed, FIG.
As in 1), the resist 4 remains only in the portion where light is applied, and the diffusion mask 2 in the portion to be etched is exposed. When this is etched, a portion without the resist 4 is etched as shown in FIG. 3 (e1), and a mask pattern of the diffusion mask 2 is formed. Next, the resist is removed (removed) to diffuse a P-type impurity, and a P layer 9 is formed in the etched portion as shown in FIG. Next, FIG.
As in 1), the electrode 10 is formed on the P layer 9 so as to be in contact with a part of the P layer 9. By passing a current from the electrode 10, a light emitting portion of an LED element in which a PN junction between the N-type wafer 1 and the P layer 9 plays a role of light emission is completed.

The steps shown in FIGS. 3 (d2) to (g2) show a case where there is a defect in a photolithography (hereinafter referred to as photolitho) step, which will be described in the next section.

[0005]

However, according to the above-described method, when there is a scratch, dirt, or dirt on the photolithographic mask, a shadow is formed at a place other than a place to be etched. In some cases, portions (photolithographic defects) 8 that do not remain may be formed (FIG. 3D
2)). In this case, the photolitho defect portion 8 is etched in the next etching step, and a mask pattern having a shape different from the original mask pattern is formed (FIG. 3 (e2)). As a result, for example, in the case of the above-mentioned LED element, impurities are diffused in the diffusion step, and the P layer 9
(FIG. 3 (f2)). Then, in the next electrode attaching step, when the electrode 9 is attached thereon, when an electric current is applied, an electric current also flows through the photolitho defect 8 (FIG. 3).
(G2)) There is a problem that a part that should originally emit light becomes dark, and another part emits light.

According to the present invention, the above-described photolithographic defect causes a defect in the shape of the mask pattern, a portion to be illuminated originally becomes dark, another portion shines, or an impurity is diffused into an incorrect region. Resist coating, mask alignment, exposure, development, etching, etc. are performed twice or more each to eliminate the problem of improper short circuiting. Photolitho defects do not adversely affect, and mask misalignment also adversely affects. It is an object of the present invention to provide a method of forming a mask pattern that does not affect the pattern.

[0007]

According to the present invention, there is provided a method for forming a mask pattern according to the above-mentioned object, in which, as a first embodiment, two or more mask layers are provided. As a general rule, the mask layer is
Steps such as mask alignment, exposure, development, and etching are performed twice or more.

[0008]

According to the present invention, as described above, even if the upper mask layer or the first resist is etched due to photolitho defects at the first development, the portion is not removed at the second development. Since it is covered with the second resist,
At the time of the second etching, the mask layer is not etched. Also, even if photolitho defects are formed during the second development, the mask layer is not etched. Therefore, neither photolithographic defect has an effect on the shape of the mask pattern.

[0009]

1 and 2 show a manufacturing process of a first embodiment of the present invention, which will be described below. Note that the same reference numerals are given to portions having the same properties as those in FIG. 3 for describing the prior art (the same applies to the second and third embodiments below).

In this embodiment, as in the case of the description of the prior art, N
An example in which a P-type impurity is diffused into a shaped wafer (substrate) to form a light emitting portion of an LED element will be described. Further, the resist is also made a negative type as in the conventional case.

First, as shown in FIG. 1A, a first diffusion mask 2 (which will be a lower layer) is formed on an N-type wafer 1, and then a second diffusion mask 3 (which is a lower layer) is formed thereon. (To be an upper layer). These diffusion masks 2 and 3 are made of alumina or nitride film as in the conventional case, and are preferably made of different materials for the etching conditions described later.

Next, as shown in FIG. 1B, a first resist 4 is applied on the second diffusion mask 3, and FIG.
As shown in (1), a first photolithographic mask 5 for patterning a portion where a light emitting portion is to be formed is set (mask alignment) and exposed. After development, the first resist 4 is patterned as shown in FIG. 1 (d1). That is, this is the pattern of the place where the light emitting section is to be formed. When etching is performed using the pattern of the first resist 4 as a mask, the upper second diffusion mask 3 is patterned as shown in FIG. 1 (e1). In other words, the etching is performed under the condition that the first diffusion mask 2 is not etched.

Next, as shown in FIG. 1 (f1), a second resist 6 is applied again on the structure formed so far, and again as shown in FIG. 1 (g1), for forming a light emitting portion. The second photolithographic mask 7 is set and exposed. This second
Since the photolithographic mask 7 is for forming the light emitting portion as described above, it has the same pattern as the first photolithographic mask 5, but in the present embodiment, a portion that blocks light (also referred to as a shadow portion. The second photolithographic mask 7 has a larger size than the first photolithographic mask 5 because it is a negative shape. That is, the first photolithographic mask 5 shown in FIG.
The relationship between the shadow portion size W and the shadow portion size W 'of the second photolithographic mask 7 shown in FIG. 1 (g1) is W'> W. This is to prevent a pattern error due to two mask alignments.

After the exposure, development is performed as shown in FIG.
A pattern of the second resist 6 is formed as in 1). Then, as shown in FIG. 2 (h1), a structure is formed in which the patterns of the second diffusion mask 3 and the second resist 6 are overlapped.

Next, etching is performed using the above-described structure as a mask, and the second resist 6 is removed. As a result, as shown in FIG. 2 (i1), the structure is patterned up to the first diffusion mask 2 in the lower layer. . In the etching, the upper second diffusion mask 3 is not etched at all,
Even if done. It is the first photolitho mask 5
Although there is the aforementioned difference W '> W in the size of the shadow portion between the second photolithographic mask 7 and the second photolithographic mask 7, it is for the purpose of preventing a pattern error as described above. is there. Obviously, the first diffusion mask 2 to be etched is a portion where the second diffusion mask 3 is etched and a portion where the second resist 6 does not remain. Like 2 (i1),
Two-layer patterns of the first and second diffusion masks 2 and 3 are formed.

Next, as shown in FIG. 2 (j1), a P-type impurity is implanted into the etched portion, that is, the light emitting portion in the same manner as in the prior art, using the structure formed up to the above as a mask, to form a P layer 9. The electrode 10 is also formed in the same manner as in the prior art so as to be in contact therewith to obtain the structure of FIG.

The above description is a process in the case where there is no photolitho defect described in the section of the prior art.

FIGS. 1 (d2) to 2 (k2) show an embodiment in which the photolitho defect exists, which will be described below.

As shown in FIG. 1 (d2), if there is a photolitho defect (hereinafter simply referred to as a defect) 8 at the time of the first development, in the etching step, as shown in FIG.
Of the diffusion mask 3 is also etched.

However, in this embodiment, after that, as described above, the second resist 6 is applied as shown in FIG. 1 (f2), and the second photolithographic mask 7 is set as shown in FIG. 1 (g2). Since exposure and development are performed (FIG. 2 (h2)), the second resist 6 remains on the defective portion 8 during the second development. That is, the probability that the first and second photolithographic masks 5 and 7 have a defect at exactly the same location is extremely small as almost zero. Therefore, at the time of the second etching (FIG. 2 (i2)), the first diffusion mask 2 is not etched. That is the subsequent step, P
The formation of the layer 9 (FIG. 2 (j2)) does not cause the formation of the P layer in the defect portion 8, and the formation of the electrode 10 (FIG. 2 (k2)) does not hinder at all.

Even if a defect 18 is formed during the second development (FIG. 2 (h2)) (of course, at a location different from the defect during the first development), the second etching (FIG. 2 (i2)) In ()), since the first diffusion mask is etched, the second diffusion mask 3 is not etched. Even if it is etched, the first diffusion mask 2 is not etched.

Accordingly, since the P layer 9 is not formed in any of the defective portions, there is no adverse effect on the light emitting portion.

Although this embodiment has two diffusion masks, it goes without saying that more than two diffusion masks may be stacked. The point is to balance the probability of defects with the number of steps. In the use of the photolitho mask twice, the size of the shadow portion was made larger in the second mask.
Even if the first and second masks are misaligned, the portion where the first diffusion mask of the lower layer is etched is determined by the first mask alignment (in the opposite case, it is determined by the second mask), and the production yield is reduced. And improve efficiency.

Although the first embodiment described above can sufficiently remove the adverse effects of photolithographic defects, this embodiment focuses on the formation of two or more diffusion masks, and does not increase the number of manufacturing steps and manufacturing equipment. Absent. Therefore, a method of obtaining the same effect even with one diffusion mask is shown in FIGS. 4 and 5 as a second embodiment, and will be described below.

In this embodiment, as in the first embodiment, the substrate is obtained by diffusing a P-type impurity into an N-type wafer.
The resist is negative.

First, as shown in FIG. 4A, a diffusion mask 2 is formed on an N-type wafer 1. The film 2 plays a role of blocking impurities in a diffusion step described later. Next, a first resist 4 is applied thereon as shown in FIG.

Since the resist 4 has a negative shape as described above, the first photolithographic mask 5 in which the portion from which the resist is to be removed is shaded is used, and the mask is exposed as shown in FIG. Then, when developed, FIG. 4 (d1)
As shown in the figure, only the part where the light hits remains. That is, the location where the light emitting section is to be formed is patterned. The size W of the pattern in this step is set to be the same as the size of a portion where a P-type impurity 9 described later is diffused. At this time, there may be a case where a portion that is not desired to be exposed due to a scratch, dust, dirt, or the like of the first photolithographic mask 5 is also exposed. This is a so-called photolitho defect, and FIG. 4 (d2)
The description of the case where there is 8 will be described later. Therefore, the description up to that is the description of the process in a normal case without a photolitho defect.

Following the above steps, a second resist 6 is applied as shown in FIG. 4 (e1), and then a second photolithographic mask 7 (the pattern is the same as that of the first photolithographic mask 5) as shown in FIG. 4 (f1). ) Is set and exposed. The size of the pattern at this time is made larger than the above-mentioned W as in the first embodiment. After development, patterning is performed as shown in FIG. Also at this time, the same photolitho defect 18 (described later) occurs, but the probability of occurrence at the same location as the first photolithographic defect is extremely low. Further, as described above, since W <W 'as in the first embodiment, even if the first and second mask alignments are slightly shifted, the portion where the diffusion mask 2 is exposed is the first mask 5 Will be decided. However, this relationship may be W> W ′, in which case the exposed portion of the diffusion mask 2 is determined by the second mask 7.

Next, using the pattern as a mask, the diffusion mask 2 is etched as shown in FIG. 5 (h1), and the resists 4 and 6 are removed.

Then, as in the first embodiment, FIG. 5 (i1)
Through a window opened in the diffusion mask 2 as shown in FIG.
Is diffused, and an electrode 10 is formed as shown in FIG.
The light emitting section of the ED element is completed.

Next, the case where there is a photolitho defect described above (hereinafter, sometimes simply referred to as a defect) will be described with reference to FIG.
2) to FIG. 5 (j2) for explanation. As shown in FIG. 4D2, even if there is a photolitho defect 8 during the first development, it is covered with the second resist 6 (FIG. 4E
2)) In the second patterning, as shown in FIG. 5 (g2), the resist 6 remains in the defective portion 8, and the diffusion mask 2 in that portion is not etched. In addition, when the defect 18 due to the second photolithographic mask occurs as shown in FIG. 5G2 (the probability of occurrence of the defect 18 at the same location as the first defect 8 is extremely low as described above), the first resist 4, the diffusion mask 2 in that portion is not etched.
Therefore, a P-type diffusion layer is not formed in an unnecessary portion.

In the embodiment described above, it is assumed that the probability that the first and second photolithographic defects occur at the same location is extremely low.
Alternatively, a defect occurs through the two layers of resist, such as when a jig or the like is used when handling a wafer. In that case, the diffusion mask at that portion is naturally etched.

A method for eliminating the influence of such a defect is shown in FIGS. 6 and 7 as a third embodiment and will be described below. The conditions such as the substrate and the resist are the same as in the first and second embodiments.

A diffusion mask 2 is formed on an N-type wafer 1 (FIG. 6A), and a first resist 4 is applied thereon (FIG. 6A).
(B)), the first photolithography mask 5 (the condition of the pattern size W is the same as in the second embodiment) (FIG. 6 (c)) (FIG. 6 (c)) until the second photolithography This is the same as the embodiment. Hereinafter, the steps in the case where there is no defect will be described first.

Next, as shown in FIG. 6E1, the diffusion mask 2 is etched by using the patterned first resist as a mask. The etching depth at this time is smaller (t) than the thickness T of the diffusion mask 2 as shown in the figure.

Next, as shown in FIG.
Is applied, and is exposed using a second photolithographic mask as shown in FIG. 7 (g1). The size W 'of the pattern is made larger than the above-mentioned W as in the second embodiment. After development, the resist 6 is patterned as shown in FIG. 7 (h1).

Next, as shown in FIG. 7 (i1), the diffusion mask 2 is etched a second time using the patterned resists 4 and 6 as a mask. The depth of the etching at this time is the diffusion mask 2 remaining after the first etching.
, And smaller than the thickness T of the diffusion mask 2.

Thereafter, formation of the P layer 9 and the electrode 10 (FIG. 7)
(J1) (k1)) are the same as in the first and second embodiments.

When the first photolithographic defect 8 occurs in this embodiment, the portion is covered with the second resist 6 as in the second embodiment, so that FIGS. 6 (d2) to 7 (h)
As shown in 2), adverse effects are hindered.

When the second defect 18 occurs through the two layers of the resists 4 and 6 as shown in FIG. 7 (h2), the subsequent etching is performed with the thickness T of the diffusion mask as described above.
Since it is larger than −t and smaller than T, the defect 18 is not etched until the surface of the substrate 1 is exposed (FIG. 7 (i2) and below). That is, the diffusion mask 2 at that portion
Remains on the substrate 1 surface. Therefore, the P layer is not formed on the substrate 1 in that portion.

In the above embodiment, the mask pattern is used as the diffusion mask of the LED element. However, the present invention is not limited to this.
It is possible to prevent impurity diffusion or short circuit from occurring in an incorrect region.

[0042]

As described above, according to the forming method of the present invention, even if there is a photolitho defect, it does not adversely affect the mask pattern (unnecessary diffusion layers are formed). Therefore, an extremely reliable semiconductor device can be realized.

[Brief description of the drawings]

FIG. 1 shows a first embodiment (No. 1) of the present invention.

FIG. 2 shows a first embodiment (No. 2) of the present invention.

FIG. 3 shows a conventional example.

FIG. 4 shows a second embodiment (part 1) of the present invention.

FIG. 5 shows a second embodiment (No. 2) of the present invention.

FIG. 6 shows a third embodiment (part 1) of the present invention.

FIG. 7 shows a third embodiment of the present invention (part 2).

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 N-type wafer 2 1st diffusion mask 3 2nd diffusion mask 4 1st resist 5 1st photolitho mask 6 2nd resist 7 2nd photolitho mask 8, 18 Photolitho defect

────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Yasuhiro Tsuno 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (56) References JP-A-62-162370 (JP, A) JP-A-62-162370 59-165473 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 33/00 H01L 21/3065

Claims (5)

(57) [Claims] 1. A step of (a) laminating at least two mask layers on a semiconductor substrate; and (b) applying a first resist layer on the mask layer, and forming the first resist layer on a predetermined layer. The first mask pattern having a pattern is selectively removed using a first mask pattern.
(C) forming a second mask pattern by selectively removing a predetermined portion of the mask layer, which is an upper layer, using the first resist pattern; d) applying a second resist layer on the second mask pattern, and selectively removing the second resist layer using the third mask pattern having the predetermined pattern; And e) forming a fourth mask pattern by selectively removing a predetermined portion of the underlying mask layer using the second resist pattern. A method of forming a mask pattern. 2. The method according to claim 1, wherein a size of the predetermined pattern in the third mask pattern is larger than a size of the predetermined pattern in the first mask pattern. (A) forming a mask layer on a semiconductor substrate; and (b) applying a first resist layer on the mask layer, wherein the first resist layer has a predetermined pattern. Forming a first resist pattern by selectively removing using a first mask pattern; and (c) applying a second resist layer on the first resist pattern, Forming a second resist pattern by selectively removing the resist layer using the second mask pattern having the predetermined pattern; and (d) using the first and second resist patterns. Forming a third mask pattern by selectively removing the mask layer. 4. The method according to claim 3, wherein the size of the predetermined pattern in the second mask pattern is larger than the size of the predetermined pattern in the first mask pattern. 5. The method according to claim 1, wherein the mask layer is used as a diffusion mask for forming a light emitting portion of a light emitting diode element.