JP3147861B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an embedded memory chip.

[0002]

2. Description of the Related Art Conventionally, a semiconductor device has a structure in which a plurality of memory chips are mixedly mounted on a single substrate. In this type of semiconductor device, when one of the mixed memory chips is defective, a means for effectively using the remaining chips is taken, and the mixed chip itself is treated as a defective product. A technique for avoiding the problem is applied, and an example of the technique is disclosed in, for example, Japanese Patent Application Laid-Open No. 9-265792.

The technique disclosed in Japanese Patent Application Laid-Open No. 9-265792 discloses a technique of electrically connecting a power supply line for supplying power to a memory cell power supply line and a plurality of bit lines for each normal memory cell group, Further, there is provided means for electrically disconnecting the common connection line provided for each normal memory cell group from a power supply line supplied from a power supply pad.

In the technique disclosed in Japanese Patent Application Laid-Open No. 9-265792, power is supplied to a power supply line and a bit load circuit of all memory cells constituting a sub-block which become unnecessary when a defective memory cell occurs. The power supply line is made to be floating, and the leakage current path is cut off.

[0005]

However, in the technique disclosed in Japanese Patent Application Laid-Open No. 9-265792, a power supply line corresponding to a defective memory cell is uniformly set to a floating state and a leakage current path is cut off. Since the wells are shared, there is a problem that a leak current occurs.

In order to solve the above-mentioned problems, Japanese Patent Laid-Open No.
As disclosed in Japanese Patent Publication No. 111350, it is conceivable to interpose a protection circuit. As the protection circuit, a field transistor or a transistor which is normally off is used.

However, in consideration of the recent demand for downsizing of the package with the downsizing of the portable terminal, a field transistor or a transistor which is normally off is added as a protection circuit in addition to the memory cell group. As a result, the dimensions of the package are enlarged, and there is a problem in directly applying the technique disclosed in Japanese Patent Application Laid-Open No. 4-111350.

In Japanese Patent Application Laid-Open No. 63-301545, a MOS standard cell composed of a MOS transistor and a bipolar standard cell composed of a bipolar transistor are prepared in a library, and these are separated into islands by a buried layer and a well. A technology is disclosed in which the power supply voltage is formed independently in a region where the power supply voltage is set.

Further, Japanese Patent Application Laid-Open No. 4-65867 discloses that
A technology in which a power supply pad and a signal pad are provided for each circuit function is disclosed.

Therefore, it is conceivable to use the techniques disclosed in JP-A-63-301545 and JP-A-4-65867. In addition, the positions of the power supply and the signal pin in the package when disconnected are not specified, and there is a possibility that a signal causing a malfunction may be input to the remaining normal memory cells.

An object of the present invention is to provide a semiconductor device capable of supplying a normal signal without error to a remaining memory cell group which has been partially separated due to occurrence of an abnormality.

[0012]

In order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device comprising a memory chip on which a plurality of memory cells are mounted, wherein the memory chip comprises a plurality of memory cells. A power pin, a signal pin, and a ground pin which are provided in common with each other, and the power pad, the signal pad, and the ground pad of the memory cell are adjacent to the power pin, the signal pin, and the ground pin. And the corresponding pins and pads are electrically wired.

The power supply pad, signal pad and ground pad are provided independently for each memory cell.

The power supply pad, the signal pad and the ground pad are provided so as to be distinguished from those used when mixedly used and those used when only memory cells are used.

The memory cells are formed so as to be electrically separated.

The corresponding pins and pads are electrically processed by wire bonding.

Further, the memory chip comprises a ROM and a RAM.
And the memory cells are mixed.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 FIG. 1 is a configuration diagram showing a semiconductor device according to Embodiment 1 of the present invention.

A semiconductor device according to the first embodiment of the present invention shown in FIG. 1 has a memory chip 1 in which a plurality of memory cells are mounted.
A memory chip 1 shown in FIG.
Has mixed memory cells 2 and 3 of ROM and RAM.

In FIG. 1, a memory chip 1 has a ROM
And a power pin 4 (see FIGS. 2 and 3), a signal pin 5, and a ground pin 6 (see FIG. 2) which are positioned and provided in common with the memory cells 2 and 3 of the RAM.

As shown in FIGS. 1 and 3, the memory cell 2
The power pad 7a, the signal pad 8a and the ground pad 9a of the memory cell 3 and the power pad 7b, the signal pad 8b and the ground pad 9b of the memory cell 3
The corresponding pins 4, 5, 6 and pads 7a, 7b, 8a, 8 are provided adjacent to the signal pin 5 and the ground pin 6.
The wires b, 9a, and 9b are electrically wired by the wire bonding 10.

Generally, the memory cells 2 and 3 of the ROM and the RAM mixedly mounted on the memory chip 1 are commonly connected by a common connection line in order to share the power supply and the ground. Specifically, the source electrode or the drain electrode of the transistors forming the memory cells 2 and 3 are commonly connected by an N-well or P-well semiconductor layer.

However, in the first embodiment of the present invention,
The memory cells 2 and 3 are formed electrically separated.
Specifically, the N-well or P-well semiconductor layer that commonly connects the source electrode or the drain electrode of the transistors forming the memory cells 2 and 3 is deleted, and the memory cells 2 and 3 are removed.
The gaps are electrically separated.

In the first embodiment of the present invention, the power supply pad 7a, the signal pad 8a and the ground pad 9a of the memory cell 2 and the memory cell 2 The three power supply pads 7b, the signal pads 8b, and the ground pads 9b are provided electrically independently for each of the memory cells 2 and 3.

The first embodiment of the present invention shown in FIG.
it's MASKROM and 1MBit's STATICRA
The present invention is applied to a memory chip 1 on which M memory cells 2 and 3 are mounted.

In the first embodiment of the present invention shown in FIG.
2MBit MASKROM and 1MBit STATI
Memory chip 1 in which memory cells 2 and 3 of CRAM are mounted
As shown in FIG. 2A, the embedded memory chip includes a power supply pin, a signal pin, and a ground pin.
T with 8 x 13.4 mm external dimensions
It is configured as an SOP type chip.

According to the current semiconductor device manufacturing technology, 1
MBIT STATICRAM memory cell 3 or 2
A memory chip (hereinafter, referred to as a single memory chip) 1 on which a memory cell 2 of a MASKROM of MBit is independently mounted.
As shown in FIG. 2B, a has 32 pins including a power supply pin, a signal pin, and a ground pin, and has an outer dimension of 8 × 13.4 mm.

As shown in FIGS. 2A and 2B, the memory chip 1 in the first embodiment of the present invention shown in FIG. 1 has 32 pins including a power supply pin, a signal pin, and a ground pin. Its external dimensions are 8 × 13.4mm and 1MB
It is a memory chip (hereinafter referred to as a single memory chip) 1 on which a STATICRAM memory cell 3 is mounted alone.
It has the same pin arrangement and outer dimensions as those of FIG.

The reason that the memory chip 1 according to the first embodiment of the present invention shown in FIG. 2A can be configured to have the same pin arrangement and external dimensions as the single memory chip 1a shown in FIG. , A power pin 4 commonly positioned and positioned with respect to the memory cells 2 and 3 of the ROM and the RAM.
It has a signal pin 5 and a ground pin 6, and has a memory cell 2,
3, power pads 7a and 7b, signal pads 8a and 8b, and ground pads 9a and 9b are provided adjacent to the power pin 4, the signal pin 5 and the ground pin 6, respectively.
5, 6 and the pads 7a, 7b, 8a, 8b, 9a, 9b are to be electrically wired by the wire bonding 10.

In the memory chips shown in FIGS. 2A and 2B, the power supply pin 4 corresponds to the pin labeled Vcc, and the ground pin 6 corresponds to the pin labeled GND. And signal pins 5 are denoted by symbols A0 to A1.
7, I / O1 to I / O8, / OE, / WE, / CE1 and / CE2 (/ ROM CS, / RAM CS).

Here, pins A0 to A17 are pins for inputting an address, I / O1 to I / O8 are pins for inputting data, a / OE pin is a pin for outputting output data, and / WE Is a pin for inputting a write signal, the / ROM CS pin is a pin for inputting a signal for operating the ROM, and the / RAM CS pin is a pin for inputting a signal for operating the RAM.

In the case of the single memory chip 1a shown in FIG. 2B, the / CE1 and / CE2 pins are enabled (En
2), the signal does not cause any particular problem. However, in the case of the embedded memory chip 1 shown in FIG.
Because it is AM and MASKROM, / CE1 pin, / C
It is impossible to use the E2 pin only for inputting the Enable signal.

Therefore, in the first embodiment of the present invention, FIG.
As shown in (a), the / CE1 and / CE2 pins as signal pins 5 are used as the / ROM CS pin and / RAM CS pin, and the / ROM CS pin and the / RAM CS pin are selected. By performing wire bonding 10, a ROM Enable signal and a ROM Enable signal are input, and the STATIC
RAM memory cell 3 and MASKROM memory cell 2
And select to work.

STATIC in Embodiment 1 of the Present Invention
RAM memory cell 3 and MASKROM memory cell 2
Means ROM selection pin (/ ROM CS pin) and RAM
It is determined by the logic of the selection pin (/ ROM CS pin), and the logic is shown in Table 1.

[0036]

[Table 1] Here, H indicates a high level, L indicates a low level, and X indicates invalid.

Memory cell 2 and STAT of MASKROM
If both of the memory cells 3 of the ICRAM are non-defective, as shown in FIG. And perform normal operation as the embedded memory chip 1.

When the memory cell 2 of the MASKROM is defective, the power supply to the memory cell 2 of the defective MASKROM is cut off by not performing wire bonding 10 on the power supply pad 7a for the MASKROM as shown in FIG. 3B.

In this case, the memory cell 2 of the MASKROM
And the memory cell 3 of the STATICRAM are electrically isolated, so that no current flows through the memory cell 2 of the defective MASKROM.

As can be seen from the logic of Table 1, / R
Connect the OM CS pin to the power pin 4 by wire bonding 10
Is performed, the memory cell 2 of the MASKROM can be forcibly deselected.
Can be used as the STATICRAM single chip 1a.

As described above, according to the first embodiment of the present invention, even if one of the memory cells in the mixed memory chip is defective with an increase in current, if the other memory cell is non-defective, the non-defective product is As a single memory chip. As a result, a product can be produced from defective products that have been conventionally discarded, and the yield can be indirectly improved.

The specific numerical values in the case of considering a mixed memory chip of STATICRAM and MASKROM are as follows.
If the calculation is performed in the case where the yield of each of the ICRAM and the MASKROM as a single memory chip is 80%, the yield of the embedded memory chip is reduced to 64% in the conventional technology.

However, in the first embodiment of the present invention, the difference between the single memory chip and the embedded memory chip is 16%
Since the ATICRAM can be relieved as a single memory chip, the yield of the embedded memory chip is indirectly reduced by 8%.
It can be raised to 0%. As can be seen from the above example, the present invention is effective as the yield of each memory chip to be mixed is low, and is effective as the number of memories to be mixed increases.

(Embodiment 2) FIG. 4 is a configuration diagram showing Embodiment 2 of the present invention.

In the second embodiment of the present invention shown in FIG. 4, two or more types of memory cells 11a and 11b are mounted on the memory chip 1. In the second embodiment of the present invention shown in FIG. Power supply pad 12a, signal pad 13a
And the ground pad 14a and the power supply pad 12b, the signal pad 13b, and the ground pad 14b when the memory cell is used alone.

In the second embodiment of the present invention shown in FIG. 4, the power supply pad 12a, the signal pad 13a and the ground pad 14a when the memory cell is used alone, and the power supply pad 12b, the signal pad 13b and the ground pad 14b when the memory cell is used alone.
The power supply pin 4, the signal pin 5 and the ground pin 6
The wire bonding 10 can be easily performed. Other configurations are the same as in the first embodiment.

According to the second embodiment of the present invention shown in FIG.
A power pad, signal pad, and ground pad for normal use as the embedded memory chip 1 and a power pad, signal pad, and ground pad for use as a single memory chip when a memory cell is defective are dedicated for distinction. , The versatility can be maintained.

(Embodiment 3) FIG. 5 is a configuration diagram showing Embodiment 3 of the present invention.

The embodiment of the present invention shown in FIGS.
The case where the memory cells of the STATICRAM and the MASKROM are mixed has been described. However, the third embodiment of the present invention shown in FIG.
STATICRAM memory cell 15b, MAS
This is a memory chip in which three or more memory cells including a memory cell 15c of a KROM are mixedly mounted. Other configurations are the same as those shown in FIGS. 1 and 4.

Assuming that the yield of each memory chip alone is 80%, the yield of the embedded memory chip when the third embodiment of the present invention is not used is 51.2%.

However, according to the third embodiment of the present invention, DY
NAMICRAM memory cell 15a and STATICR
When repairing the memory cell 15b of AM, 44.8%
, The yield of embedded memory chips can be indirectly reduced to 96%.

[0060]

As described above, according to the present invention, when one of the mixed memory chips is defective, not only can the remaining chips be used effectively, A normal signal can be supplied without error to a memory cell group in which a part where an abnormality has occurred is separated.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram illustrating a specific example of the semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a configuration diagram illustrating an operation of the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a configuration diagram illustrating a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a configuration diagram illustrating a semiconductor device according to a third embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Mixed memory chip 1a Single memory chip 2 Memory cell 3 Memory cell 4 Electrode pin 5 Signal pin 6 Ground pin 7a, 7b Electrode pad 8a, 8b Signal pad 9a, 9b Ground pad 10 Wire bonding

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/10 H01L 21/82 H01L 21/822 H01L 27/04

Claims (6)

(57) [Claims] 1. A semiconductor device comprising a memory chip in which a plurality of memory cells are mounted, wherein the memory chip includes a power pin, a signal pin, and a ground pin which are positioned and commonly provided with respect to the plurality of memory cells. And a power pad, a signal pad, and a ground pad of the memory cell are provided adjacent to the power pin, the signal pin, and the ground pin, and the corresponding pins and pads are electrically wired. A semiconductor device, comprising: 2. The semiconductor device according to claim 1, wherein the power supply pad, the signal pad, and the ground pad are provided independently for each memory cell. 3. The semiconductor according to claim 1, wherein the power supply pad, the signal pad and the ground pad are provided so as to be distinguished from ones used in a mixed use and those used only in a memory cell. apparatus. 4. The semiconductor device according to claim 1, wherein said memory cells are formed electrically separated. 5. The semiconductor device according to claim 1, wherein the corresponding pins and pads are electrically processed by wire bonding. 6. The semiconductor device according to claim 1, wherein the memory chip includes a combination of ROM and RAM memory cells.