JP3396830B2 - Circuit board and semiconductor circuit device using the same - Google Patents

Circuit board and semiconductor circuit device using the same

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Publication number
JP3396830B2
JP3396830B2 JP26955296A JP26955296A JP3396830B2 JP 3396830 B2 JP3396830 B2 JP 3396830B2 JP 26955296 A JP26955296 A JP 26955296A JP 26955296 A JP26955296 A JP 26955296A JP 3396830 B2 JP3396830 B2 JP 3396830B2
Authority
JP
Japan
Prior art keywords
circuit board
bonding pad
circuit
pattern
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP26955296A
Other languages
Japanese (ja)
Other versions
JPH10116854A (en
Inventor
啓一 植木
Original Assignee
日本電気エンジニアリング株式会社
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Filing date
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Application filed by 日本電気エンジニアリング株式会社 filed Critical 日本電気エンジニアリング株式会社
Priority to JP26955296A priority Critical patent/JP3396830B2/en
Publication of JPH10116854A publication Critical patent/JPH10116854A/en
Application granted granted Critical
Publication of JP3396830B2 publication Critical patent/JP3396830B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
    • H10W42/281—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons characterised by their materials
    • H10W42/287—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons characterised by their materials materials for magnetic shielding, e.g. ferromagnetic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/521—Structures or relative sizes of bond wires
    • H10W72/522—Multilayered bond wires, e.g. having a coating concentric around a core
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/543—Dispositions of bond wires of outermost layers of multilayered bond wires, e.g. coating being only on a part of a core
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/555—Materials of bond wires of outermost layers of multilayered bond wires, e.g. material of a coating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は回路基板及びそれを
用いた半導体回路装置に関し、特に半導体チップの出力
をボンディングパッドに対してボンディングワイヤを使
用して接続する様にした回路基板及びそれを用いた半導
体回路装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board and a semiconductor circuit device using the same, and more particularly to a circuit board for connecting the output of a semiconductor chip to a bonding pad by using a bonding wire and the same. The present invention relates to a semiconductor circuit device.

【０００２】[0002]

【従来の技術】半導体回路装置の高速化等が進むと、信
号の立上りや立下り時に急峻な電流変化が生じることに
なる。この電流には高周波成分が含まれており、これに
より発振やノイズが生じて回路の誤動作の要因となる。2. Description of the Related Art As the speed of a semiconductor circuit device increases, a sharp current change occurs when a signal rises or falls. This current contains a high frequency component, which causes oscillation and noise, which causes malfunction of the circuit.

【０００３】そこで、図２に示す如きノイズ防止対策
が、特開平４−１０９６３９号公報に提案されている。
この例では、ボンディングワイヤに流れる急峻な電流に
よるノイズや発振防止を行うものである。Therefore, a noise prevention measure as shown in FIG. 2 is proposed in Japanese Patent Laid-Open No. 109639/1992.
In this example, noise and oscillation are prevented by the steep current flowing through the bonding wire.

【０００４】図２（Ａ）を参照すると、半導体チップ６
のボンディングパッド６１とリードフレームのインナー
リード１１との間のボンディングワイヤ５の一部に、フ
ェライトビーズ１２を予め挿通せしめておくことで、ノ
イズ等の防止を行うものである。Referring to FIG. 2A, the semiconductor chip 6
By inserting the ferrite beads 12 into a part of the bonding wire 5 between the bonding pad 61 and the inner lead 11 of the lead frame in advance, noise or the like is prevented.

【０００５】図２（Ｂ）を参照すると、ボンディングワ
イヤ５のボンディングを行った後に、このワイヤの全面
に磁性膜１２をコーティングしたものであり、塗布また
は蒸着によりコーティングがなされる様になっている。Referring to FIG. 2B, after the bonding wire 5 is bonded, the entire surface of this wire is coated with a magnetic film 12, which is coated or vapor-deposited. .

【０００６】[0006]

【発明が解決しようとする課題】図２（Ａ），（Ｂ）に
示した構造により、ワイヤ５を通過する信号の急峻な立
上りや立下り時に生ずる電流変化を鈍化させて、ノイズ
の発生の抑止や高周波成分を除去することが可能となる
が、以下の如き欠点を有している。With the structure shown in FIGS. 2A and 2B, the change in current that occurs at the steep rise and fall of the signal passing through the wire 5 is slowed down, and noise is generated. Although it is possible to suppress or remove high frequency components, it has the following drawbacks.

【０００７】図２（Ａ）の例では、ボンディングワイヤ
に予めフェライトビーズを通しておくことが必要であり
作業性が悪く、またフェライトビーズが非常に短いボン
ディングワイヤ周囲に設けられているので、フェライト
ビーズを何等かの方法で固定しない限り、持ち運び等に
よる振動でボンディングワイヤが切断されたり、部品す
なわち半導体チップと接触したりして、破損する可能性
があるという問題がある。In the example of FIG. 2 (A), it is necessary to pass the ferrite beads through the bonding wires in advance, and the workability is poor, and since the ferrite beads are provided around the bonding wires that are very short, the ferrite beads are not used. Unless it is fixed by some method, there is a problem that the bonding wire may be broken or may come into contact with a component, that is, a semiconductor chip due to vibration caused by carrying or the like and may be damaged.

【０００８】図２（Ｂ）の例では、極めて短いボンディ
ングワイヤに磁性膜を塗布したり蒸着したりする必要が
あるために、作業性が著しく低下するという欠点があ
る。The example shown in FIG. 2B has a drawback that the workability is remarkably reduced because it is necessary to coat or deposit a magnetic film on an extremely short bonding wire.

【０００９】本発明の目的は、作業性の低下をなくして
ノイズや高周波成分の抑圧を有効に行い得る様にした回
路基板及びそれを用いた半導体回路基板を提供すること
である。An object of the present invention is to provide a circuit board and a semiconductor circuit board using the same, which can suppress noise and high frequency components effectively without reducing workability.

【００１０】[0010]

【課題を解決するための手段】本発明による回路基板
は、ボンディングパッドを有し、このボンディングパッ
ドに半導体チップの出力をボンディングワイヤにて接続
する様にした回路基板であって、前記ボンディングパッ
ドの周囲を囲む様に設けられた磁性材膜と、前記磁性材
膜と基板上面との間に設けられたグランドパターン膜と
を含むことを特徴とする。A circuit board according to the present invention is a circuit board having a bonding pad, and the output of a semiconductor chip is connected to the bonding pad by a bonding wire. A magnetic material film provided so as to surround the periphery, and the magnetic material
A ground pattern film provided between the film and the upper surface of the substrate .

【００１１】更に、前記ボンディングパッドに接続され
たビアホールと、このビアホールに接続された内層回路
パターンとを更に含むことを特徴とする。 Further, it is connected to the bonding pad.
Via hole and inner layer circuit connected to this via hole
And a pattern.

【００１２】本発明による半導体回路装置は、回路基板
と、この回路基板の一主面に設けられたボンディングパ
ッドと、前記一主面に設けられた半導体チップと、この
半導体チップの出力と前記ボンディングパッドとを接続
するボンディングワイヤと、前記ボンディングパッドの
周囲を囲む様に設けられた磁性材膜と、前記磁性材膜と
前記回路基板の一主面上に設けられたグランドパターン
膜とを含むことを特徴とする。A semiconductor circuit device according to the present invention includes a circuit board, a bonding pad provided on one main surface of the circuit board, a semiconductor chip provided on the one main surface, an output of the semiconductor chip and the bonding. A bonding wire connecting the pad, a magnetic material film provided so as to surround the periphery of the bonding pad, and the magnetic material film
A ground pattern provided on one main surface of the circuit board
And a film .

【００１３】更に、前記回路基板に設けられ前記ボンデ
ィングパッドに接続されたビアホールと、前記回路基板
に設けられ前記ビアホールと接続された内層回路パター
ンとを更に含むことを特徴とする。 Further, the bonder is provided on the circuit board.
Via hole connected to the wiring pad and the circuit board
An inner layer circuit pattern provided on the inner surface and connected to the via hole
And are further included.

【００１４】[0014]

【発明の実施の形態】以下に図面を参照しつつ本発明の
実施例について説明する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

【００１５】図１は本発明の実施例の構成を示す図であ
り、図１（Ａ）は平面図、（Ｂ）は（Ａ）のＡ−Ａ´線
に沿う断面図である。尚、図２と同等部分は同一符号に
より示している。1A and 1B are views showing the configuration of an embodiment of the present invention. FIG. 1A is a plan view and FIG. 1B is a sectional view taken along the line AA 'in FIG. The same parts as those in FIG. 2 are indicated by the same reference numerals.

【００１６】図１を参照すると、本実施例の回路基板１
００は２層構造（図１（Ｂ）参照）となっており、最上
層（外層）の配線パターン１１はビアホール４により内
層の配線パターン１０に接続されている。また、ビアホ
ール３により内層の配線パターン１０とボンディングパ
ッド８とが接続されている。Referring to FIG. 1, a circuit board 1 according to this embodiment.
00 has a two-layer structure (see FIG. 1B), and the uppermost (outer layer) wiring pattern 11 is connected to the inner layer wiring pattern 10 through the via hole 4. In addition, the wiring pattern 10 in the inner layer and the bonding pad 8 are connected by the via hole 3.

【００１７】このボンディングパッド８と半導体チップ
（ベアチップと呼ばれる）６の出力とは、ボンディング
ワイヤ５にて接続されている。このボンディングパッド
８の回りを取囲む様に、磁性膜２が設けられており、こ
の磁性膜２は回路基板１００の一主面上に、グランドパ
ターン１を介して形成されている。The bonding pad 8 and the output of the semiconductor chip (called a bare chip) 6 are connected by a bonding wire 5. A magnetic film 2 is provided so as to surround the bonding pad 8, and the magnetic film 2 is formed on one main surface of the circuit board 100 with a ground pattern 1 interposed therebetween.

【００１８】尚、７はベアチップ６を回路基板１００の
一主面上に取付けるためのマウントパターンを示すもの
である。Reference numeral 7 denotes a mount pattern for mounting the bare chip 6 on one main surface of the circuit board 100.

【００１９】次に信号の流れについて説明する。ベアチ
ップ６の出力信号は急峻な立上り立下りを有した信号で
あり、この信号はボンディングワイヤ５を通り、基板１
００のパターン上へ伝送される。基板１００上のボンデ
ィングパッド８へ伝送された信号は、ボンディングパッ
ド８のすぐ横に設けられたビアホール３を通り、内層の
パターン１０へ伝送され、ビアホール４を通り再び外層
のパターン１１へ現れる。Next, the signal flow will be described. The output signal of the bare chip 6 is a signal having a steep rise and fall, and this signal passes through the bonding wire 5 and the substrate 1
00 pattern. The signal transmitted to the bonding pad 8 on the substrate 100 is transmitted to the pattern 10 in the inner layer through the via hole 3 provided immediately beside the bonding pad 8, and then appears again in the pattern 11 in the outer layer through the via hole 4.

【００２０】この際、ボンディングパッド８及びビアホ
ール３の周囲にはグランドパターン１とそれに塗布され
た磁性膜２とが設けられており、よって信号経路がビア
ホール及び内層のパターンよりこの磁性膜の外部へ抜け
ることにより、導体の周囲に磁性体を設けたものと等価
となり、ボンディングワイヤ５をフェライトビーズに通
したものと同じ効果が得られる。At this time, the ground pattern 1 and the magnetic film 2 applied to the ground pattern 1 are provided around the bonding pad 8 and the via hole 3, so that the signal path extends from the via hole and the inner layer pattern to the outside of this magnetic film. When the bonding wire 5 is removed, it becomes equivalent to a magnetic body provided around the conductor, and the same effect as that obtained by passing the bonding wire 5 through a ferrite bead is obtained.

【００２１】尚、磁性膜２を設ける箇所のパターンをグ
ランドパターン１とした例について説明したが、グラン
ドパターン１を用いた方がシールド効果が高められるた
めであり、使用する磁性膜によっては必ずしもグランド
パターンは必要なく、磁性膜を設けるのみでも効果は得
られる。Although the example in which the pattern of the portion where the magnetic film 2 is provided is the ground pattern 1 has been described, this is because the shield effect is enhanced by using the ground pattern 1, and the ground pattern 1 is not always necessary. The pattern is not necessary, and the effect can be obtained only by providing the magnetic film.

【００２２】この磁性膜としては、磁性材からなる薄膜
を用いることができるものであり、例えばアモルファス
状の磁性材からなるテープ（市販されている）を、適当
な形状に切断加工して用いることが可能である。As the magnetic film, a thin film made of a magnetic material can be used. For example, a tape (commercially available) made of an amorphous magnetic material is cut into an appropriate shape and used. Is possible.

【００２３】[0023]

【発明の効果】以上述べた様に、本発明によれば、ボン
ディングパッドの周囲に磁性膜を被着形成するのみの簡
単な構成であるので、作業性の低下なくノイズ軽減が可
能となるという効果がある。As described above, according to the present invention, since the magnetic film is simply deposited around the bonding pad, the noise can be reduced without lowering the workability. effective.

【００２４】また、ボンディングワイヤにフェライトビ
ーズをかぶせたり、磁性体を被着させたりする必要がな
いので、ワイヤに無用な力が作用することがなく、切断
や部品破損等の事故が防止できるものである。Further, since it is not necessary to cover the bonding wire with ferrite beads or to attach a magnetic substance, unnecessary force does not act on the wire, and accidents such as cutting and damage to parts can be prevented. Is.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の実施例の構成を示す図である。FIG. 1 is a diagram showing a configuration of an exemplary embodiment of the present invention.

【図２】従来例を示す構成図である。FIG. 2 is a configuration diagram showing a conventional example.

【符号の説明】[Explanation of symbols]

１ グランドパターン ２ 磁性膜 ３，４ ビアホール ５ ボンディングワイヤ ６ ベアチップ ７ マウントパターン ８ ボンディングパッド １０ 内層パターン １１ 外層パターン １００ 回路基板 1 grand pattern 2 Magnetic film 3,4 Beer hole 5 Bonding wire 6 bare chips 7 mount pattern 8 Bonding pad 10 Inner layer pattern 11 Outer layer pattern 100 circuit board

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/60 H03H 7/00 ─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. 7 , DB name) H01L 21/60 H03H 7/00

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 ボンディングパッドを有し、このボンデ
ィングパッドに半導体チップの出力をボンディングワイ
ヤにて接続する様にした回路基板であって、前記ボンデ
ィングパッドの周囲を囲む様に設けられた磁性材膜と、
前記磁性材膜と基板上面との間に設けられたグランドパ
ターン膜とを含むことを特徴とする回路基板。1. A circuit board having a bonding pad, the output of a semiconductor chip being connected to the bonding pad by a bonding wire, the magnetic material film being provided so as to surround the bonding pad. When,
A ground pattern provided between the magnetic material film and the upper surface of the substrate.
A circuit board including a turn film . 【請求項２】 前記ボンディングパッドに接続されたビ
アホールと、このビアホールに接続された内層回路パタ
ーンとを更に含むことを特徴とする請求項１記載の回路
基板。 2. A via connected to the bonding pad.
A hole and the inner layer circuit pattern connected to this via hole
The circuit of claim 1, further comprising:
substrate. 【請求項３】 回路基板と、この回路基板の一主面に設
けられたボンディングパッドと、前記一主面に設けられ
た半導体チップと、この半導体チップの出力と前記ボン
ディングパッドとを接続するボンディングワイヤと、前
記ボンディングパッドの周囲を囲む様に設けられた磁性
材膜と、前記磁性材膜と前記回路基板の一主面上に設け
られたグランドパターン膜とを含むことを特徴とする半
導体回路装置。 3. A circuit board and a main surface of the circuit board.
And a bonded bonding pad on the one main surface.
Semiconductor chip, the output of the semiconductor chip and the
Bonding wire to connect the
Magnetic property provided around the bonding pad
Material film, provided on the main surface of the magnetic material film and the circuit board
And a ground pattern film provided with
Conductor circuit device. 【請求項４】 前記回路基板に設けられ前記ボンディン
グパッドに接続されたビアホールと、前記回路基板に設
けられ前記ビアホールと接続された内層回路パターンと
を更に含むことを特徴とする請求項３記載の半導体回路
装置。 4. The bonder provided on the circuit board
Via holes connected to the circuit board and the circuit board.
And an inner layer circuit pattern connected to the via hole
The semiconductor circuit according to claim 3, further comprising:
apparatus.
JP26955296A 1996-10-11 1996-10-11 Circuit board and semiconductor circuit device using the same Expired - Fee Related JP3396830B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26955296A JP3396830B2 (en) 1996-10-11 1996-10-11 Circuit board and semiconductor circuit device using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26955296A JP3396830B2 (en) 1996-10-11 1996-10-11 Circuit board and semiconductor circuit device using the same

Publications (2)

Publication Number Publication Date
JPH10116854A JPH10116854A (en) 1998-05-06
JP3396830B2 true JP3396830B2 (en) 2003-04-14

Family

ID=17473975

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26955296A Expired - Fee Related JP3396830B2 (en) 1996-10-11 1996-10-11 Circuit board and semiconductor circuit device using the same

Country Status (1)

Country Link
JP (1) JP3396830B2 (en)

Also Published As

Publication number Publication date
JPH10116854A (en) 1998-05-06

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