JP3473506B2 - Pipeline processing equipment - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention includes an instruction overtaking buffer, a plurality of arithmetic units share a write port to a register file among the arithmetic units, and a replacement path (data replacement path) exists. Pipeline processing device.

[0002]

2. Description of the Related Art In a processor that realizes a pipeline processing device, a plurality of arithmetic units may share a write port to a register file among the arithmetic units. In such a case, conventionally, a larger number of arithmetic units than the number of arithmetic instructions that can be issued at the same time have been mounted.

FIG. 7 is a block diagram showing an outline of an example of the configuration of a processor (pipeline processing device) to which the present invention is applied.

In the pipeline processing apparatus shown in FIG. 7, a maximum of four operands can be read from the register file at the same time. Two of the operands are supplied to an address adder used in a memory access type instruction, and the other two operands are supplied to an arithmetic unit that executes an arithmetic operation or a logical operation.

In the data path structure in the pipeline processing apparatus shown in FIG. 7, two arithmetic units share a read port from the register file and a write port to the register file. Such sharing is performed because a RAM (Random Access Memory) hard macro that has a read port that can supply data to all arithmetic units at the same time and a write port that can write back data from all arithmetic units at the same time This is because it is difficult to use in terms of delay and delay. For this reason, although such a pipeline processing device includes two arithmetic units, the number of arithmetic instructions that can be issued simultaneously is limited to one.

Now, the execution process of the instruction sequence shown in FIG. 11 in the pipeline processing apparatus (processor) having the configuration shown in FIG. 7 will be described (see also the time chart of FIG. 12).

In FIG. 12, it is assumed that all the instructions in FIG. 11 are registered in the instruction overtaking buffer in FIG. 7 before time T0.

It is assumed that the LOAD instruction of the first instruction is issued at time T0, the SUB instruction of the sixth instruction is issued at time T1, and the ADD instruction of the second instruction is issued at time T2. Furthermore, after that, at time T3
An OR instruction of a third instruction that refers to the operation result of the first instruction is issued, and an ADD instruction of a fourth instruction that refers to the operation result of the second instruction is issued at time T4.
Fifth time referring to the operation result of the fourth instruction at time T5
It is assumed that the ADD instruction of the above instruction is issued.

By the way, at time T3, both the OR instruction of the third instruction and the ADD instruction of the fourth instruction have their operand dependencies resolved and are ready to be issued. Also, the OR instruction of the third instruction and the ADD of the fourth instruction
The type of arithmetic unit used differs from the instruction. Further, it is known that the ADD instruction of the fourth instruction overwrites the operation result S07 by the SUB instruction of the subsequent sixth instruction. Therefore, the fifth instruction that refers to the operation result of the fourth instruction If it can be guaranteed that the ADD instruction of the above will be issued while supplying the operand by using the replacement path around the arithmetic unit,
It is not always necessary to write back the operation result of the fourth instruction to the register file. In addition, at the time T3, one operand of each of the third instruction and the fourth instruction is supplied by the replacement path, so that the read port of the register file is left.

As described above, at time T3, even if the OR instruction of the third instruction and the AND instruction of the fourth instruction are issued at the same time, contention of the computing unit resources does not occur. Nevertheless, according to the prior art, it is actually time T3.
In, only the third instruction is issued.

[0011]

In the above-described conventional pipeline processing apparatus, even if a plurality of operation instructions are simultaneously issued at a fixed time of the pipeline processing, there is no conflict of operation unit resources. Since only one operation instruction is actually issued, there is a problem in that the performance corresponding to the input computing resource is not obtained. For example, although it is possible to issue the third instruction (OR instruction) and the fourth instruction (AND instruction) at the same time at time T3 in FIG. Was not done.

In view of the above points, an object of the present invention is to improve the efficiency of instruction issuance, to make more use of the performance of invested arithmetic unit hardware resources, and (EN) Provided is a pipeline processing device capable of improving the effective performance of a processor that realizes the line processing device.

[0013]

A pipeline processing apparatus according to the present invention is a pipeline processing apparatus in which a plurality of arithmetic units share a write port to a register file among the arithmetic units and a replacement path exists, Replacement flag for each input operand, consisting of multiple entries,
An instruction overtaking buffer that holds a ready flag and subsequent reference entry information and an entry valid flag, a destination field, and an L flag in each entry, and various information regarding instructions in the D stage data holding circuit in the instruction overtaking buffer. Entry registration means for registering information indicating the dependency relationship with the entry in the instruction overtaking buffer in which the instruction having the dependency relationship between the instruction of the entry and the operand is registered. A ray test setting means for setting the L flag in the registration entry of the instruction in the instruction overtaking buffer at the time of registering the instruction and resetting the L flag in the registration entry of the preceding instruction for writing the operation result in the same register as the instruction. And the instruction passing Registered in the instruction overtaking buffer, and an operand ready setting means for setting an operand ready flag in an entry in the instruction overtaking buffer for an instruction having a dependency relationship with the issued instruction when the instruction in the instruction overwriting buffer is issued. From the selection of issued instruction candidates from the “instruction group whose input operand is ready”, from the “instruction group that is known to overwrite the operation result by the subsequent instruction” registered in the instruction overtaking buffer Select an issue instruction based on the selection of candidate issue instructions and resource conflict check, and at the time of the selection, issue multiple instructions simultaneously within the range where resource conflict does not occur, If an instruction selected from among the “instructions that are known to overwrite the result” is actually issued, Without forcibly delay the subsequent instruction that references the calculated results and an issued instruction selection means for issuing (the time of the next cycle).

Here, the issue instruction selecting means in the pipeline processing apparatus of the present invention described above is based on the reference of the setting information (operand ready flag for each input operand) in each entry in the instruction overtaking buffer. First instruction selecting means for selecting an instruction that is a candidate for an issued instruction from an instruction group whose input operand is ready;
Based on the reference of the setting information (L flag etc.) in each entry in the instruction overtaking buffer, an instruction which is a candidate of the issuing instruction is selected from the instruction group in which it is known that the operation result is overwritten by the subsequent instruction. When a resource conflict check is performed between the second instruction selecting unit to be selected, the instruction selected by the first instruction selecting unit and the instruction selected by the second instruction selecting unit, and resource conflict does not occur. Both the instructions are issued at the same time, and if a resource conflict occurs, only the instruction selected by the first instruction selecting means is issued, and the instruction selected by the second instruction issuing selecting means is issued. When it is actually issued, it is provided with an issue instruction arbitration means for forcibly issuing a subsequent instruction referring to the operation result of the instruction without delay .

Further, the issue instruction arbitration means in the issue instruction selecting means in the pipeline processing apparatus of the present invention described above has the corresponding bit of the subsequent reference entry information for each input operand in each entry in the instruction overtaking buffer. An OR gate for each entry that generates a signal indicating an entry in which an instruction that refers to the operation result of the instruction registered in that entry is generated by generating a logical sum for each entry; A selector that selects the output signal of the OR gate for the entry in which the instruction selected by the instruction selection means is registered, and an entry information register that stores information based on the "signal indicating the entry" selected by the selector (FIG. The register B) in 2 and the instruction selected by the second instruction selecting means are actually issued. From the first instruction selecting means, the second instruction selecting means, the entry information register, and the instruction issuing information register. An issue instruction arbitration circuit for selecting an issue instruction based on information can be configured.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a pipeline processing apparatus according to an embodiment of the present invention. The gist of the present invention lies in the control content relating to the instruction overtaking buffer in the pipeline processing device. Therefore, FIG. 1 mainly shows components related to the instruction overtaking buffer (instruction overtaking buffer 10). The overall configuration of this pipeline processing device is shown in FIG.

Referring to FIG. 1, the pipeline processing apparatus according to the present embodiment includes an instruction overtaking buffer 10 having a plurality of (n, n is a positive integer of 2 or more) entries.
Entry registration means 20, issue instruction selection means 30, D
The stage data holding circuit 40, an operand ready setting means 50, a ray test (latest) setting means 60, and an I stage data holding circuit 70 are included. Although not shown in FIG. 1, the entry registration means 20, the issued instruction selection means 30, the operand ready set means 50, and the late test set means 60.
May include components within the instruction overtaking buffer 10. In addition, the same components may be shared between the respective means.

FIG. 2 is a diagram for explaining a detailed configuration (including peripheral configuration) and operation of the issue instruction selecting means 30.

The issuing instruction selecting means 30 is an AND gate 3.
01, 302, 304, 305, and 306, an exclusive OR gate 303, and a combinational logic circuit 30.
7, an OR gate 308, an instruction selecting unit A309,
The instruction selection means B310, the selector 311, the issued instruction arbitration circuit 312, the register A313, and the register B3.
And 14 are included. Here, the above 301
The constituent elements denoted by reference numerals ˜308 exist corresponding to each entry in the instruction overtaking buffer 10. Also,
The issued instruction arbitration means is configured by including the OR gate 308, the selector 311, the issued instruction arbitration circuit 312, the register A 313, and the register B 314 in each entry.

FIG. 3 is a diagram for explaining the detailed structure and operation of the ray test setting means 60.

The ray test setting means 60 comprises a comparator 601 and an AND gate 602. Here, the above-mentioned constituent elements exist corresponding to each entry in the instruction overtaking buffer 10. The new entry management unit 201 and the decoder 202, which are components of the entry registration unit 20, also correspond to the components of the ray test setting unit 60.

FIG. 4 shows the operand ready set means 50.
3 is a diagram for explaining a detailed configuration and operation of FIG.

The operand ready set means 50 selects the Y operand subsequent reference entry information 105 of each entry in the instruction overtaking buffer 10 as a selection target.
01 and a selector 502 that selects the Z operand subsequent reference entry information 106 of each entry as a selection target.

FIG. 5 is a diagram for explaining the detailed structure and operation of the entry registration means 20.

The entry registration means 20 includes a new entry management unit 201, a decoder 202, a comparator 203 and an AND gate group (AND gates 213 and 2) existing corresponding to each entry in the instruction overtaking buffer 10.
14 and 218). Although FIG. 5 shows only the components related to the Y operand, it goes without saying that similar components (such as a comparator for the Z operand) also exist for the Z operand.

FIG. 6 is a diagram showing the components of each entry in the instruction overtaking buffer 10 in detail.

The instruction overtaking buffer 10 has, for each entry, an entry valid flag (indicated by "V flag" in FIG. 6) 101 indicating that the entry is valid in a lighted state, and a destination field (in FIG. 6). Is indicated by "DESTINATION") 10
2 and the Y operand ready flag (in FIG. 6, "Y
-Rdy ") 103, a Z operand ready flag (indicated by" Z-rdy "in FIG. 6) 104,
Y operand subsequent reference entry information, which is information indicating an entry (entry in the instruction overtaking buffer 10) in which a subsequent instruction that refers to the result of the instruction registered in the entry as the Y operand (first input operand) is registered (Indicated by “Y-op subsequent reference entry information” in FIG. 6) 105 and an entry in which a subsequent instruction that refers to the result of the instruction registered in the entry as the Z operand (second input operand) is registered Z, which is information indicating (entry in the instruction overtaking buffer 10)
Operand subsequent reference entry information ("Z
-Op subsequent reference entry information ") 106, and L
(Latest) flag 130 and Y operand replacement flag (shown as “Y-replacement” in FIG. 6) 131
And the Z operand replacement flag (“Z
-Replacement) 132).

Here, the Y operand replacement flag 13
The 1 and Z operand replacement flags 132 hold the set signals of the Y operand ready flag 103 and the Z operand ready flag 104, respectively, for only one cycle. When issuance of the instruction is selected at the timing when the Y operand replacement flag 131 or the Z operand replacement flag 132 in the entry corresponding to the instruction is lit, the input operand of the instruction is the read data from the register file. It means that the data is supplied not by using the replacement path but by using the replacement path (the supplied data is the operation result of the preceding instruction).

FIG. 7 is a block diagram showing the overall configuration of the pipeline processing device according to the present embodiment, as described above. However, the entry registration means 20 shown in FIG.
Issuing instruction selecting means 30 and operand ready setting means 5
0, the ray test setting means 60, and the pipeline management block for integrally managing the pipeline processing device are not shown in FIG. 7 because the entire diagram becomes complicated. Further, the data path structure in the pipeline processing device of the present invention is not limited to that shown in FIG. 7, and data path structures as shown in the following a and b are also conceivable. a. The register file has a plurality of write ports, the first write port is shared (shared) between the first computing unit and the second computing unit, and the second write port is shared by the third computing unit and the fourth computing unit. A data path structure that is shared with an arithmetic unit, and each other write port is shared with another arithmetic unit group hereinafter. B. The register file has a plurality of write ports, the first write port is shared by the first arithmetic unit and the second arithmetic unit, and the second write port is the second arithmetic unit and the third arithmetic unit. Data path structure in which each other write port is shared by the operation unit group.

Here, a brief description will be given of the overall image of the pipeline processing apparatus shown in FIG. 7 (that is, the pipeline processing apparatus according to the present embodiment shown in FIG. 1).

The instruction read from the instruction buffer is once held in the D stage data holding circuit 40 and then registered in the instruction overtaking buffer 10.

The execution of the instruction registered in the instruction overtaking buffer 10 is started when the execution condition is satisfied. At this time, an instruction whose execution condition is not satisfied may be overtaken by a subsequent instruction.

The deletion of the instruction from the instruction overtaking buffer 10 is performed when the execution of the corresponding instruction is started.

The instruction whose execution has started is sent to the I stage data holding circuit 70, the contents of the entry of the register file indicated by the I stage data holding circuit 70 are read out, and the X stage is read based on the read out. It is sent to the data holding circuit.

If the instruction of the X stage is an operation instruction, it is input to the operation unit (operation unit FIX or operation unit LOG in FIG. 7), and if it is a memory access type instruction such as a load instruction, it is input to the address adder. It Here, “arithmetic unit FIX” in FIG. 7 means an arithmetic arithmetic unit for fixed point arithmetic, and “arithmetic unit LOG” means an arithmetic unit for logical operation. Needless to say, the contents of the arithmetic unit group in the pipeline processing device of the present invention are not limited to those shown in FIG. 7 (for example,
In a normal processor, an arithmetic unit for arithmetic operation is implemented by being divided into a fixed point addition system / floating point addition system / multiplication system / division system, etc.).

Further, if the X stage instruction is a memory access type instruction such as a load instruction, the read data of the cache memory is written in the register file, and if it is an arithmetic instruction, the operation result of the arithmetic unit is written in the register file. .

In the pipeline processing apparatus according to the present embodiment, not only the read data of the cache memory and the operation result of the arithmetic unit are written in the register file, but also the input of the X stage data holding circuit, the address adder and the arithmetic unit. Directly into the. As a path for this direct input, a replacement path (data replacement path) is provided. By this replacement path, the pipeline processing device shortens the number of cycles required to transfer data to the subsequent instruction that refers to the operation result of the preceding instruction, thereby improving the performance.

For example, in the instruction sequence of FIG. 9 referred to later,
The subsequent SUB instruction refers to the operation result S7 of the ADD instruction as the Y operand. Operation unit TAT (Turn
If the Around Time) is one cycle (T), the SUB instruction can be issued one cycle later than the ADD instruction. When the preceding ADD instruction reaches the W stage, the succeeding SUB instruction is on the X stage. W
By directly inputting the result of the preceding ADD instruction on the stage to the arithmetic unit, the succeeding SUB instruction can start execution without waiting for the operation result of the preceding ADD instruction to be written in the register file.

In FIG. 7, the following "a" to "c" correspond to the above "replacement path". a. Path from the data holding circuit on the output side of the arithmetic unit FIX and the arithmetic unit LOG to the selector on the input side of the arithmetic unit FIX and the arithmetic unit LOG b. Path from the data holding circuit on the output side of the arithmetic unit FIX and the arithmetic unit LOG to the X stage data holding circuit via the 2-input selector c. X from the data holding circuit on the output side of the cache memory
Path to stage data holding circuit

FIG. 8 is a diagram showing a format of an instruction handled by the pipeline processing device according to the present embodiment.

This instruction has an OP field indicating an instruction code, an X field indicating an X operand (operand of a storage destination of an operation result), and a Y operand (first operation
Input operand) and a Z field indicating the Z operand (second input operand of the operation).

9 and 10 are diagrams for explaining a specific operation of the pipeline processing device according to the present embodiment. That is, FIG. 9 is a diagram showing a specific example of the instruction sequence, and FIG. 10 is a diagram showing a time chart corresponding to the instruction sequence of FIG.

Next, the operation of the pipeline processing apparatus according to the present embodiment configured as described above (the operation centering on the operation relating to the control of the instruction overtaking buffer 10) will be described in detail. The instruction overtaking buffer 10
"Register various information about the instruction" in the entry in
This may be simply expressed as “registering an instruction”.

In the following, a specific operation of the pipeline processing apparatus according to the present embodiment will be described by appropriately using the instruction sequence shown in FIG. 9 as an example.

In the instruction string of FIG. 9, the Y operand of the instruction 2 (SUB instruction) refers to the operation result of the instruction 1 (ADD instruction). It is assumed that the instruction 1 is registered in the entry # 3 of the instruction overtaking buffer 10 and the instruction 2 is registered in the entry # 8 of the instruction overtaking buffer 10. Also,
Both the ADD of the instruction 1 and the SUB of the instruction 2 have the operation TAT of one cycle (T).

(1) Operation at the time of registering an instruction in the instruction overtaking buffer 10 First, FIG. 3, FIG. 5, FIG. 6, FIG. 9, and FIG. It will be described with reference to FIG.

(1-1) General operation at the time of instruction registration The entry registration means 20 is the D stage data holding circuit 4
Various information relating to the instruction in 0 (instruction of the format shown in FIG. 8) is registered in a predetermined entry in the instruction overtaking buffer 10 (setting of the L flag 130 is performed by the ray test setting means 60).

At the time of this registration, the entry registration means 2
0 indicates that the Y-operand subsequent reference entry information 105 and the Z-operand subsequent reference entry information 106 in the other entry are related to each other in order to indicate the dependency relationship regarding the operand with the instruction previously registered in the other entry. Set the information that indicates the dependency relationship. Note that this operation will be described in detail later in (1-2).

Further, at the time of this registration, the ray test setting means 60 sets the L flag 1 in the entry of the instruction to be registered.
30 is set and, if necessary, the L flag 130 related to the instruction previously registered in another entry is reset. The reset operation will be described in detail later in (1-3).

For example, the instructions shown in FIGS. 9 and 10 are registered in the instruction overtaking buffer 10 as follows.

The instruction 1 (ADD instruction) is fetched at time T0 in FIG. 10, passes through the D stage at time T1, and passes the instruction overtaking buffer 10 at time T2.
Entry # 3 of the above. Note that FIG.
The notation “R3” in the time chart indicates that the instruction 1 is registered in the entry # 3 of the instruction overtaking buffer 10.

At the time of registering the instruction 1 as described above, the new registration entry management unit 201, via the decoder 202,
Instruct to register instruction 1 in entry # 3. Based on this instruction, the X operand data of the D stage data holding circuit 40 is registered in the destination field 102 and the entry valid flag 101 is set for the entry # 3 in the instruction overtaking buffer 10. The above processing is performed by the entry registration means 20.
Corresponds to the processing of.

Further, the newly registered entry management unit 20 described above
Based on the instruction of 1, the L flag 130 of entry # 3 is set. This process is performed by the ray test setting means 60.
Corresponds to the processing of. Here, L flag 1 of an entry
The fact that 30 is in the "lit (set) state" means
It indicates that the instruction registered in the entry is the latest (last) instruction for updating the entry of the register file indicated by the destination field 102 in the entry. That is, by setting the above L flag 130 for the instruction 1, at the time T2, the instruction overtaking buffer 10 that updates the same register as the instruction 1 (the entry in the register file in which the operation result of the instruction 1 is stored) is updated. Within the command group in
It will be shown that the instruction 1 is the last instruction to update the register in the instruction sequence.

Instruction 2 (SUB instruction) is the same as instruction 1 (ADD
Instruction), one cycle later, fetched at time T1, reaches the D stage at time T2, and is registered in entry # 8 of the instruction overtaking buffer 10 at time T3. The notation “R8” in the time chart of FIG. 10 indicates that the instruction 2 is registered in the entry # 8 of the instruction overtaking buffer 10.

At the time of registering the instruction 2 as described above, the time T
In 2, the new registration entry management unit 201 gives an instruction to register the instruction 2 in the entry # 8 in the instruction overtaking buffer 10 via the decoder 202. Based on this instruction, the X operand data of the D stage data holding circuit 40 is the destination field 1 of the entry # 8.
02, and the entry valid flag 101 of entry # 8 is set. The above processing corresponds to the processing of the entry registration means 20.

Further, by the processing of the entry registration means 20 (processing of (1-2) described later), the Y operand subsequent reference entry in the entry # 3 is shown in order to show the dependency relationship between the operands of the instruction 1 and the instruction 2. The bit corresponding to entry # 8 in information 105 is set.

The newly registered entry management unit 20 described above
Based on the instruction of 1, the L flag 130 of the entry # 8 is set. This process is performed by the ray test setting means 60.
Corresponds to the processing of.

[0059]

(1-2) Operation by the entry registration means 20 for setting the information indicating the dependency relation between instructions Here, referring to FIG. 5, the instruction 1 and the instruction 2 at the time of registration of the instruction 2 are described. The operation related to the setting of the information (here, the Y operand subsequent reference entry information 105 for the instruction 2) indicating the inter-operand dependency relationship will be described.

Each comparator 203 (entry registering means 2) corresponding to each entry in the instruction overtaking buffer 10
0) is a D stage data holding circuit 4
The Y operand data in the instruction of 0 is compared with the contents of the destination field 102 of each entry, and if both are the same, TRUE is output.

At time T2 in FIG. 10, since S7 is registered in the destination field 102 of entry # 3, the contents of this destination field 102 (S7) and the Y operand data of the D stage data holding circuit 40 are stored. In comparison with S7, the output of the comparator 203 of entry # 3 becomes TRUE.

At time T2, the entry # 8 is instructed by the new registration entry management unit 21 as the registration entry of the instruction 2, and the input signal of the destination field 102 of the entry # 8 is TRUE. .

The AND gate 218 of the entry # 3 inputs the output signal of the comparator 203 of the entry # 3 and the input signal of the destination field 102 of the entry # 8, and is the logical product of these two signals. TRUE is output as an output signal.

At time T3, entry # 8 of instruction 2
At the same time as the registration to the entry # 3, the output of the AND gate 218 of the above entry # 3 sets the bit corresponding to the entry # 8 of the Y operand subsequent reference entry information 105 in the entry # 3.

As described above, at the same time that the instruction 2 is registered in the instruction overtaking buffer 10, the dependency relationship between the instruction 1 and the instruction 2 is detected, and the detected dependency relationship between them is the entry of the instruction 1 (entry # 3). ) In the Y operand is registered in the subsequent reference entry information 105.

(1-3) Operation of Resetting the L Flag 130 by the Ray Test Setting Means 60 Next, referring to FIG. 3, the operation of resetting the L flag 130 by the ray test setting means 60 at the time of registering an instruction will be described. .

As described above, the L flag 130 in a given entry is "the latest (last) instruction for which the instruction registered in the entry updates the entry in the register file indicated by the destination field 102 in the entry. Is a "lit (set) state".

When there is an instruction newly decoded and registered in the instruction overtaking buffer 10, the contents of the destination field 102 in the entry of the preceding instruction already registered in the instruction overtaking buffer 10 and the X field of the subsequent instruction Means that the entry of the register file that registers the operation result of the preceding instruction is overwritten by the subsequent instruction. In such a case, the L flag 130 of the entry of the preceding instruction is reset so that the mode of overwriting can be recognized when selecting an issuing instruction to be described later.

In order to realize the reset of the L flag 130 as described above, the ray test setting means 60 sets the destination of each entry in the instruction overtaking buffer 10 and the X operand data in the instruction of the D stage data holding circuit 40. The contents of the field 102 are compared with each comparator 601 for each entry. Then, the logical product of the comparison result and the entry valid flag 101 in each entry is ANDed with each entry.
A reset signal that is generated by the gate 602 and that outputs the output signal of each AND gate 602 to the L flag 130 in each entry (a signal that instructs the reset of the L flag 130 when the output of the AND gate 602 is TRUE). Figure 3
Refer to "R").

[0071]

(2) Operation at the time of issuing an instruction Second, the operation at the time of issuing an instruction registered in the instruction overtaking buffer 10 will be described with reference to FIGS.
This will be described with reference to 0.

(2-1) Operation of Operand Ready Set Means 50 First, the operation of the operand ready set means 50 when a certain instruction is issued will be described. Here, instruction 1
Y operand ready flag 1 of instruction 2 when issuing
The operation at the time of setting 03 will be described with reference to FIG.

At the time T7 in FIG. 10, when the instruction 1 is selected as the issue instruction by the control of the issue instruction selecting means 30 which will be described later, as shown in FIG. The registration entry of instruction 1) is designated.

The selector 501, which is a constituent element of the operand ready setting means 50, has the instruction overtaking buffer 10.
Information of the Y operand subsequent reference entry of each entry in the
The contents of 05 are entered. At time T7, the selector 501 selects the Y operand subsequent reference entry information 105 of the entry # 3 as an output because the issue entry selection signal indicates the entry # 3.

As described above, each bit of the Y operand subsequent reference entry information 105 in each entry corresponds to the entry in which the subsequent instruction that refers to the operation result of the registration instruction of its own entry is registered. Therefore, the selector 501 sets each bit of its own output as a set signal of the Y operand ready flag 103 of each corresponding entry in the instruction overtaking buffer 10.

At time T7, the "bit corresponding to entry # 8" in the output signal of selector 501 becomes TRUE, so that Y operand ready flag 103 of entry # 8 is turned on (set) at time T8. As a result, as will be described later, it becomes possible to select the instruction 2 which is the registration instruction of the entry # 8 as a candidate of the issuing instruction at time T8.

(2-2) Operation of Issued Instruction Selection Means 30 Next, the operation of the issued instruction selection means 30 will be described with reference to FIG. The operation of the issuing instruction selecting means 30 is
This embodiment corresponds to the central operation of the present invention and eventually the present invention.

The instruction selecting means A309 is as follows.
Select an instruction that is a candidate for an issue instruction. Note that this selection is similar to the selection of the issuing instruction according to the conventional technique.

The AND gate 302 corresponding to each entry in the instruction overtaking buffer 10 generates and outputs a logical product of the entry valid flag 101, the Y operand ready flag 103, and the Z operand ready flag 104 of each entry. AND gate 30 for each entry
The output of 2 is TRUE, which means that the issue condition of the instruction for each entry is satisfied, and the instruction can be a target of issue selection (candidate of issue instruction).

The instruction selecting means A309 inputs the output of the AND gate 302 of each of the above-mentioned entries and selects one instruction from the instructions satisfying the issuing conditions as a candidate for the issuing instruction. As a mode (criterion) of this selection, selection based on the order of registration in the instruction overtaking buffer 10, selection based on the order of entries in the instruction overtaking buffer 10, and the like can be considered.

On the other hand, the instruction selecting means B310 selects an instruction which is a candidate for an issuing instruction as follows. Note that this choice is unique to the present invention.

The instruction that can be selected by the instruction selecting means B310 is the next a in the entry for the instruction.
To satisfy the conditions shown in e.

A. Both the Y operand ready flag 103 and the Z operand ready flag 104 are lit. This condition is checked by AND gate 304.

B. Only one of the Y operand replacement flag 131 and the Z operand replacement flag 132 is lit. This condition is checked by the exclusive OR gate 303.

C. The L flag 130 is not lit. It should be noted that the fact that the L flag 130 is not lit indicates that the register file is overwritten by the subsequent instruction. This condition is checked by AND gate 301.

D. The entry valid flag 101 is lit. This condition is also checked by the AND gate 301.

E. Y operand subsequent reference entry information 1
05 and Z operand: The turned-on bit of the subsequent reference entry information 106 is at most 1 bit. This means that there is at most one instruction that refers to the operation result of the instruction of the entry. This condition is checked by the combinational logic circuit 307.

The AND gate 306 is the AND gate 30.
The logical product of the output of 1 and the output of the AND gate 305 (the logical product of the output of the exclusive OR gate 303 and the output of the AND gate 304) and the output of the combinational logic circuit 307 is output. The signal whose output is TRUE is a signal indicating that the above conditions a to e are satisfied (a signal indicating that the issuance condition of the instruction registered in the entry is satisfied).

The instruction selecting means B310 inputs the output of the AND gate 306 of each entry as described above, and selects one instruction from the instructions satisfying the issuing conditions as a candidate for the issuing instruction. As a mode (criterion) of this selection, selection based on the order of registration in the instruction overtaking buffer 10, selection based on the order of entries in the instruction overtaking buffer 10, and the like can be considered.

The OR gate 3 corresponding to each entry
08 generates a logical sum for each bit of the Y operand subsequent reference entry information 105 and the Z operand subsequent reference entry information 106 in each entry. That is, a signal indicating the entry in which the instruction that refers to the calculation result of the registration instruction of each entry is registered is generated.

The selector 311 ORs all entries.
The output signal of the gate 308 is inputted and the instruction selecting means B31
The output signal of the OR gate 308 of the entry corresponding to the instruction selected by 0 is selected and stored in the register B 314.

The issued instruction arbitration circuit 312 uses the following selection criteria to select the instruction (issued instruction candidate) selected by the instruction selecting means A309 and the instruction (issued instruction candidate) selected by the instruction selecting means B310. And the register B314 when the register A313 is lit.
Arbitration is performed with the instruction registered in the entry indicated by, the instruction to be actually issued to the arithmetic unit is determined from these instructions, and the instruction is issued. The setting of the register A313 will be described later.

When the register A 313 is on (set), the instruction of the entry indicated by the register B 314 is compulsorily issued as the first issuing instruction. At this time, the instruction selected by the instruction selecting unit A309 is canceled. Instruction selection means B3
The instruction selected by 10 is issued at the same time as the first issuance instruction as the second issuance instruction unless resource conflict with the first issuance instruction occurs. At this time, the register A313 is set. When the instruction selected by the instruction selecting unit B310 causes a resource conflict with the first issued instruction, the instruction (instruction selected by the instruction selecting unit B310) is canceled and is not issued.
At this time, the register A313 is reset.

On the other hand, when the register A313 is not lit, the instruction selected by the instruction selecting means A309 is issued as the first issuing instruction. Command selection means B
The instruction selected by 310 is issued at the same time as the first issuance instruction as the second issuance instruction unless resource conflict with the first issuance instruction occurs. At this time, the register A313 is set. When the instruction selected by the instruction selecting unit B310 causes a resource conflict with the first issued instruction, the instruction (instruction selected by the instruction selecting unit B310) is canceled and is not issued. At this time, the register A313 is reset.

As can be seen from the above operation, the register A313 indicates that the instruction selected by the instruction selecting means B310 has actually been issued in the "lighting (set) state".

Here, for the instruction selected by the instruction selecting means B310, the operation result is written to the register file based on the fact that the L bit 130 in the registered entry is not lit (reset). Back is not done. This is because the write port of the register file is used to write back the operation result of the first issue instruction issued at the same timing.

Therefore, when the instruction selected by the instruction selecting means B310 is actually issued as the second issuance instruction, the subsequent instruction which refers to the operation result of the second issuance instruction is the second issuance instruction. The operation result of is supplied as an input operand using the replacement path, and is always issued with a delay of one cycle of the second issuing instruction.
Such issuance is performed because the operation result of the second issuance instruction (instruction selected by the instruction selecting means B310) is not written in the register file, so that if such issuance is not performed, the subsequent instruction will be input again. This is because the operand cannot be obtained.

The operation of the pipeline processing apparatus (processor implementing the pipeline processing apparatus) according to this embodiment has been described above. Here, in order to specifically confirm the above operation, the operation according to the present embodiment regarding the instruction sequence in FIG. 11 will be described with reference to the time chart in FIG.

In FIG. 13, before time T0, as shown in FIG.
It is assumed that all the instructions of 1 are registered in the instruction overtaking buffer 10.

It is assumed that the LOAD instruction of the first instruction is issued at time T0, the SUB instruction of the sixth instruction is issued at time T1, and the ADD instruction of the second instruction is issued at time T2.

At time T3, both the OR instruction of the third instruction and the ADD instruction of the fourth instruction have the operand dependency resolved and ready to be issued. Further, the OR instruction of the third instruction and the ADD instruction of the fourth instruction use different types of arithmetic units. Furthermore, the ADD instruction of the fourth instruction is the S of the operation result by the SUB instruction of the subsequent sixth instruction.
Since it is known that 07 is overwritten on the instruction sequence, the operand is supplied to the ADD instruction of the fifth instruction that refers to the operation result of the fourth instruction using the replacement path around the arithmetic unit. If you can guarantee that it will be issued,
It is not always necessary to write back the operation result of the fourth instruction to the register file. In addition, at the time T3, one operand of each of the third instruction and the fourth instruction is supplied by the replacement path, so that the read port of the register file is left.

Based on the above points, the issuing instruction selecting means 3
With the control of 0, the OR of the third instruction is performed at time T3.
The instruction is actually issued as the first issuance instruction, and at the same time, the ADD instruction of the fourth instruction is actually issued as the second issuance instruction. Further, at time T4, the ADD instruction of the fifth instruction that refers to the X operand of the fourth instruction (ADD instruction) that is the second issued instruction at time T3 is forcibly issued.

12 is a time chart when the prior art is applied, and FIG. 13 is a time chart when the present embodiment (present invention) is applied.
It can be seen that when the present embodiment is applied, all the processes are completed quickly for one cycle. That is, it is possible to confirm the performance improvement of the present embodiment, and eventually the pipeline processing device of the present invention.

[0105]

As described above, according to the present invention,
By providing the issue instruction selection means and the like as described above, the instruction issue efficiency can be improved as compared with the conventional technique, and the performance of the invested arithmetic unit hardware resource can be more effectively drawn out. The effect is that the effective performance of the processor that realizes the pipeline processing device can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a pipeline processing device according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining a detailed configuration and operation of an issue instruction selection means in FIG.

FIG. 3 is a diagram for explaining a detailed configuration and operation of the ray test setting means in FIG.

FIG. 4 is a diagram for explaining a detailed configuration and operation of an operand ready setting means in FIG.

5 is a diagram for explaining the detailed configuration and operation of the entry registration means in FIG.

FIG. 6 is a diagram showing in detail the components of each entry in the instruction overtaking buffer in FIG.

7 is a block diagram showing an overall configuration of an example of the pipeline processing apparatus shown in FIG. 1 and a conventional pipeline processing apparatus.

8 is a diagram showing a format of an instruction handled by the pipeline processing device shown in FIG.

9 is a diagram (a diagram showing a specific example of an instruction sequence) for explaining a specific operation of the pipeline processing device according to the present embodiment shown in FIG. 1;

10 is a diagram (a diagram showing a time chart corresponding to the instruction sequence in FIG. 9) for explaining a specific operation of the pipeline processing device according to the present embodiment shown in FIG. 1;

FIG. 11 is a diagram showing an instruction sequence for explaining a specific operation of the pipeline processing device according to the present embodiment and the conventional pipeline processing device shown in FIG. 1;

FIG. 12 is a diagram showing a time chart for explaining a specific operation of the conventional pipeline processing apparatus.

FIG. 13 is a diagram showing a time chart for explaining a specific operation of the pipeline processing device according to the present embodiment shown in FIG. 1.

[Explanation of symbols]

10 instruction passing buffer 20 entry registration means 30 issued instruction selection means 40 D stage data holding circuit 50 operand ready setting means 60 ray test setting means 70 I stage data holding circuit 101 entry valid flag (V flag) 102 destination field (DESTI
(NATION) 103 Y operand ready flag (Y-rdy) 104 Z operand ready flag (Z-rdy) 105 Y operand Subsequent reference entry information (Y-op)
Subsequent reference entry information) 106 Z operand Subsequent reference entry information (Z-op
Subsequent reference entry information) 130 L flag 131 Y operand replacement flag (Y-replacement) 132 Z operand replacement flag (Z-replacement) 201 New registration entry management unit 202 Decoder 203, 601 Comparator 213, 214, 218, 301, 302, 304, 3
05, 306, 602 AND gate 303 Exclusive OR gate 307 Combinational logic circuit 308 OR gate 309 Instruction selecting means A 310 Instruction selecting means B 311, 501, 502 Selector 312 Issue instruction arbitration circuit 313 Register A 314 Register B

Claims (5)

(57) [Claims] 1. In a pipeline processing device in which a plurality of arithmetic units share a write port to a register file among the arithmetic units and a substitution path exists, a substitution flag for each input operand is composed of a plurality of entries. An instruction overtaking buffer that holds a ready flag and subsequent reference entry information and an entry valid flag, a destination field, and an L flag in each entry, and various information related to instructions in the D stage data holding circuit in the instruction overtaking buffer. Entry registration means for registering information indicating the dependency relationship in the entry in the instruction overtaking buffer in which an instruction having a dependency relationship between the instruction of the entry and the operand is registered, and the entry registration means When the order is registered, Raytest setting means for setting the L flag in the registration entry of the instruction in the overtaking buffer and resetting the L flag in the registration entry of the preceding instruction for writing the operation result in the same register as the instruction; and the instruction overtaking buffer. An operand ready set means for setting an operand ready flag in an entry in the instruction overtaking buffer for an instruction having a dependency relationship with the issued instruction, and an instruction ready register registered in the instruction overtaking buffer. Selection of issued instruction candidates from the "instruction group whose input operand is ready", from the "instruction group whose operation result is known to be overwritten by the subsequent instruction" registered in the instruction overtaking buffer Issuing based on selection of issuing instruction candidates and checking for resource conflicts Select an instruction, issue multiple instructions at the same time within the range where resource conflict does not occur, and select from the "instruction group where it is known that the operation result will be overwritten by subsequent instructions" possess the issued instruction selection means for issuing forcibly without delay subsequent instruction referencing calculation results of the instruction to when actually issued the instruction to be, the issued instruction selection means, the instruction in the overtaking buffer Setting information in each entry
Input operand is ready based on reference to
Select an instruction that is a candidate for an issued instruction from the instruction group.
1 instruction selecting means and setting information in each entry in the instruction overtaking buffer
Subsequent instruction overwrites the operation result based on
From the group of instructions that are known to
Second instruction selecting means for selecting an instruction, the instruction selected by the first instruction selecting means, and the first instruction selecting means.
Resource competition with the instruction selected by the instruction selecting means
If there is no resource conflict,
Issues both instructions at the same time, causing resource contention
The instruction selected by the first instruction selecting means,
Issue only the order and select by the second command issue selection means.
If the selected instruction is actually issued, the operation of that instruction
Issuing a forcible subsequent instruction that refers to the result without delay
A pipeline processing device comprising: a line instruction arbitration means . 2. An operation result of an instruction registered in each entry is generated by generating a logical sum of corresponding bits of subsequent reference entry information for each input operand in each entry in the instruction overtaking buffer. The output signal of the OR gate for each entry generating a signal indicating the entry in which the instruction to be referred to and the output signal of the OR gate for the entry in which the instruction selected by the second instruction selecting means are registered are selected. Selector, an entry information register for storing information based on the "signal indicating an entry" selected by the selector, and a lighting state indicating that the instruction selected by the second instruction selecting means is actually issued. The instruction issue information register shown, the first instruction selecting means, the second instruction selecting means, and the entry Broadcast registers and the issued instruction pipeline processor according to claim 1, characterized in that it has an arbitration unit and an issued instruction arbitration circuit for selecting the issued instruction based on the information from the instruction issue information register. 3. An instruction having a format having two input operands, a Y operand and a Z operand, is handled, and each entry has an entry valid flag, a destination field, an L flag, a Y operand replacement flag, a Y operand ready flag, and a Z operand. 3. The pipeline processing device according to claim 1, further comprising the instruction overtaking buffer holding a replacement flag, a Z operand ready flag, Y operand subsequent reference entry information, and Z operand subsequent reference entry information. 4. An instruction having a format having two input operands, a Y operand and a Z operand, is handled, and each entry has an entry valid flag, a destination field, an L flag, a Y operand replacement flag, a Y operand ready flag, and a Z operand. An instruction overtaking buffer holding a replacement flag, a Z operand ready flag, Y operand subsequent reference entry information, and Z operand subsequent reference entry information;
"Both the Y operand ready flag and the Z operand ready flag are lit", "Only one of the Y operand replacement flag and the Z operand replacement flag is lit", "L flag is lit""No","The entry valid flag is on", and "The illuminated bit in the Y operand subsequent reference entry information and the Z operand subsequent reference entry information is at most 1 bit". The second instruction for selecting a candidate instruction to be issued from among the instructions of the entry in the instruction overtaking buffer
3. The pipeline processing apparatus according to claim 1 or 2, further comprising: the issue instruction selecting means including the instruction selecting means. 5. A comparator for each entry that determines whether the contents of the X operand data in the D stage data holding circuit and the contents of the destination field in each entry in the instruction overtaking buffer are equal, When an instruction is registered in a certain entry in the instruction overtaking buffer, the logical product of the output of the comparator for each entry in the instruction overtaking buffer and the content of the entry valid flag in the relevant entry is output as a reset signal of the L flag. claim 1, characterized in that it comprises a ray test set means including an aND gate for each entry, claim 2, pipeline processor according to claim 3 or claim 4, wherein,.