JP3789633B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP3789633B2
JP3789633B2 JP05153898A JP5153898A JP3789633B2 JP 3789633 B2 JP3789633 B2 JP 3789633B2 JP 05153898 A JP05153898 A JP 05153898A JP 5153898 A JP5153898 A JP 5153898A JP 3789633 B2 JP3789633 B2 JP 3789633B2
Authority
JP
Japan
Prior art keywords
inner lead
semiconductor chip
semiconductor device
bonded
insulating tape
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP05153898A
Other languages
English (en)
Japanese (ja)
Other versions
JPH10289920A5 (2
JPH10289920A (ja
Inventor
紀幸 木村
Original Assignee
ユー・エム・シー・ジャパン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ユー・エム・シー・ジャパン株式会社 filed Critical ユー・エム・シー・ジャパン株式会社
Priority to JP05153898A priority Critical patent/JP3789633B2/ja
Publication of JPH10289920A publication Critical patent/JPH10289920A/ja
Publication of JPH10289920A5 publication Critical patent/JPH10289920A5/ja
Application granted granted Critical
Publication of JP3789633B2 publication Critical patent/JP3789633B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H10W72/9445—Top-view layouts, e.g. mirror arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP05153898A 1997-02-17 1998-02-17 半導体装置 Expired - Fee Related JP3789633B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP05153898A JP3789633B2 (ja) 1997-02-17 1998-02-17 半導体装置

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP4692097 1997-02-17
JP9-46920 1997-02-17
JP05153898A JP3789633B2 (ja) 1997-02-17 1998-02-17 半導体装置

Publications (3)

Publication Number Publication Date
JPH10289920A JPH10289920A (ja) 1998-10-27
JPH10289920A5 JPH10289920A5 (2) 2005-08-25
JP3789633B2 true JP3789633B2 (ja) 2006-06-28

Family

ID=26387072

Family Applications (1)

Application Number Title Priority Date Filing Date
JP05153898A Expired - Fee Related JP3789633B2 (ja) 1997-02-17 1998-02-17 半導体装置

Country Status (1)

Country Link
JP (1) JP3789633B2 (2)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100585585B1 (ko) * 1999-07-05 2006-06-07 삼성테크윈 주식회사 반도체 패키지
KR100561549B1 (ko) * 1999-10-07 2006-03-17 삼성전자주식회사 패드 온 칩형 반도체 패키지

Also Published As

Publication number Publication date
JPH10289920A (ja) 1998-10-27

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