JP4012496B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4012496B2 JP4012496B2 JP2003328911A JP2003328911A JP4012496B2 JP 4012496 B2 JP4012496 B2 JP 4012496B2 JP 2003328911 A JP2003328911 A JP 2003328911A JP 2003328911 A JP2003328911 A JP 2003328911A JP 4012496 B2 JP4012496 B2 JP 4012496B2
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
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- H—ELECTRICITY
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W40/00—Arrangements for thermal protection or thermal control
- H10W40/20—Arrangements for cooling
- H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
- H10W40/226—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area
- H10W40/228—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area the projecting parts being wire-shaped or pin-shaped
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- H—ELECTRICITY
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- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/01—Manufacture or treatment
- H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
- H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
- H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
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- H—ELECTRICITY
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
- H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
- H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/099—Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/013—Manufacture or treatment of die-attach connectors
- H10W72/01331—Manufacture or treatment of die-attach connectors using blanket deposition
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07331—Connecting techniques
- H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/241—Dispositions, e.g. layouts
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
- H10W72/351—Materials of die-attach connectors
- H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
- H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/941—Dispositions of bond pads
- H10W72/9413—Dispositions of bond pads on encapsulations
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
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- Microelectronics & Electronic Packaging (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
請求項2に記載の発明は、請求項1に記載の発明において、前記半導体構成体は、前記外部接続用電極としての柱状電極を有するものであることを特徴とするものである。
請求項3に記載の発明は、請求項2に記載の発明において、前記半導体構成体は放熱用柱状電極を有することを特徴とするものである。
請求項4に記載の発明は、請求項1に記載の発明において、前記中継放熱層は前記ベース板上に積層された金属箔からなることを特徴とするものである。
請求項5に記載の発明は、請求項1に記載の発明において、前記放熱層は前記最上層の上層再配線と同一の材料によって形成されていることを特徴とするものである。
請求項6に記載の発明は、請求項1に記載の発明において、前記最上層の上層再配線の接続パッド部上に半田ボールが設けられていることを特徴とするものである。
請求項2に記載の発明は、請求項1に記載の発明において、前記半導体構成体は、前記外部接続用電極としての柱状電極を有するものであることを特徴とするものである。
請求項3に記載の発明は、請求項2に記載の発明において、前記半導体構成体は放熱用柱状電極を有し、前記放熱層は前記放熱用柱状電極に接続されていることを特徴とするものである。
請求項4に記載の発明は、請求項3に記載の発明において、前記放熱層は前記最上層の上層絶縁膜の上面に設けられ、且つ、その少なくとも一部が前記最上層の上層絶縁膜上に設けられたオーバーコート膜の開口部を介して露出されていることを特徴とするものである。
請求項5に記載の発明は、請求項4に記載の発明において、前記放熱層は前記最上層の上層再配線と同一の材料によって形成されていることを特徴とするものである。
請求項6に記載の発明は、請求項1に記載の発明において、前記放熱層は前記ベース板の下面に設けられていることを特徴とするものである。
請求項7に記載の発明は、請求項6に記載の発明において、前記放熱層は、前記ベース板と前記半導体構成体の半導体基板との間に設けられた中継放熱層に、前記ベース板に設けられた貫通孔を介して接続されていることを特徴とするものである。
請求項8に記載の発明は、請求項7に記載の発明において、前記中継放熱層は前記ベース板上に積層された金属箔からなることを特徴とするものである。
請求項9に記載の発明は、請求項6に記載の発明において、前記放熱層は前記最上層の上層再配線と同一の材料によって形成されていることを特徴とするものである。
請求項10に記載の発明は、請求項1に記載の発明において、前記最上層の上層再配線の接続パッド部上に半田ボールが設けられていることを特徴とするものである。
図1はこの発明の参考実施形態1としての半導体装置の断面図を示す。この半導体装置は平面矩形形状のベース板1を備えている。ベース板1は、ガラス繊維、アラミド繊維、液晶繊維等にエポキシ系樹脂、ポリイミド系樹脂、BT(ビスマレイミド・トリアジン)樹脂、PPE(ポリフェニレンエーテル)等を含浸させたもの、あるいは、シリコン、ガラス、セラミックス、樹脂単体等の絶縁材料からなっている。
図16はこの発明の第1実施形態としての半導体装置の断面図を示す。この半導体装置において、図1に示す場合と異なる点は、放熱用下地金属層12、放熱用再配線13、放熱用柱状電極15、放熱用下地金属層22、放熱層23および開口部28を備えておらず、その代わりに、ベース板1の下面中央部に放熱用下地金属層51および放熱層52が設けられ、放熱層52を含む放熱用下地金属層51が、ベース板1と半導体構成体2のシリコン基板4との間に設けられた中継放熱層53に、ベース板1に設けられた貫通孔54を介して接続された点である。
図17はこの発明の第2実施形態としての半導体装置の断面図を示す。この半導体装置では、図1に示す放熱層23等および図16に示す放熱層52等を備えている。したがって、この半導体装置では、放熱性をより一層良くすることができる。
上記参考実施形態2では、図1に示すように、上層絶縁膜18上に上層再配線20を1層だけ形成した場合について説明したが、これに限らず、2層以上としてもよく、例えば、図18に示すこの発明の第4実施形態のように、2層としてもよい。すなわち、半導体構成体2および絶縁層17の上面にはビルドアップ材等からなる第1の上層絶縁膜61が設けられている。
なお、上記各実施形態において、半導体構成体2は、外部接続用電極として、再配線11の接続パッド部上に設けられた柱状電極14を有するものとしたが、これに限定されるものではない。例えば、半導体構成体2は、外部接続用電極としての接続パッド部を有する再配線11を有するものであってもよく、また、外部接続用電極としての接続パッド5を有するものであってもよく、さらに、外部接続用電極として、接続パッド5上に設けられた柱状電極を有するものであってもよい。
2 半導体構成体
3 接着層
4 シリコン基板
5 接続パッド
11 再配線
13 放熱用再配線
14 柱状電極
15 放熱用柱状電極
16 封止膜
17 絶縁層
18 上層絶縁膜
20 上層再配線
23 放熱層
25 オーバーコート膜
27 半田ボール
28 開口部
Claims (6)
- ベース板と、前記ベース板上に設けられ、且つ、半導体基板および該半導体基板の上面側に設けられた複数の外部接続用電極を有する半導体構成体と、前記半導体構成体上およびその周囲における前記ベース板上に設けられた絶縁層と、前記絶縁層上に前記半導体構成体の外部接続用電極に接続されて設けられ、且つ、接続パッド部を有する少なくとも1層の上層再配線と、前記上層再配線のうちの最上層の上層再配線の接続パッド部を除く部分を覆う上層絶縁膜と、前記ベース板と前記半導体構成体の半導体基板との間に設けられた中継放熱層と、前記ベース板の下面に形成され、前記ベース板に設けられた貫通孔を介して前記中継放熱層に接続された放熱層とを備えていることを特徴とする半導体装置。
- 請求項1に記載の発明において、前記半導体構成体は、前記外部接続用電極としての柱状電極を有するものであることを特徴とする半導体装置。
- 請求項2に記載の発明において、前記半導体構成体は放熱用柱状電極を有することを特徴とする半導体装置。
- 請求項1に記載の発明において、前記中継放熱層は前記ベース板上に積層された金属箔からなることを特徴とする半導体装置。
- 請求項1に記載の発明において、前記放熱層は前記最上層の上層再配線と同一の材料によって形成されていることを特徴とする半導体装置。
- 請求項1に記載の発明において、前記最上層の上層再配線の接続パッド部上に半田ボールが設けられていることを特徴とする半導体装置。
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003328911A JP4012496B2 (ja) | 2003-09-19 | 2003-09-19 | 半導体装置 |
| US10/940,232 US7042081B2 (en) | 2003-09-19 | 2004-09-13 | Semiconductor device having heat dissipation layer |
| CNB2004101047355A CN1322566C (zh) | 2003-09-19 | 2004-09-16 | 半导体装置 |
| KR1020040074047A KR100637307B1 (ko) | 2003-09-19 | 2004-09-16 | 반도체장치 |
| TW093128125A TWI248148B (en) | 2003-09-19 | 2004-09-17 | Semiconductor device having heat dissipation layer cross-reference to related applications |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003328911A JP4012496B2 (ja) | 2003-09-19 | 2003-09-19 | 半導体装置 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007012146A Division JP4316624B2 (ja) | 2007-01-23 | 2007-01-23 | 半導体装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2005093942A JP2005093942A (ja) | 2005-04-07 |
| JP4012496B2 true JP4012496B2 (ja) | 2007-11-21 |
Family
ID=34308837
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2003328911A Expired - Fee Related JP4012496B2 (ja) | 2003-09-19 | 2003-09-19 | 半導体装置 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US7042081B2 (ja) |
| JP (1) | JP4012496B2 (ja) |
| KR (1) | KR100637307B1 (ja) |
| CN (1) | CN1322566C (ja) |
Families Citing this family (65)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3979404B2 (ja) * | 2004-06-30 | 2007-09-19 | カシオ計算機株式会社 | 半導体装置 |
| JP3945483B2 (ja) | 2004-01-27 | 2007-07-18 | カシオ計算機株式会社 | 半導体装置の製造方法 |
| JP4093186B2 (ja) * | 2004-01-27 | 2008-06-04 | カシオ計算機株式会社 | 半導体装置の製造方法 |
| DE102004018475A1 (de) * | 2004-04-16 | 2005-11-10 | eupec Europäische Gesellschaft für Leistungshalbleiter mbH | Leistungshalbleiteranordnung |
| JP2006173232A (ja) * | 2004-12-14 | 2006-06-29 | Casio Comput Co Ltd | 半導体装置およびその製造方法 |
| JP4725178B2 (ja) * | 2005-04-28 | 2011-07-13 | カシオ計算機株式会社 | 半導体装置およびその製造方法 |
| US7468545B2 (en) * | 2005-05-06 | 2008-12-23 | Megica Corporation | Post passivation structure for a semiconductor device and packaging process for same |
| US7582556B2 (en) | 2005-06-24 | 2009-09-01 | Megica Corporation | Circuitry component and method for forming the same |
| JP4605378B2 (ja) * | 2005-07-13 | 2011-01-05 | セイコーエプソン株式会社 | 半導体装置 |
| JP4289335B2 (ja) * | 2005-08-10 | 2009-07-01 | セイコーエプソン株式会社 | 電子部品、回路基板及び電子機器 |
| JP4817796B2 (ja) * | 2005-10-18 | 2011-11-16 | Okiセミコンダクタ株式会社 | 半導体装置及びその製造方法 |
| JP2007294652A (ja) * | 2006-04-25 | 2007-11-08 | Matsushita Electric Ind Co Ltd | 半導体集積回路装置及びその製造方法 |
| US9305859B2 (en) * | 2006-05-02 | 2016-04-05 | Advanced Analogic Technologies Incorporated | Integrated circuit die with low thermal resistance |
| JP4193897B2 (ja) * | 2006-05-19 | 2008-12-10 | カシオ計算機株式会社 | 半導体装置およびその製造方法 |
| US20080116564A1 (en) * | 2006-11-21 | 2008-05-22 | Advanced Chip Engineering Technology Inc. | Wafer level package with die receiving cavity and method of the same |
| US7911044B2 (en) * | 2006-12-29 | 2011-03-22 | Advanced Chip Engineering Technology Inc. | RF module package for releasing stress |
| US20080157342A1 (en) * | 2007-01-03 | 2008-07-03 | Advanced Chip Engineering Technology Inc. | Package with a marking structure and method of the same |
| US20080157316A1 (en) * | 2007-01-03 | 2008-07-03 | Advanced Chip Engineering Technology Inc. | Multi-chips package and method of forming the same |
| TW200901409A (en) * | 2007-06-22 | 2009-01-01 | Nan Ya Printed Circuit Board Corp | Packaging substrate with embedded chip and buried heatsink |
| US7863090B2 (en) * | 2007-06-25 | 2011-01-04 | Epic Technologies, Inc. | Packaged electronic modules and fabrication methods thereof implementing a cell phone or other electronic system |
| JP2009016818A (ja) * | 2007-07-04 | 2009-01-22 | Samsung Electro-Mechanics Co Ltd | 多層印刷回路基板及びその製造方法 |
| US7915728B2 (en) * | 2007-07-12 | 2011-03-29 | Vishay General Semiconductor Llc | Subassembly that includes a power semiconductor die and a heat sink having an exposed surface portion thereof |
| US8587124B2 (en) | 2007-09-21 | 2013-11-19 | Teramikros, Inc. | Semiconductor device having low dielectric insulating film and manufacturing method of the same |
| US20090079072A1 (en) * | 2007-09-21 | 2009-03-26 | Casio Computer Co., Ltd. | Semiconductor device having low dielectric insulating film and manufacturing method of the same |
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| JPH0756887B2 (ja) * | 1988-04-04 | 1995-06-14 | 株式会社日立製作所 | 半導体パッケージ及びそれを用いたコンピュータ |
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| JP3664432B2 (ja) | 2000-05-18 | 2005-06-29 | カシオ計算機株式会社 | 半導体装置およびその製造方法 |
| JP3520039B2 (ja) * | 2000-10-05 | 2004-04-19 | 三洋電機株式会社 | 半導体装置および半導体モジュール |
| TW577160B (en) * | 2002-02-04 | 2004-02-21 | Casio Computer Co Ltd | Semiconductor device and manufacturing method thereof |
| US6770971B2 (en) * | 2002-06-14 | 2004-08-03 | Casio Computer Co., Ltd. | Semiconductor device and method of fabricating the same |
| JP2003142525A (ja) * | 2002-11-11 | 2003-05-16 | Toshiba Corp | 半導体装置 |
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| CN1619787A (zh) | 2005-05-25 |
| KR20050028791A (ko) | 2005-03-23 |
| KR100637307B1 (ko) | 2006-10-25 |
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