JP4094724B2 - ソフトウェアをデバッグする際に例外を識別するための装置および方法 - Google Patents

ソフトウェアをデバッグする際に例外を識別するための装置および方法 Download PDF

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JP4094724B2
JP4094724B2 JP13325698A JP13325698A JP4094724B2 JP 4094724 B2 JP4094724 B2 JP 4094724B2 JP 13325698 A JP13325698 A JP 13325698A JP 13325698 A JP13325698 A JP 13325698A JP 4094724 B2 JP4094724 B2 JP 4094724B2
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instruction
breakpoint
signal
data
processor core
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JPH11110254A5 (2
JPH11110254A (ja
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アンソニー セガーズ サイモン
ローガン ハロッド ピーター
ジョン マーリット アンドリュー
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エイアールエム リミテッド
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software
    • G06F11/362—Debugging of software
    • G06F11/3648—Debugging of software using additional hardware
    • G06F11/3656—Debugging of software using additional hardware using a specific debug interface

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
JP13325698A 1997-09-09 1998-05-15 ソフトウェアをデバッグする際に例外を識別するための装置および方法 Expired - Lifetime JP4094724B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9719173.8 1997-09-09
GB9719173A GB2329049B (en) 1997-09-09 1997-09-09 Apparatus and method for identifying exceptions when debugging software

Publications (3)

Publication Number Publication Date
JPH11110254A JPH11110254A (ja) 1999-04-23
JPH11110254A5 JPH11110254A5 (2) 2005-07-28
JP4094724B2 true JP4094724B2 (ja) 2008-06-04

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JP13325698A Expired - Lifetime JP4094724B2 (ja) 1997-09-09 1998-05-15 ソフトウェアをデバッグする際に例外を識別するための装置および方法

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US (1) US6052774A (2)
JP (1) JP4094724B2 (2)
GB (1) GB2329049B (2)

Cited By (1)

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KR102181715B1 (ko) * 2019-08-01 2020-11-23 한상교 마이크로프로세서용 미정의된 명령어 예외에 대한 처리 방법 및 상기 마이크로프로세서용 미정의된 명령어 예외에 대한 처리 방법이 적용된 마이크로프로세서

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US6321331B1 (en) * 1998-04-22 2001-11-20 Transwitch Corporation Real time debugger interface for embedded systems
JP2000099366A (ja) * 1998-09-21 2000-04-07 Fujitsu Ltd 演算処理装置および演算処理装置のデバッグ方法
US6560712B1 (en) * 1999-11-16 2003-05-06 Motorola, Inc. Bus arbitration in low power system
US6732311B1 (en) * 2000-05-04 2004-05-04 Agere Systems Inc. On-chip debugger
US7039834B1 (en) * 2000-12-21 2006-05-02 Unisys Corporation High speed processor interconnect tracing compaction using selectable triggers
US7287147B1 (en) 2000-12-29 2007-10-23 Mips Technologies, Inc. Configurable co-processor interface
US7237090B1 (en) 2000-12-29 2007-06-26 Mips Technologies, Inc. Configurable out-of-order data transfer in a coprocessor interface
JP4451010B2 (ja) * 2001-04-09 2010-04-14 三菱電機株式会社 プログラマブルコントローラ
US7178133B1 (en) 2001-04-30 2007-02-13 Mips Technologies, Inc. Trace control based on a characteristic of a processor's operating state
US7185234B1 (en) 2001-04-30 2007-02-27 Mips Technologies, Inc. Trace control from hardware and software
US7124072B1 (en) 2001-04-30 2006-10-17 Mips Technologies, Inc. Program counter and data tracing from a multi-issue processor
US7069544B1 (en) 2001-04-30 2006-06-27 Mips Technologies, Inc. Dynamic selection of a compression algorithm for trace data
US7134116B1 (en) 2001-04-30 2006-11-07 Mips Technologies, Inc. External trace synchronization via periodic sampling
US7168066B1 (en) 2001-04-30 2007-01-23 Mips Technologies, Inc. Tracing out-of order load data
US7181728B1 (en) 2001-04-30 2007-02-20 Mips Technologies, Inc. User controlled trace records
US7065675B1 (en) 2001-05-08 2006-06-20 Mips Technologies, Inc. System and method for speeding up EJTAG block data transfers
US7043668B1 (en) 2001-06-29 2006-05-09 Mips Technologies, Inc. Optimized external trace formats
US7231551B1 (en) 2001-06-29 2007-06-12 Mips Technologies, Inc. Distributed tap controller
US7296259B2 (en) * 2002-09-11 2007-11-13 Agere Systems Inc. Processor system with cache-based software breakpoints
DE60222187D1 (de) * 2002-11-14 2007-10-11 St Microelectronics Sa Überwachungschaltung eines mikroprozessors und analysewerkzeug und seine ein- und ausgänge
WO2004046929A1 (fr) * 2002-11-14 2004-06-03 Stmicroelectronics S.A. Transmission d'un message numerique entre un circuit de surveillance d'un microprocesseur et un outil d'analyse
US7225098B2 (en) * 2002-11-21 2007-05-29 Stmicroelectronics S.A. Monitoring device with optimized buffer
US7159101B1 (en) 2003-05-28 2007-01-02 Mips Technologies, Inc. System and method to trace high performance multi-issue processors
US7237149B2 (en) * 2005-02-25 2007-06-26 Freescale Semiconductor, Inc. Method and apparatus for qualifying debug operation using source information
US7447874B1 (en) * 2005-10-18 2008-11-04 Qlogic, Corporation Method and system for designing a flexible hardware state machine
US8010774B2 (en) * 2006-03-13 2011-08-30 Arm Limited Breakpointing on register access events or I/O port access events
US7865704B2 (en) * 2006-03-29 2011-01-04 Freescale Semiconductor, Inc. Selective instruction breakpoint generation based on a count of instruction source events
US20080059339A1 (en) * 2006-08-31 2008-03-06 Gualandri J Joseph Systems and methods for identifying attachments
US7783867B2 (en) * 2007-02-01 2010-08-24 International Business Machines Corporation Controlling instruction execution in a processing environment
US9639451B2 (en) 2010-01-25 2017-05-02 Nxp Usa, Inc. Debugger system, method and computer program product for utilizing hardware breakpoints for debugging instructions
US9288161B2 (en) * 2011-12-05 2016-03-15 International Business Machines Corporation Verifying the functionality of an integrated circuit
GB2530050B (en) * 2014-09-10 2021-07-21 Advanced Risc Mach Ltd Debugging in a data processing apparatus
JP7202225B2 (ja) * 2019-03-12 2023-01-11 ローム株式会社 半導体装置及びデバッグシステム
US12524371B2 (en) * 2024-02-22 2026-01-13 High Tech Technology Limited Enhanced Harvard architecture reduced instruction set computer (RISC) with debug mode access of instruction memory within a unified memory space

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US5390305A (en) * 1991-03-29 1995-02-14 Kabushiki Kaisha Toshiba Information processing apparatus capable of executing exception at high speed
US5745770A (en) * 1993-12-27 1998-04-28 Intel Corporation Method and apparatus for servicing simultaneous I/O trap and debug traps in a microprocessor
US5537559A (en) * 1994-02-08 1996-07-16 Meridian Semiconductor, Inc. Exception handling circuit and method
KR100403405B1 (ko) * 1995-05-26 2004-03-30 내셔널 세미콘덕터 코포레이션 분산형버스액세스및제어조정에따라다수개의내부신호버스를공유하는다수개의회로기능요소를갖는집적회로
US5680620A (en) * 1995-06-30 1997-10-21 Dell Usa, L.P. System and method for detecting access to a peripheral device using a debug register

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102181715B1 (ko) * 2019-08-01 2020-11-23 한상교 마이크로프로세서용 미정의된 명령어 예외에 대한 처리 방법 및 상기 마이크로프로세서용 미정의된 명령어 예외에 대한 처리 방법이 적용된 마이크로프로세서

Also Published As

Publication number Publication date
GB2329049A (en) 1999-03-10
US6052774A (en) 2000-04-18
GB9719173D0 (en) 1997-11-12
GB2329049B (en) 2002-09-11
JPH11110254A (ja) 1999-04-23

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