JP4852261B2 - シリコン化合物の形成方法 - Google Patents
シリコン化合物の形成方法 Download PDFInfo
- Publication number
- JP4852261B2 JP4852261B2 JP2005144616A JP2005144616A JP4852261B2 JP 4852261 B2 JP4852261 B2 JP 4852261B2 JP 2005144616 A JP2005144616 A JP 2005144616A JP 2005144616 A JP2005144616 A JP 2005144616A JP 4852261 B2 JP4852261 B2 JP 4852261B2
- Authority
- JP
- Japan
- Prior art keywords
- interface
- compound
- substrate
- forming
- etched
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/448—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for generating reactive gas streams, e.g. by evaporation or sublimation of precursor materials
- C23C16/4488—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for generating reactive gas streams, e.g. by evaporation or sublimation of precursor materials by in situ generation of reactive gas by chemical or electrochemical reaction
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10P95/50—Alloying conductive materials with semiconductor bodies
-
- C—CHEMISTRY; METALLURGY
- C01—INORGANIC CHEMISTRY
- C01B—NON-METALLIC ELEMENTS; COMPOUNDS THEREOF; METALLOIDS OR COMPOUNDS THEREOF NOT COVERED BY SUBCLASS C01C
- C01B33/00—Silicon; Compounds thereof
- C01B33/06—Metal silicides
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/32—Carbides
- C23C16/325—Silicon carbide
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/42—Silicides
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
- H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
- H10D64/0112—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
- H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
- H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H10D64/01314—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of Ge, C or of compounds of Si, Ge or C contacting the insulator
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
- H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
- H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H10D64/01318—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN
- H10D64/0132—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN the conductor being a metallic silicide
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F10/00—Individual photovoltaic cells, e.g. solar cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F77/00—Constructional details of devices covered by this subclass
- H10F77/10—Semiconductor bodies
- H10F77/12—Active materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P10/00—Bonding of wafers, substrates or parts of devices
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Landscapes
- Chemical & Material Sciences (AREA)
- Organic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Mechanical Engineering (AREA)
- Engineering & Computer Science (AREA)
- Materials Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Metallurgy (AREA)
- Inorganic Chemistry (AREA)
- Electrochemistry (AREA)
- Electrodes Of Semiconductors (AREA)
- Chemical Vapour Deposition (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
本実施例は、図4に示すMOSトランジスタのソース電極01、ドレン電極02にNiSiを形成する場合である。この場合の基板3は、Si基板上にSiO2膜を形成するとともに、ソース電極01及びドレン電極02を形成する部分のSiO2膜が除去された状態でSi界面が露出した状態となっている。かかる基板3を図1に示す装置のチャンバ1内の支持台2上に載置する。このとき、被エッチング部材11はNiで形成しておく。
Cl*ラジカルにより次のような被エッチング部材11のエッチング反応が進行する。
Ni(s)+Cl*→NiCl(g) ・・・・(1)
このようにガスプラズマ23が発生することにより被エッチング部材11を加熱する(例えば、300℃〜700℃)一方、温度制御手段6により基板3の温度を被エッチング部材11の温度よりも低い温度(例えば、100℃〜300℃)に保持しておく。
上記温度条件の下で下記のような前駆体24の吸着反応が進行する。
NiCl(g)→NiCl(ad) ・・・・(2)
次のような塩素ラジカルCl*による還元作用でNiSiが形成される。
NiCl(ad)+Cl* +Si(s)→NiSi(s)+Cl2↑・・・・(3)
本実施例は、図4に示すMOSトランジスタのゲート電極03を形成する場合である。この場合の基板3は、ゲート電極03を形成するポリシリコン等のSi界面を露出した状態でこの基板3を図1に示す装置のチャンバ1内の支持台2上に載置する。このとき、被エッチング部材11はNiで形成しておく。
本実施例は、図4に示すMOSトランジスタのゲートスタックを形成する場合である。この場合の基板3のn型シリコン基板04上にゲート絶縁膜05であるSiO2膜を形成し、その上に上述の実施例と同様の方法によりNi膜を生成することで、SiO2のSi成分の一部が、Niと反応してゲート電極03にNiSi膜が形成される。
上記第1及び第2の実施例を組み合わせればMOSトランジスタの全ての電極01,02,03を形成することができる。
同様に、上記第1及び第3の実施例を組み合わせればMOSトランジスタの全ての電極01,02,03を形成するとともにゲート絶縁膜05であるSiO2を含む全てのゲート構造を形成することができる。
太陽電池の材料として期待されているものにFeSiがあるが、このFeSiを利用して太陽電池を作成するためには、太陽電池のp型シリコン層及びn型シリコン層をFeSiで形成する必要がある。この場合にも本発明を適用でき、優れた効果を奏する。具体的には、図1に示す被エッチング部材11をFeとし、基板3のp型シリコン層又はn型シリコン層上にFe膜を形成すれば良い。このことによりFeとSiとが反応し、p型及びn型のFeSi層を形成して太陽電池のp型層及びn型層を形成することができる。
最近、MOSトランジスタのソース電極01及びドレン電極02として従来のSiGeの代わりにSiCを使用することでチャネルに引っ張り歪を導入し、nMOSトランジスタの移動速度を高められることが分かった。この場合のSiCの形成に本発明を適用しても前述の如き優れた効果を得る。具体的には、図1に示す被エッチング部材11をグラファイトで形成して第1の実施例と同様の工程を経れば良い。
2) チャンバ1内に連通する筒状の通路を流通するハロゲンガスにマイクロ波を供給してこのハロゲンガスをプラズマ化する。
3) チャンバ1内に連通する筒状の通路を流通するハロゲンガスを加熱して熱的解離する。
4) チャンバ1内に連通する筒状の通路を流通するハロゲンガスに電磁波又は電子線を供給してこのハロゲンガスを解離させる。
5) チャンバ1内に連通する筒状の通路を流通するハロゲンガスを、触媒作用により解離させる触媒金属に接触させる。
3 基板
8 プラズマアンテナ
11 被エッチング部材
21 作用ガス
Claims (3)
- Si界面とSiO2膜とが並存する基板を真空容器であるチャンバの内部に配置する工程と、
NiとSiとの化合物を前記Si界面上に形成する工程とを有し、
前記化合物を形成する工程は、
前記チャンバの内部に配設するとともに前記Niで形成した被エッチング部材を、300℃〜700℃に保持した状態でハロゲンガスのラジカルを作用させることにより前記Niとハロゲンとの化合物である前駆体のガスを形成する一方、
前記基板の温度を前記被エッチング部材の温度よりも低い温度100℃〜300℃に保持することにより前記前駆体を前記基板のSi界面に吸着させると共に、
前記Si界面に吸着させた前記前躯体に前記300℃〜700℃であるハロゲンガスのラジカルを作用させて前記Si界面に吸着させた前躯体を還元して前記Si界面上に前記Niからなる膜を形成すると共に、前記ハロゲンガスのラジカルにより前記Niからなる膜と前記Si界面のSiとを反応させて前記Si界面上に前記NiとSiとの化合物であるNiSiを形成することを特徴とするシリコン化合物の形成方法。 - 請求項1において、
前記前駆体のSiO2領域とSi領域に対する前記Ni化合物の生成時間の差であるインキュベーションタイムの間に前記化合物の形成を完了することにより前記基板の前記Si界面のみに前記化合物であるNiSiを形成することを特徴とするシリコン化合物の形成方法。 - 請求項1または請求項2において、
前記Si界面に形成するNiSiでMOSトランジスタの電極を形成することを特徴とするシリコン化合物の形成方法。
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005144616A JP4852261B2 (ja) | 2005-05-17 | 2005-05-17 | シリコン化合物の形成方法 |
| US11/919,484 US7776751B2 (en) | 2005-05-17 | 2006-05-17 | Process for producing silicon compound |
| KR1020077029289A KR100940824B1 (ko) | 2005-05-17 | 2006-05-17 | 실리콘 화합물의 형성방법 |
| EP06746497A EP1884987A4 (en) | 2005-05-17 | 2006-05-17 | PROCESS FOR PRODUCING A SILICON COMPOUND |
| PCT/JP2006/309794 WO2006123673A1 (ja) | 2005-05-17 | 2006-05-17 | シリコン化合物の形成方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005144616A JP4852261B2 (ja) | 2005-05-17 | 2005-05-17 | シリコン化合物の形成方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2006324357A JP2006324357A (ja) | 2006-11-30 |
| JP4852261B2 true JP4852261B2 (ja) | 2012-01-11 |
Family
ID=37431245
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005144616A Expired - Fee Related JP4852261B2 (ja) | 2005-05-17 | 2005-05-17 | シリコン化合物の形成方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US7776751B2 (ja) |
| EP (1) | EP1884987A4 (ja) |
| JP (1) | JP4852261B2 (ja) |
| KR (1) | KR100940824B1 (ja) |
| WO (1) | WO2006123673A1 (ja) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2008065908A1 (ja) * | 2006-11-29 | 2010-03-04 | キヤノンアネルバ株式会社 | 金属iv族元素化合物膜の形成方法及び半導体装置の製造方法 |
| US8617411B2 (en) * | 2011-07-20 | 2013-12-31 | Lam Research Corporation | Methods and apparatus for atomic layer etching |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3194256B2 (ja) | 1991-11-14 | 2001-07-30 | 富士通株式会社 | 膜成長方法と膜成長装置 |
| JP3084497B2 (ja) * | 1992-03-25 | 2000-09-04 | 東京エレクトロン株式会社 | SiO2膜のエッチング方法 |
| JPH06318563A (ja) * | 1993-05-10 | 1994-11-15 | Toshiba Corp | 半導体装置及びその製造方法 |
| JPH0794446A (ja) * | 1993-09-20 | 1995-04-07 | Hitachi Ltd | 半導体装置の製造方法 |
| JPH0959013A (ja) | 1995-08-22 | 1997-03-04 | Mitsubishi Heavy Ind Ltd | シリサイド膜の作製方法 |
| JP2001024194A (ja) | 1999-05-06 | 2001-01-26 | Toshiba Corp | 半導体装置の製造方法及び半導体装置 |
| JP2001064099A (ja) | 1999-08-26 | 2001-03-13 | Matsushita Electronics Industry Corp | 薄膜の形成方法 |
| JP3727878B2 (ja) * | 2001-11-14 | 2005-12-21 | 三菱重工業株式会社 | 金属膜作製装置 |
| JP3716235B2 (ja) | 2002-03-08 | 2005-11-16 | 三菱重工業株式会社 | 金属膜作製方法及び金属膜作製装置 |
| DE60329292D1 (de) * | 2002-03-08 | 2009-10-29 | Canon Anelva Corp | Verfahren und Vorrichtung zum Herstellen von Metall-Schichten |
| JP3733424B2 (ja) * | 2002-07-08 | 2006-01-11 | 国立大学法人名古屋大学 | ニッケルシリコン系薄膜、ニッケルシリコン系多層膜構造及びニッケルシリコン系薄膜の作製方法 |
| JP3782763B2 (ja) * | 2002-08-23 | 2006-06-07 | 三菱重工業株式会社 | 金属膜作製方法及び金属膜作製装置 |
| KR100446309B1 (ko) | 2002-11-14 | 2004-09-01 | 삼성전자주식회사 | L자형 스페이서를 채용한 반도체 소자의 제조 방법 |
| JP3840198B2 (ja) * | 2003-04-28 | 2006-11-01 | 株式会社東芝 | 半導体装置およびその製造方法 |
| JP3872773B2 (ja) * | 2003-06-25 | 2007-01-24 | 三菱重工業株式会社 | 金属膜作製方法及び金属膜作製装置 |
| JP3828511B2 (ja) * | 2003-06-26 | 2006-10-04 | 株式会社東芝 | 半導体装置の製造方法 |
-
2005
- 2005-05-17 JP JP2005144616A patent/JP4852261B2/ja not_active Expired - Fee Related
-
2006
- 2006-05-17 KR KR1020077029289A patent/KR100940824B1/ko not_active Expired - Fee Related
- 2006-05-17 WO PCT/JP2006/309794 patent/WO2006123673A1/ja not_active Ceased
- 2006-05-17 US US11/919,484 patent/US7776751B2/en not_active Expired - Fee Related
- 2006-05-17 EP EP06746497A patent/EP1884987A4/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| KR20080017364A (ko) | 2008-02-26 |
| EP1884987A1 (en) | 2008-02-06 |
| WO2006123673A1 (ja) | 2006-11-23 |
| US20090081869A1 (en) | 2009-03-26 |
| KR100940824B1 (ko) | 2010-02-05 |
| US7776751B2 (en) | 2010-08-17 |
| EP1884987A4 (en) | 2012-11-21 |
| JP2006324357A (ja) | 2006-11-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102632203B1 (ko) | 반도체 응용들을 위한 나노와이어들을 제조하기 위한 선택적 산화 | |
| US10177227B1 (en) | Method for fabricating junctions and spacers for horizontal gate all around devices | |
| KR101189926B1 (ko) | 플라즈마 cvd 방법, 질화 규소막의 형성 방법 및 반도체 장치의 제조 방법 | |
| JP2006261217A (ja) | 薄膜形成方法 | |
| TW201739001A (zh) | 水平環繞式閘極元件的奈米線氣隙間隔之形成 | |
| TWI450338B (zh) | 場效電晶體之閘極介電質的製造方法 | |
| JP2006135161A (ja) | 絶縁膜の形成方法及び装置 | |
| WO2007114155A1 (ja) | プラズマ原子層成長方法及び装置 | |
| CN103137468B (zh) | 半导体制造装置及半导体制造方法 | |
| JPWO2007139041A1 (ja) | 金属化合物層の形成方法、半導体装置の製造方法及び金属化合物層の形成装置 | |
| JP4852261B2 (ja) | シリコン化合物の形成方法 | |
| JP2011023431A (ja) | 炭化珪素半導体装置の製造方法 | |
| WO2011078240A1 (ja) | ドープエピタキシャル膜の選択成長方法及びドープエピタキシャル膜の選択成長装置 | |
| KR101098975B1 (ko) | 기판 처리 장치 | |
| TWI305941B (en) | Method for forming transistor of semiconductor device | |
| TW202514790A (zh) | 有提升的表面純度之含矽及鍺材料之選擇性蝕刻 | |
| JP2007123662A (ja) | 半導体装置の製造方法および半導体装置 | |
| CN117558762B (zh) | 一种沟槽型mosfet及制备方法 | |
| Liao et al. | NMOS SiP Epitaxy Process-Optimizing Facet Growth | |
| US20110189862A1 (en) | Silicon oxynitride film and process for production thereof, computer-readable storage medium, and plasma cvd device | |
| CN102479721A (zh) | 晶体管及其形成方法 | |
| JPWO2008065908A1 (ja) | 金属iv族元素化合物膜の形成方法及び半導体装置の製造方法 | |
| CN117497605A (zh) | 一种高温下低导通电阻的pmos及制备方法 | |
| JP2006294953A (ja) | 半導体装置の製造方法及び製造装置 | |
| CN117497604A (zh) | 一种改进型平面栅mosfet及制备方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20061030 |
|
| RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20061116 |
|
| A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20070215 |
|
| RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20070307 |
|
| A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20081125 |
|
| RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20081125 |
|
| RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20090123 |
|
| RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20090127 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100412 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100611 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110411 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110601 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20111017 |
|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20111024 |
|
| R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20141028 Year of fee payment: 3 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |