JP5117817B2 - Multi-level voltage generator, data driver, and liquid crystal display device - Google Patents

Description

  The present invention relates to a multilevel voltage generator, a data driver using the same, and a liquid crystal display device, and more particularly to a layout pattern of a resistor string in the multilevel voltage generator.

  The resistor string includes a plurality of resistors connected via a plurality of voltage dividing electrodes, divides an input reference voltage, and outputs a divided voltage (level voltage) from each of the plurality of voltage dividing electrodes. As an example of a conventional resistor string layout pattern, a resistor string described in JP-A-8-213912 will be described (see Patent Document 1). In the resistor string described in Patent Document 1, contacts and electrodes are provided at equal intervals in one resistor element, and a divided voltage is output therefrom. FIG. 14 is a plan view showing a layout pattern of a resistor string described in Patent Document 1. As shown in FIG.

Referring to FIG. 14, in a resistor string 50 according to the prior art, N + 1 contacts 54-0 to 54 -N are provided at equal intervals in one resistor element 55. Resistor string 50, the contact 54-0 and 54-N of dividing the potential difference between the reference voltages VG ₀ and VG _N are input to each minute, through a contact 54-0~54-N divided voltage _V 0 ~V _N is output. In particular, the contact 54-0, the reference voltage VG ₀ is connected to the wiring 51 to be input, the contact 54-N, the wiring 52 in which the reference voltage VG _N is input is connected. Wirings 53-1 to 53- (N-1) are connected to the contacts 54-1 to 54- (N-1), respectively. With such a configuration, the potential difference between the two input reference voltages VG ₀ and VG _N is divided by the resistance R between the contacts (between the voltage dividing electrodes), and the divided voltages V _{1 to} V _N−1. To the nodes 56-1 to 56- (N-1). The input reference voltages VG ₀ and VG _N are supplied to the nodes 5-0 and 56-N as the divided voltages V ₀ and V _N via the wirings 51 and 52, respectively.

In recent years, a highly accurate divided voltage is required, and a technique for improving the accuracy of the voltage dividing resistor is required. For this reason, in order to improve the accuracy of the voltage dividing resistor, a resistor string in which a plurality of resistor elements are connected via voltage dividing electrodes instead of one resistor element is described as a prior art in Japanese Patent Laid-Open No. 2000-208703. (See Patent Document 2). Furthermore, Patent Document 2 describes a technique for improving the accuracy of a divided voltage by avoiding variations in resistance (hereinafter referred to as contact resistance) in a contact by using a low resistance element as a pattern for extracting a polarization electrode. Yes.
JP-A-8-213912 Japanese Patent Application No. 2000-208703

  On the other hand, in order to reduce display unevenness of a display device typified by a liquid crystal display device, a highly accurate gradation voltage is required. In particular, there is a need for a technique for reducing an error between a gradation voltage generated by a gradation voltage generation circuit and a gamma curve of a desired gradation voltage.

  However, the resistance string according to the prior art has a difference in resistance between voltage dividing electrodes (hereinafter referred to as divided resistance) that contributes to voltage division due to the contact resistance of a contact to which a reference voltage is input. For this reason, when the resistor string according to the prior art is used for the gradation voltage generating circuit, the precision of the gradation voltage is lowered, and it is difficult to obtain the gradation voltage corresponding to the desired gamma curve. Hereinafter, with reference to FIGS. 14 and 15, an error in the divided voltage (gradation voltage) of the resistor string according to the conventional technique will be described.

FIG. 15 is an equivalent circuit of the resistor string 50 shown in FIG. Referring to FIG. 14, in a stable state, constant current I based on the reference voltage flows along a path from wiring 51 to wiring 52 via contacts 54-0 and 54 -N. For this reason, as shown in FIG. 15, contact resistances r _con0 and r _conN are formed by the contacts 54-0 and 54-N on the current path. When the contact resistances r _con0 and r _conN are not considered, the reference voltage is _divided only by the resistor R, and the generated _divided voltages V _{0 to} V _N are output at desired values (ideal values). However, actual divided voltage _{V 1 ~V N-1} whereas receiving the influence of the voltage drop due to contact resistance _{r con0} and _{r Conn,} gradation voltages _{V 0} and _{V N} are, VG ₀ and VG _N is output as it The For this reason, in the resistor string according to the prior art, the relative error between the divided voltages V _{0 to} V _N becomes large. Further, each product due to variations in the r _con0 ~r _Conn during manufacture, and there is a possibility that different values for each contact, resulting gradation voltage output as designed be designed in anticipation of contact resistance The display characteristics may be deteriorated. Or, if the product selection standard is tightened to avoid this problem, the product yield may be lowered.

  The above-described problem occurs in the resistance string described in Patent Document 2 as well as in the resistance string configured by connecting a plurality of resistance elements. Particularly, in a resistor string configured by connecting a plurality of resistance elements, a difference occurs in contact resistance due to manufacturing variations of contacts connecting the resistance elements, and the relative error of each gradation voltage further increases.

  [Means for Solving the Problems] will be described below using the numbers and symbols used in [Best Mode for Carrying Out the Invention] in parentheses. This number / symbol is added to clarify the correspondence between the description of [Claims] and the description of the best mode for carrying out the invention. It should not be used for interpreting the technical scope of the invention described in [Scope].

Multilevel voltage generator according to the present invention (22), a first reference voltage to be supplied (VG ₀₎ and a second reference voltage (VG _N) and a plurality of level voltage corresponding to _(V 0 _~V N) Is a multi-level voltage generator. The multi-level voltage generator (22) includes a resistor (7), a first conductor (10) to which a first reference voltage (VG ₀ ) is supplied, and a second reference voltage (VG _N ). The supplied second conductor (11) and the first level voltage (V ₀ ) having a value closest to the first reference voltage (VG ₀ ) among the plurality of level voltages (V _{0 to} V _N ) The third conductor (1) to be output and the fourth conductor (3 _-N ) that outputs a second level voltage (for example, V _N-1 ) different from the first level voltage (V ₀ ). In this case, each of the first to fourth conductors (1, 10, 3- (N-1), 11) is formed separately. The level voltage generator (22) combines the first conductor (10) and the resistor (7) to enable conduction, and the second conductor (1). 1) and the resistor (7) are coupled to enable conduction, and the second connection portion (9) that allows conduction and the third conductor (1) and resistor (7) are coupled to enable conduction. The third connection portion (4), the fourth conductor (3- (N-1), and the resistor (7) are coupled to each other to enable conduction. Here, the third connecting portion (4), the first connecting portion (8), the fourth connecting portion (6- (N-1)), and the second connecting portion (9). _Are sequentially arranged on the resistor (7) so as to form first to third resistance regions (r _dum and R) in series.

With such a configuration, a constant current (I) based on the first and second reference voltages (VG ₀ and VG _N ) is generated between the first connection portion (8) and the second connection portion (9). Only the second and third resistance regions (R) formed in For this reason, the influence by the contact resistance of the connection parts (8, 9) to which the reference voltage is supplied acts uniformly on all the level voltages (V _{0 to} V _N ).

Further, the multi-level voltage generator (22) according to the present invention is preferably applied to the data driver (20) as a gradation voltage generating circuit. In this case, the data driver (20) includes a decoder (25) for selecting a level voltage (V _{0 to} V _N ) output from the multi-level voltage generator (22) according to input digital data, and a decoder ( And an amplifier (26) for amplifying and outputting the level voltage selected in 25).

  Further, the data driver (20) using the multi-level voltage generator (22) is preferably applied to the liquid crystal display device (100). In this case, the liquid crystal display device (100) includes the above-described data driver (100), a display panel (40) having pixels (P) connected to the scanning lines (47) and the data lines (46), and scanning. And a gate driver (30) for driving the line (47).

  According to the multilevel voltage generator of the present invention, it is possible to suppress relative errors in a plurality of level voltages to be output.

  Further, according to the data driver and the liquid crystal display device using the multi-level voltage generator according to the present invention as the gradation voltage generating circuit, display unevenness can be reduced.

  Further, the yield of the multilevel voltage generator, the data driver using the same, and the liquid crystal display device can be improved.

  Hereinafter, embodiments of a grayscale voltage generation circuit and a layout pattern of resistor strings according to the present invention will be described with reference to the accompanying drawings. In this embodiment, a gradation voltage generation circuit that is formed integrally with other circuits in a data driver of a liquid crystal display device as a multi-level voltage generator and generates a gradation voltage for driving a data line (pixel). As an example, a layout pattern of resistor strings will be described. The layout pattern corresponds to a mask pattern used in an exposure apparatus or the like in a process in which elements and circuits are formed by laminating a thin film material on a semiconductor substrate, an insulating substrate, or the like. In the following description, the same components and signals are denoted by the same reference numerals, and when there are a plurality of the same components, a serial number is assigned for explanation. In addition, when a plurality of configurations are collectively referred to, they will be described with reference numerals excluding the serial number.

1. Configuration of Liquid Crystal Display Device 100 With reference to FIGS. 1 and 2, the configuration of the liquid crystal display device 100 using the gradation voltage generation circuit 22 according to the present invention will be described. FIG. 1 is a block diagram showing a configuration of the liquid crystal display device 100. The liquid crystal display device 100 includes a data driver 20, a gate driver 30, and a display panel 40. In the display panel 40, pixels P are provided in intersection areas of a plurality of data lines 46 and a plurality of scanning lines 47 that are orthogonal to each other. Although only one data line 46, one scanning line 47, and one pixel P are shown in FIG. 1, the actual display panel 40 is provided with a plurality of data lines 46 and gate lines 47. Pixels P are provided in a matrix. The data driver 20 outputs a data signal _Vout to the data line 46 and drives the pixel P. The gate driver 30 drives the gate line 47 to determine the pixel P to which the data signal _Vout is written. The pixel P includes a TFT 48 and a liquid crystal capacitor 43 connected between a pixel electrode 44 that is one end of the TFT 48 and a counter electrode 45. When the data signal V _out is supplied through the data line 46 in a state where the TFT 48 is turned on by the gate driver 30, the data signal V _out is written into the liquid crystal capacitor 43.

FIG. 2 is a block diagram showing the configuration of the data driver 20. The data driver 20 includes a gradation voltage circuit 22, a latch address selector 23, a latch 24, a decoder 25, and an amplifier 26. The latch address selector 23 designates the address of the pixel P to be driven with respect to the latch 24 at a timing according to the clock CLK. The latch 24 outputs the input video data to the decoder 25 as a B-bit data signal in accordance with the strobe signal STB. The gradation voltage generation circuit 22 supplies gradation voltages V _{0 to} V _N for driving the data line 44 to the decoder 25. Specifically, the gradation voltage generation circuit 22 includes a resistor string 21 that outputs gradation voltages V _{0 to} V _N corresponding to input reference voltages (gamma voltages) VG ₀ and VG _N. A plurality of decoders 25 and amplifiers 26 are provided corresponding to the plurality of data lines 46. Resistor string 21 has a node 14 - 0 to 14-N for outputting a gray scale voltage _V 0 ~V _N, which via a switch circuit (not shown) connected to each of the plurality of decoders 25. The decoder 25 selects a gradation voltage corresponding to the data signal from the latch 24 from the gradation voltages V _{0 to} V _N and outputs it to the data line 44 as the data signal V _out .

  Here, the gradation voltage selected by the decoder 25 is supplied to an input terminal of a differential amplifier (not shown) of the amplifier 26 (for example, a gate terminal of a transistor constituting a differential pair). That is, the nodes 14-0 to 14-N are connected to a capacitive load (the gate capacitance of a transistor constituting a differential pair), and between the nodes 14-0 to 14-N and the input terminal of the amplifier 26. However, no constant current (static current consumption) flows through (after sufficient time has elapsed). A plurality of gradation voltages may be selected simultaneously by the decoder 25. At this time, the node 14 that outputs the selected grayscale voltage is connected to a plurality of input terminals of the differential amplifier in the amplifier 26, but as described above, between the node 14 and the input terminal of the differential amplifier. A constant current does not flow through.

2. First Embodiment A first embodiment of a resistor string 21 according to the present invention shown in FIG. 2 will be described with reference to FIGS. In the following embodiments, a resistor string is described in which a divided resistor is formed using a single continuous resistance element and a contact, and a grayscale voltage corresponding to a reference voltage is generated.

(Layout pattern of resistor string 21)
FIG. 3 is a plan view showing a layout pattern of the resistor string 21. FIG. 4 is a perspective view of the resistor string 21 as viewed three-dimensionally. Referring to FIGS. 3 and 4, the resistor string 21, the gray scale voltage _V 0 to Vn corresponding to the reference voltage VG ₀ and VG _N is supplied to one resistive element 7, the contact 4,6-1～ 6- (N-1) and 5 are output to the nodes 14-0 to 14-N. In particular, the contact 8 and 9 are provided on a single resistive element 7, the reference voltage VG ₀ and VG _N are input via respective lines 10 and 11. Further, N-1 contacts 6-1 to 6- (N-1) are provided at equal intervals between the contact 8 and the contact 9 on the resistance element 7, and the resistance R is set by the resistance element between the contacts. Is formed. Contacts 6-1 to 6- (N-1) in the present embodiment are provided in a region on the shortest distance line connecting contact 8 and contact 9 in resistance element 7. Wirings 3-1 to 3- (N-1) are connected to the contacts 6-1 to 6- (N-1), respectively, and gradation voltages V _{1 to} V _N-1 are connected to the node N14-1 from there. To 14- (N-1). In FIG. 4, the heights of the contacts need not be equal. Moreover, each wiring may be below the resistance element 7 instead of above.

Further, contacts 4 and 5 for extracting the gradation voltages V ₀ and V _N are provided in the resistance element 7 outside the region between the contacts 8 and 9. For example, as shown in FIG. 3, the contact 4 is provided in the region of the resistance element 7 facing the contact 6-1 with the contact 8 interposed therebetween. At this time, the distance between the contact 4 and the contact 8 is preferably sufficiently small. Similarly, the contact 5 is provided in the region of the resistance element 7 facing the contact 6-N across the contact 9, and the distance between the contact 5 and the contact 9 is preferably sufficiently small. Here, a dummy resistor r _dum is formed by a resistive element between the contact 4 and the contact 8 and between the contact 5 and the contact 9. This dummy resistor r _dum is preferably almost equal to zero. A wiring 1 is connected to the contact 4, and a gradation voltage V ₀ having a value substantially equal to VG ₀ is supplied to the node 14-0 through the wiring 1. Similarly, the wiring 2 is connected to the contact 5, and the gradation voltage V _N having a value substantially equal to VG _N is supplied to the node 14 _-N via the wiring 2.

Here, if the reference voltage VG ₀ is a voltage value greater than the reference voltage VG _N , the gradation voltage V ₀ is the maximum value of the gradation voltage, and the gradation voltage V _N is the minimum value of the gradation voltage. In other words, in the present invention, the contacts 4 and 5 serving as the outlets for the maximum value and the minimum value of the gradation voltage are provided outside the region between the contact 8 and the contact 9 serving as the reference voltage supply port. In other words, the contacts 4 and 5 serving as the outlets for the gradation voltages V ₀ and V _N closest to the reference voltages VG ₀ and VG _N are provided outside the region between the contacts 8 and 9. If the contacts 6-1 to 6- (N-1) are provided in the region on the shortest distance line connecting the contact 8 and the contact 9, the circuit area can be reduced, which is advantageous in terms of area cost.

  Here, the wirings 1, 2, 3-1 to 3-(N−1) and the wirings 10 and 11 are preferably metal wirings, and the wiring 1 and the wiring 10 and the wiring 2 and the wiring 11 are separated from each other.

(Operation of the resistor string 21)
With the configuration as described above, the resistor string 21 supplies the gradation voltage _V 0 ~V _N corresponding to the reference voltage VG ₀ and VG _N to node ₁₄ 0 to 14 _N. At this time, since the capacitive load in the amplifier 26 (the gate capacitance of the transistors constituting the differential pair) is connected to the nodes 14-0 to 14-N, in the stable state, the contacts 4, 6-1 to The constant current (static current consumption) does not flow through the path from 6- (N-1) 5 to the nodes 14-0 to 14-N. On the other hand, a constant current I flows between the contact 8 and the contact 9 in accordance with the potential difference between the reference voltage VG ₀ and the reference voltage VG _N. At this time, the constant current I flows through a path from the contact 8 to the contact 9 via the contacts 6-1 to 6- (N-1). However, since the contacts 4 and 5 are not provided between the contact 8 and the contact 9, they are off the path of the constant current I.

FIG. 5 is an equivalent circuit of the resistor string 21 in the first embodiment. With reference to FIG. 5, the influence of the contact resistance in the resistor string 21 will be described. Here, each contact resistance resisted by contact 8 and 9 _{r conH,} and _{r CONL,} the resistance due to the contact 4 and 5 and the contact resistance _{r con0} and _{r Conn} respectively, by contact 6-1~6- (N-1) The resistances are referred to as contact resistances r _{con1 to} r _conN−1 , respectively.

Referring to FIG. 5, N resistors R by resistance element 7 are connected in series between nodes 17 and 18. The connection points between the resistors R are connected to the nodes 14-1 to 14- (N-1) via the contact resistors r _{con1 to} r _conN-1 . The node 17 is connected to the node 14-0 via the dummy resistor r _dum and the contact resistor r _con0 , and the node 18 is connected to the node 14-N via the dummy resistor r _dum and the contact resistor r _conN. . Further, the reference voltage VG ₀ is supplied to the node 17 via the contact resistance r _conH , and the reference voltage VG _N is supplied to the node 18 via the contact r _conL .

As described above, no current flows through the contacts 4, 5, 6-1 to 6- (N-1) in the stable state. That is, the constant current does not flow through the dummy resistor _{r dum,} and the contact resistance _r con0 _{~r conN.} Therefore, the dummy resistor _{r dum} for gradation voltages _V 0 ~V _N, and influence of the voltage drop due to contact resistance _r con0 _{~r Conn} is eliminated. The constant current I flows through N resistors R via the contact resistors r _conH and r _conL . Therefore, the node 17 and 18, the reference voltage VG ₀ and VG _N that voltage drop by the respective contact resistances _{r conH} and _{r CONL} are supplied. As described above, the influence of the voltage drop due to the contact resistances r _conH and r _conL acts uniformly on all the values of the gradation voltages 14-0 to 14-N, and therefore affects the relative error between the gradation voltages. do not do. That is, the resistor string 21 according to the present invention can supply the gradation voltages V _{0 to} V _N approximated to a desired gamma curve as compared with the prior art.

As described above, according to the present invention, the maximum value (grayscale voltage V ₀ ) and the minimum value (grayscale voltage V _N ) of the grayscale voltage are provided in a region outside the current path of the constant current I based on the reference voltage. Contacts 4 and 5 are provided for taking out. For this reason, the influence of the voltage drop due to the contact resistances r _conH and r _conL due to the contacts 8 and 9 to which the reference voltage is supplied is uniformly applied to all the gradation voltages V _{0 to} V _N , and the relative error between the gradation voltages is _calculated. Can be suppressed.

Further, in a conventional resistor string using a plurality of resistance elements, a relative error between gradation voltages is large due to manufacturing variations of contact resistance. Furthermore, in the conventional technique using a plurality of resistance elements, a large number of contacts for connecting the divided resistors are required. On the other hand, in the present embodiment, since the resistor string uses one resistance element 7, it is not affected by the contact resistances _rcon0 to _rconN of the contacts that serve as the gradation voltage extraction ports, and between the gradation voltages. Relative error can be reduced. Also, the number of contacts may be smaller than when using a plurality of resistance elements. Therefore, according to the present invention, it is possible to provide a grayscale voltage generation circuit with a high yield.

In the present embodiment, the resistor string using one resistor element 7 has been described. However, the present invention is not limited to this, and the present invention can be applied to a form using a plurality of resistor elements. In this case, as in the case of using a single resistive element 7, the contact 4 and 5 for taking out the gradation voltages V ₀ and V _N, the contacts 8 and 9 reference voltages VG ₀ and VG _N is supplied What is necessary is just to provide so that it may not be located between. That is, the contacts 4 and 5 may be provided outside the constant current by the reference voltage. With this configuration, even in a resistor string using a plurality of resistance elements, the influence of the voltage drop due to the contact resistances V _conH and V _conL acts uniformly on all the gradation voltages V _{0 to} V _N. The relative error between the gradation voltages can be reduced.

(Modification of the first embodiment)
6 and 7 are plan views illustrating modifications of the layout pattern of the resistor string 21 according to the first embodiment. With reference to FIG. 6 and FIG. 7, the layout pattern of the resistor string 21 in which the contacts serving as the outlets for the gradation voltages V _{0 to} V _N are provided at positions away from the current path of the constant current I will be described.

Referring to FIG. 6, the resistor string 21, contacts 8 and 9 are provided on a single resistive element 7, the reference voltage VG ₀ and VG _N are input via respective lines 10 and 11. On the resistance element 7, N−1 contacts 6-1 to 6- (N−1) are provided at equal intervals between the contact 8 and the contact 9. Is formed. At this time, the contacts 6-1 to 6- (N-1) are the shortest distance lines connecting the contact 8 and the contact 9 in the resistance element 7 (current path of the constant current I between the contact 8 and the contact 9). Is provided in the outer region of. The distance between the shortest distance line connecting contact 8 and contact 9 and contacts 6-1 to 6- (N-1) is such that constant current I is not inhibited by contacts 6-1 to 6- (N-1). It is preferable that they are separated. The respective contact 6-1~6- (N-1) are connected to the wiring 3-1~3- (N-1), gradation corresponding therefrom to a potential difference between the reference voltage VG ₀ and the reference potential VG _N Voltages V _{1 to} V _N−1 are supplied to the nodes 14-1 to 14-(N−1).

Referring to FIG. 6, contacts 4 and 5 for taking out gradation voltages V ₀ and V _N are provided in resistance element 7 outside the region between contact 8 and contact 9. Here, the contact 4 is provided in a region adjacent to the contact 8 on the same side as the contact 6-1 with respect to the shortest distance line connecting the contact 8 and the contact 9. Here, the contact 4 is preferably provided in a region on the line adjacent to the contact 8 and orthogonal to the shortest distance line. The contacts 4 are preferably arranged so as to maintain the same layout pattern as the contacts 6-1 to 6- (N-1). Similarly, the contact 5 is provided in a region on a line adjacent to the contact 9 on the contact 6- (N-1) side and orthogonal to the shortest distance line connecting the contacts 8 and 9. Here, a dummy resistor r _dum is formed by a resistive element between the contact 4 and the contact 8 and between the contact 5 and the contact 9. This dummy resistor r _dum is preferably almost equal to zero. A wiring 1 is connected to the contact 4, and a gradation voltage V ₀ having a value substantially equal to VG ₀ is supplied to the node 14-0 through the wiring 1. Similarly, the wiring 2 is connected to the contact 5, and the gradation voltage V _N having a value substantially equal to VG _N is supplied to the node 14 _-N via the wiring 2.

As described above, when the resistor string 21 is formed in the layout pattern as shown in FIG. 6, the current I flowing between the contact 8 and the contact 9 can be routed only within the resistor element 7. In the layout pattern shown in FIG. 3, the resistance element 7 on the current path of the constant current I may be narrowed by the contacts 6-1 to 6- (N-1), and the resistance value may vary. Further, the variation value of the resistance value is not uniform due to the manufacturing variation of the contact. Therefore, the resistor string 21 formed in the layout pattern as shown in FIG. 6 supplies the gradation voltages V _{0 to} V _N with higher accuracy (with less relative error) than the resistor string shown in FIG. it can.

The layout pattern of the resistor string 21 shown in FIG. 7 is symmetric with respect to the shortest path outside the region of the shortest path (path of the constant current I) connecting the contact 8 and the contact 9 as in the layout pattern shown in FIG. This is an example in which a contact for taking out a grayscale voltage is provided so as to have the characteristics. Specifically, the pair of contacts 61-1 and 62-1 to 61- (N-1) and 62- (N) are arranged so as to sandwich the constant current I path connecting the contact 8 and the contact 9 of the resistance element 7. -1) is provided in the resistance element 7, and gradation voltages V _{1 to} V _N-1 are taken out from the respective contact pairs. Here, the respective contact pairs (for example, the contacts 61-1 and 62-1) are provided symmetrically with respect to the constant current I.

Further, contacts 41 and 42, 51 and 52 for taking out the gradation voltages V ₀ and V _N are provided in the resistance element 7 outside the region between the contacts 8 and 9. At this time, the pair of contacts 41 and contacts 42 are provided symmetrically so as to sandwich the contact 8. Similarly, the pair of contacts 5-1 and 5-2 are provided so as to sandwich the contact 9 therebetween. Further, the wiring 41 is connected to the contacts 41 and 42, and the gradation voltage V ₀ having a value substantially equal to VG ₀ is supplied to the node 14-0 via the wiring 1. Similarly, the contact 5-1 and 5-2, the wiring 2 are connected, the gradation voltage _{V N} at a value approximately equal VG _N via the wiring 2 is supplied to the node 14-N.

As described above, the resistor string 21 shown in FIG. 7 includes a plurality of contact pairs for taking out the grayscale voltages V _{1 to} V _N at positions avoiding the constant current I path. For this reason, compared with the resistor string 21 shown in FIG. 6, the layout pattern has symmetry, and manufacturing variations can be suppressed. Further, in the resistor string 21 shown in FIG. 6, since the contact exists only on one side in the vicinity of the current path, the influence of the electric field around the contact may be non-uniform. However, in the resistor string 21 shown in FIG. 7, since the contacts are provided symmetrically with respect to the current path, the influence of the electric field around the contacts becomes uniform, and the influence on the constant current I due to the manufacturing variation of the contacts, that is, The influence on the accuracy of the gradation voltage can be suppressed.

3. Second Embodiment With reference to FIGS. 8 and 9, a second embodiment of the resistor string 21 will be described. In the first embodiment, the dividing resistor that determines the gradation voltage is constant with the resistor R. In the second embodiment, a case where the dividing resistance between the voltage dividing electrodes is different will be described.

FIG. 8 is an equivalent circuit diagram of the resistor string 21 in the second embodiment. Here, it described in the first embodiment, the dummy resistor _{r dum,} and the contact resistance _r con0 _{~r Conn} is omitted. Referring to FIG. 8, the resistor string 21 used in the gradation voltage generation circuit 22 normally divides the reference voltage using resistors R _{1 to} R _N having different resistance values as divided resistors. FIG. 9 is a plan view showing a layout pattern of the resistor string 21 in the second embodiment. Referring to FIG. 9, the resistor string 21 in the second embodiment, for taking out the gradation voltages _{V 1 ~V N-1} contact 6-1～6- between each of (N-1) The distance is set to have a desired resistance value (R ₂ , R ₃ ,..., R _N-1 ). Here, the distance between the contact 8 and the contact 6-1 so that the resistor R _1, the distance of the contact 6- (N-1) and the contact 9 is set to be the resistor R _N. The other layout patterns are the same as those in the first embodiment, and a description thereof will be omitted.

As described above, the present invention can also be applied to a resistor string that generates gradation voltages using divided resistors having different resistance values, and the relative error of gradation voltages V _{0 to} V _N can be reduced as in the first embodiment. Can be suppressed.

4). Third Embodiment With reference to FIGS. 10 and 11, a third embodiment of the resistor string 21 will be described. In the resistor string 21 in the first embodiment, the gradation voltage is extracted from the divided polarization provided for each resistor R. In the third embodiment, a description will be given of a resistor string from which a gradation voltage is extracted from a voltage dividing electrode (contact and wiring) provided for each of a plurality of resistors R.

FIG. 10 is an equivalent circuit diagram of the resistor string 21 in the third embodiment. Here, described in the first embodiment, the dummy resistor _{r dum,} and the contact resistance _r con0 _{~r Conn} is, the influence of the voltage drop is not constant current flows is negligible, described are omitted. FIG. 10 shows, as an example, a resistor string 21 to which nodes 14-0, 14-2,..., 14-N for extracting gradation voltages for each of two resistors R are connected. The layout pattern of the resistor string 21 in this case is shown in FIG. Referring to FIG. 11, resistor string 21 in the third embodiment includes contacts 6-1, 6-3,..., 6- (N-1) and wiring 3- in the first embodiment. , 3- (N-1), dummy contacts 16-1, 16-3,..., 16- (N-1) and dummy wirings 15-1, 15- 3, ..., 15- (N-1) are provided. Further, the gradation voltage is not extracted from the dummy wirings 15-1, 15-3,..., 15- (N-1). That is, the contacts 6-2, 6-4,..., 6- (N-2) for taking out the gradation voltages to the nodes 14-2, 14-4,. and wiring 3-2,3-4, ···, 3- (N- 2) is provided for each two resistors R, gradation voltages _{V 0, V 2, ···,} V N is the node 14 , 14-2,..., 14-N. The other layout patterns are the same as those in the first embodiment, and a description thereof will be omitted. In this embodiment, the gradation voltage is extracted for each of the two resistors R, but the number is not limited.

As described above, the present invention can also be applied to a resistor string that generates a gradation voltage by a plurality of resistors, and suppresses a relative error of gradation voltages V _{0 to} V _N as in the first embodiment. Can do.

5. Fourth Embodiment With reference to FIGS. 12 and 13, a fourth embodiment of the resistor string 21 will be described. In the fourth embodiment, a resistor string including a plurality of resistor strings in the first embodiment will be described.

FIG. 12 is an equivalent circuit diagram of the resistor string 21 in the fourth embodiment. Here, a configuration in which two resistor strings 21A and 21B having the same configuration as the resistor string 21 described in the first embodiment are connected in series is shown. Further, the same components as those in the first embodiment are described by distinguishing them by attaching the symbols A or B to the same symbols. Further, the dummy resistor _{r dum,} and the contact resistance _r con0 _{~r Conn} is, the influence of the voltage drop is not constant current flows is negligible, described are omitted. Referring to FIG. 12, the resistor string 21A, the reference voltage VG ₀ and VG _N are input, and supplies the gradation voltage _V 0A _{~V NA} corresponding to the node 14A-0~14A-N. Resistor string 21B, the reference voltage VG _N and _{VG 2N} are input, and supplies the gradation voltage _V 0B _{~V NB} corresponding to the node 14B-1~14B-2N. The resistor string 21A, the reference voltage VG _N is supplied through the node 19A. Further, the resistor string 21B is connected to the node 19A, having nodes 19B to the reference voltage VG _N is supplied. As shown in FIG. 12, between node 19A and node 19B, the resistance R _t is provided, the reference voltage that is a voltage drop by the resistor R _t may be supplied to the node 19B. Further reference voltage VG _N is not a node 19A, it may be supplied to the node 19B. Further, the reference voltage VG _N may not be supplied to either of the nodes 19A and 19B, and only the reference voltages VG ₀ and VG _2N may be supplied. In that case, a constant current flows through a path from the terminal to which the reference voltage VG ₀ is supplied to the terminal to which the reference voltage VG _2N is supplied via the resistor string 21A, the resistor R _t , and the resistor string 21B.

FIG. 13 shows a layout pattern of the resistor string 21 corresponding to the equivalent circuit shown in FIG. Referring to FIG. 13, each of the resistor strings 21 in the fourth embodiment includes resistor strings 21A and 21B having a layout pattern similar to that in the first embodiment. The wiring 11A of the resistor string 21A, the wiring 10B of the resistor string 21B is connected through a resistor _{R t.} In particular, contact 8C and 9C are provided on the resistive element 7C to form a resistance value R _t. The contact 8C is connected to the wiring 11A through the wiring 11C, and the contact 9C is connected to the wiring 10B through the wiring 10C. That is, the reference voltage VG _N is supplied to the wiring 11A is supplied to the contact 8B of the resistor string 21B via the resistor _{R t} formed between the contact 8C and 9C. The wiring 10C and the wiring 11C are formed separately. Further, the wiring 11A and the wiring 11C, and the wiring 10B and the wiring 10C may be the same wiring. A reference voltage _V2N is supplied to the wiring 11B. Here, the reference voltage V _2N is smaller than the reference voltage supplied to the wiring 10B.

With such a configuration, in the resistor string 21A, the influence of the voltage drop due to the contact resistances r _conHA and r _{conLA on} the reference voltage acts equally on the grayscale voltages V _{0A to} V _NA and suppresses the relative errors thereof. . Similarly, in the resistor string 21B, the influence of the voltage drop caused by the contact resistances r _conHB and r _{conLB on} the reference voltage acts equally on the grayscale voltages V _{0B to} V _NB , and suppresses the relative errors thereof. That is, the relative error of the gradation voltage in each of the resistor strings 21A and 21B is suppressed.

  As described above, the present invention can suppress the relative error of the gradation voltage in each resistor string even when the resistor strings 21 are provided.

6). Fifth Embodiment With reference to FIGS. 16 and 17, a fifth embodiment of the resistor string 21 will be described. The fifth embodiment is a resistor string provided with a plurality of resistor strings in the modified example (FIGS. 5 and 6) of the first embodiment. Further, the fifth embodiment is a resistor string suitable for the case where the reference voltage VG _N is not supplied and only the reference voltages VG ₀ and VG _2N are supplied in the fourth embodiment (FIGS. 12 and 13). It is the composition. In FIG. 13 of the fourth embodiment, the relative error in the gradation voltages V _{0A to} V _NA and the gradation voltages V _{0B to} V _NB in each of the resistor strings 21A and 21B can be suppressed. However, when the reference voltage VG _N is not supplied and only the reference voltages VG ₀ and VG _2N are supplied, the contact of the resistor string 21A and the contact of the resistor element 7C are on the current path at the connection portion of the resistor strings 21A and 21B. There are contacts 8B of 8C and 9C and the resistor string 21B, which are affected by the voltage drop of four contact resistances. If this reason there is a variation of the contact resistance, there is a possibility that the relative error in the potential difference between the gradation voltage V _NA and V _0B. In the fifth embodiment, a configuration in which a relative error is suppressed even with respect to a potential difference between resistor strings will be described.

FIG. 16 is an equivalent circuit diagram of the resistor string 21 in the fifth embodiment. Here, a configuration is shown in which two resistor strings 21A and a resistor string 21B having the same configuration as that of the resistor string 21 described in the modification of the first embodiment (FIGS. 5 and 6) are connected in series. Further, the same configurations as those in FIGS. 5 and 6 will be described by adding the same reference numerals to the same reference numerals as A or B. Further, the dummy resistor _{r dum,} and the contact resistance _r con0 _{~r Conn} is, the influence of the voltage drop is not constant current flows is negligible, described are omitted. Referring to FIG. 16, reference voltages VG ₀ and VG _XN are respectively input to the resistor strings 21A and 21B, and grayscale voltages V _{0A to} V _NA corresponding thereto are supplied from the resistor string 21A to the nodes 14A-0 to 14A-N. The gradation voltages V _{0B to} V _NB are supplied from the resistor string 21B to the nodes 14B-1 to 14B-N. 5 and 6, the N resistors R of the resistor string are all the same. However, as described in the second embodiment, each resistor R may have a different resistance value. Therefore, in the fifth embodiment, the N resistors of the resistor string 21A are R _{1A to} R _NA, and the N resistors of the resistor string 21B are R _{1B to} R _NB . The resistor strings 21A and 21B are connected via a resistor R _{(N + 1) A} added to the resistor string 21A. One end of the resistor R _{(N + 1) A} is connected to the node 18A, and the other end (node 19A-1) of the resistor R _{(N + 1) A} is connected to the contact resistor r _contLA . The contact resistance r _contLA (node 19A-2) of the resistance string 21A and the contact resistance r _contHB (node 17B-1) of the resistance string 21B are connected by wiring (metal wiring or the like), thereby connecting the resistance strings 21A and 21B. Is done.

Further, another resistor string 21C may be provided in the middle of the wiring connecting the resistor string 21A and the resistor string 21B. In FIG. 16, the resistor string 21C has the same configuration as that of the resistor string 21A. Resistor string 21C is connected to the contact resistance _{r ContLA} nodes 19A-2 of the node 17C-1 is the resistor string 21A through the wiring of the contact resistance _{r contHC,} via the node 19C-1 is the wiring contact resistance _{r ContLC} resistance It is connected to the node 17B-1 of the contact resistance r _contHB of the string 21B. The constant current flows through a path from the terminal to which the reference voltage VG ₀ is supplied to the terminal to which the reference voltage VG _XN is supplied via the resistor strings 21A, 21C, and 21B. The reference voltage is not input to the resistor string 21C, and the gradation voltages V _{0C to} V _NC are supplied from the resistor string 21C to the nodes 14C-0 to 14C-N according to the constant current. Note that a plurality of resistor strings 21C may be provided in series between the resistor strings 21A and 21B.

FIG. 17 shows a layout pattern of the resistor string 21 corresponding to the equivalent circuit shown in FIG. Referring to FIG. 17, each of the resistor strings 21 in the fifth embodiment includes resistor strings 21A and 21B having a layout pattern similar to that in FIG. 17 differs from the layout pattern in FIG. 6 in that the contact 9 connected to the wiring 11 is arranged in the vicinity of the contact 5 connected to the wiring 2 in FIG. 6, but is connected to the wiring 11A-1 in FIG. The resistor element 7A is arranged at a position where the resistor R _{(N + 1) A} is extended from the vicinity of the contact 5A where the contact 9A-1 is connected to the wiring 2A. The wiring 11A-1 of the resistor string 21A is connected to the wiring 10B of the resistor string 21B, whereby the resistor string 21A and the resistor string 21B are connected. Preferably, the wirings 11A-1 and 10B are the same wiring.

  Further, the resistor string 21C may be disposed between the resistor string 21A and the resistor string 21B. In FIG. 17, the resistor string 21C has the same layout pattern as the resistor string 21A. In this case, the wiring 10C of the resistance string 21C is connected to the wiring 11A-1 of the resistance string 21A, and the wiring 11C-1 is connected to the wiring 10B of the resistance string 21B. Preferably, the wirings 11A-1 and 10C are the same wiring, and the wirings 11C-1 and 10B are also the same wiring.

16 and 17, when the resistor strings 21A and 21B are connected (when the resistor string 21C is not provided), the contact 9A− of the resistor string 21A is on the constant current path at the connection portion of the resistor strings 21A and 21B. 1 and only the contact 8B of the resistor string 21B, the voltage drop of the contact resistance is reduced to two places. Thus resistor string 21A than the case of the fourth embodiment in the present embodiment (FIG. 13), reduced the influence of the contact resistance between 21B, it can be suppressed relative error of the potential difference between the gradation voltage V _NA and V _0B . Note that the resistor R _{(N + 1) A} of the resistor string 21A is formed in the same resistor element 7A as the resistors R _{1A to} R _NA, and is a gradation generated by resistance division of the resistors R _{1A to} R _{(N + 1) A.} The relative error of voltage V is small. Potential difference of the gradation voltages _{V 0B} between the gradation voltage _{V NA} of the resistor string 21A resistor string 21A is set by the resistor _{R (N + 1) A.} The resistor R _{(N + 1) A} is divided into resistance elements 7A and 7B, and the divided resistors are connected via the contacts 9A-1 and 8B and the wiring 11A-1 (10B). May be. In addition, even when the resistor string 21C is connected between the resistor strings 21A and 21B, there are only two contact resistors through which a constant current flows at the connection portion between the resistor strings. Therefore, the relative error of the gradation voltage between each resistor string can be suppressed. The potential difference between the gradation voltages V _NA and V _{0C of} the resistor strings 21A and 21C is set by the resistor R _{(N + 1) A} , and the potential difference between the gradation voltages V _NC and V _{0B of} the resistor strings 21C and 21B is the resistance R _{(N + 1)} Set by C. The resistors R _{(N + 1) A} and R _{(N + 1) C} may be divided between the two resistance elements.

  As described above, the present invention can suppress the relative error of the grayscale voltage in each resistor string and the relative error of the grayscale voltage between the resistor strings even when the resistor strings 21 are provided. .

According to the present invention, the contacts 5 and 6 to which the maximum value (V ₀ ) and the minimum value (V _N ) of the gradation voltage are supplied are located in a region that is out of the current path of the constant current I flowing in the resistor string 21. By providing, a relative error between gradation voltages due to contact resistance can be suppressed. For this reason, when this invention is applied to a liquid crystal display device, the display nonuniformity of a display panel can be suppressed. Further, since the influence of the contact resistance on the gradation voltage is eliminated, the yield can be improved. When the present invention is applied to a liquid crystal display device, the reference voltage may be modulated according to the gamma characteristic of the liquid crystal panel. Even in this case, the relative accuracy of the gradation voltages V _{1 to} V _N-1 is maintained. Is done.

  The embodiment of the present invention has been described in detail above, but the specific configuration is not limited to the above-described embodiment, and changes within a scope not departing from the gist of the present invention are included in the present invention. . In the above-described embodiments, one contact for extracting the gradation voltage and one contact to which the reference voltage is supplied have been described (two in the modification), but a plurality of contacts may be provided. In this embodiment, the gradation voltage generation circuit used in the liquid crystal display device has been described as an example. However, it goes without saying that it can be used in circuits such as an AD converter or a DA converter, or a sensor using a plurality of level voltages. Yes.

FIG. 1 is a block diagram showing a configuration of a liquid crystal display device according to the present invention. FIG. 2 is a block diagram showing the configuration of the data driver according to the present invention. FIG. 3 is a plan view showing a layout pattern of the resistor string according to the first embodiment of the present invention. FIG. 4 is a diagram exemplarily illustrating the configuration of the resistor string in the first embodiment. FIG. 5 is an equivalent circuit of the resistor string in the first embodiment. FIG. 6 is a plan view showing a modification of the layout pattern of the resistor string in the first embodiment. FIG. 7 is a plan view showing a modification of the layout pattern of the resistor string in the first embodiment. FIG. 8 is an equivalent circuit of the resistor string in the second embodiment. FIG. 9 is a plan view showing a layout pattern of the resistor string according to the second embodiment of the present invention. FIG. 10 is an equivalent circuit of the resistor string in the third embodiment. FIG. 11 is a plan view showing a layout pattern of the resistor string according to the third embodiment of the present invention. FIG. 12 is an equivalent circuit of the resistor string in the fourth embodiment. FIG. 13 is a plan view showing a layout pattern of the resistor string according to the fourth embodiment of the present invention. FIG. 14 is a plan view showing a layout pattern of a resistor string according to the prior art. FIG. 15 is an equivalent circuit of a resistor string according to the prior art. FIG. 16 is an equivalent circuit of the resistor string in the fifth embodiment. FIG. 17 is a plan view showing a layout pattern of the resistor string according to the fifth embodiment of the present invention.

Explanation of symbols

1, 2, 3-1 to 3-N, 51, 52, 53-1 to 53-N, 10 to 13: Wiring 4, 41, 42, 4A, 4B: Contact MAX
5, 5-1, 5-2, 5A, 5B: contact MIN
6-1 to 6-N, 8, 9, 54-0 to 54-N, 61-1 to 61-N, 62-1 to 62N, 6A-1 to 6A-N, 6B-1 to 6B-N: Contacts 7, 55: Resistive elements 14-0 to 14-N, 14A-0 to 14A-N, 14B-0 to 14B-N, 17, 17B, 18, 18A, 19A, 19B, 56-0 to 56-N : Node 15: Dummy wiring 16: Dummy contact 20: Data driver 21, 21A, 21B, 21C, 50: Resistor string 22: Grayscale voltage generation circuit 23: Latch address selector 24: Latch 25: Decoder 26: Amplifier 30: Gate Driver 40: Display panel P: Pixel 43: Liquid crystal capacitance 44: Pixel electrode 45: Counter electrode 46: Data line 47: Scan line 48: TFT
100: Liquid crystal display device VG ₀ , VG _N : Reference voltage V _{0 to} V _N : Gradation voltage V _out : Display signal R, R _t : Resistance r _conH , r _conHA , r _conHB , r _conHC , r _conL , r _{conLA , r conLB, r conLC, r} con0 ~r conN: contact resistance

Claims (15)

A plurality of level voltages corresponding to the supplied first reference voltage and second reference voltage are generated, and a plurality of conductors that output the plurality of level voltages are capacitive on the input side of the amplifier via a decoder. A multi-level voltage generator connected to a load,
A resistor,
A first conductor supplied with a first reference voltage;
A second conductor supplied with a second reference voltage;
A third conductor that outputs a first level voltage having a value closest to the first reference voltage among the plurality of level voltages;
A fourth conductor from which a second level voltage different from the first level voltage is output;
A first connecting portion that couples the first conductor and the resistor to enable conduction;
A second connecting portion that couples the second conductor and the resistor to enable conduction;
A third connection portion that couples the third conductor and the resistor to enable conduction;
A fourth connection portion that couples the fourth conductor and the resistor to enable conduction;
Comprising
Each of the first to fourth conductors is separated from each other ,
Third connection portion prior to reporting, the first connecting portion, the fourth connecting portion, said second connecting portion, the first series configuration so as to form a third resistor region, the resistor Are arranged sequentially ,
An interval between the third connection portion and the first connection portion via the first resistance region is an interval between the first connection portion and the fourth connection portion via the second resistance region. And a multi-level voltage generator that is sufficiently smaller than an interval between the fourth connection portion and the second connection portion via the third resistance region . The multilevel voltage generator of claim 1.
A fifth conductor that outputs a third level voltage having a value closest to the second reference voltage among the plurality of level voltages;
A fifth connection portion that couples the fifth conductor and the resistor to enable conduction;
Further comprising,
Before fifth connection portion SL is disposed on the resistor so as to form a fourth resistance region between said second connecting portion,
The interval between the fifth connection portion and the second connection portion via the fourth resistance region is the interval between the first connection portion and the fourth connection portion via the second resistance region. And a multi-level voltage generator that is sufficiently smaller than an interval between the fourth connection portion and the second connection portion via the third resistance region . The multilevel voltage generator of claim 1.
A plurality of conductors that output a level voltage group different from the first and second level voltages among the plurality of level voltages;
A plurality of connecting portions that connect the plurality of conductors and the resistor to enable conduction;
Further comprising
The plurality of connection portions are disposed between the first and fourth connection portions, and the second resistance region formed between the first and fourth connection portions is further provided with a plurality of connection portions. Multi-level voltage generator that divides into resistive areas. The multilevel voltage generator of claim 3.
The fourth connection section and the plurality of connection sections are multi-level voltage generators arranged on a shortest path connecting the first connection section and the second connection section in the resistor. The multilevel voltage generator of claim 3.
The fourth connecting portion and the plurality of connecting portions are arranged at positions away from the shortest path connecting the first connecting portion and the second connecting portion in the resistor. vessel. A multi-level voltage generator according to any one of claims 1 to 5,
Each of the first to fourth conductors is a multi-level voltage generator formed of a metal material. To generate a plurality of level voltages corresponding to the first and second reference voltages supplied, via a plurality of electrical conductors decoder for outputting said plurality of level voltages connected to the capacitive load on the input side of the amplifier A multi-level voltage generator
First and second resistors;
A first conductor supplied with a first reference voltage;
A second conductor supplied with a second reference voltage;
Third and fourth conductors connecting the first and second resistors;
A fifth to eighth conductor from which a first to fourth level voltage is output at each of the plurality of level voltages;
A first connecting portion that couples the first conductor and the first resistor to enable conduction;
A second connection portion that couples the second conductor and the second resistor to enable conduction;
A third connection portion that couples the third conductor and the first resistor to enable conduction;
A fourth connecting portion that couples the fourth conductor and the second resistor to enable conduction;
5th and 6th connection parts which connect each of said 5th and said 6th electric conductors and said 1st resistor, and can conduct, and
Seventh and eighth connection portions that connect each of the seventh and eighth conductors and the second resistor to enable conduction;
Comprising
Each of the first, third, fifth, and sixth conductors coupled to the first resistor are separated from each other;
Each of the second, fourth, seventh, and eighth conductors coupled to the second resistor are separated from each other ;
Connecting portions of the front Symbol fifth, the first connection portion, the connection portion of the sixth, as the third connecting portions, to the first series form a third resistor region, said first Are placed sequentially on the resistors ,
Before SL connecting portion of the seventh, the fourth connection portion, the connection portion of the eighth, as the second connecting portion, to the fourth series morphogenesis resistance region of the sixth, the second Are placed sequentially on the resistors ,
The interval between the fifth connection portion and the first connection portion via the first resistance region is the interval between the first connection portion and the sixth connection portion via the second resistance region. And sufficiently smaller than the distance between the sixth connection part and the third connection part via the third resistance region,
The interval between the seventh connection portion and the fourth connection portion via the fourth resistance region is the interval between the fourth connection portion and the eighth connection portion via the fifth resistance region. And a multi-level voltage generator that is sufficiently smaller than an interval between the eighth connection portion and the second connection portion via the sixth resistance region . The multi-level voltage generator of claim 7,
A third resistor connected between the third conductor and the fourth conductor;
A multi-level voltage generator in which a third reference voltage is supplied to either the third conductor or the fourth conductor. The multi-level voltage generator of claim 7,
The multi-level voltage generator, wherein the fourth conductor is the same as the third conductor. The multi-level voltage generator of claim 7,
A multi-level voltage generator further comprising a plurality of resistors connected in series between the third conductor and the fourth conductor. The multi-level voltage generator according to any one of claims 7 to 10,
A ninth conductor from which a fifth level voltage is output;
A ninth connecting portion that couples the ninth conductor and the second resistor to enable conduction;
Further comprising,
Before SL connections ninth, the between the second connecting portion is disposed in said so as to form a resistive region of the seventh second resistor, the first through the seventh resistor region of The interval between the second connection portion and the ninth connection portion is the interval between the fourth connection portion and the eighth connection portion via the fifth resistance region, and via the sixth resistance region. A multi-level voltage generator that is sufficiently smaller than the distance between the eighth connection and the second connection . The multi-level voltage generator of claim 10.
A third resistor connected to the third conductor among the plurality of resistors connected between the third conductor and the fourth conductor;
Ninth and tenth conductors from which fifth and sixth level voltages are output, respectively;
A ninth connecting portion that couples the third conductor and the third resistor to enable conduction;
A tenth connecting portion that couples the ninth conductor and the third resistor to enable conduction;
An eleventh connection portion that couples the tenth conductor and the third resistor to enable conduction ;
Connecting portions of the front SL 10, connecting portions of the ninth, connecting portions of the first 11, so as to form a seventh and resistance region of the eighth series configuration, it is sequentially disposed on the third resistor, The interval between the tenth connection portion and the ninth connection portion via the seventh resistance region is the same as that between the ninth connection portion and the eleventh connection portion where the eighth resistance region is formed. Multilevel voltage generator that is sufficiently small compared to the interval . The multi-level voltage generator according to any one of claims 7 to 12,
A first conductor group that outputs a first level voltage group different from the first and second level voltages among the plurality of level voltages;
A second conductor group that outputs a second level voltage group different from the third and fourth level voltages among the plurality of level voltages;
A first connection portion group that allows the first conductor group and the first resistor to be coupled to each other to be conductive;
A second connection portion group that couples the second conductor group and the second resistor to enable conduction;
Further comprising
The first connection portion group is disposed between the first connection portion and the sixth connection portion, and is formed between the first and sixth connection portions. The resistance region is further divided into a plurality of resistance regions,
The second connecting portion group is disposed between the fourth connecting portion and the eighth connecting portion, and is formed between the fourth and eighth connecting portions. A multi-level voltage generator that further divides a resistance region into a plurality of resistance regions. A multi-level voltage generator according to any one of claims 1 to 13,
A decoder for selecting a level voltage output from the multi-level voltage generator according to input digital data;
An amplifier for amplifying and outputting the level voltage selected by the decoder;
A data driver comprising: A data driver according to claim 14;
A display panel having pixels connected to scanning lines and the data lines;
A liquid crystal display device comprising a gate driver for driving the scanning line.

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