JP6772995B2 - Soiウェーハの製造方法およびsoiウェーハ - Google Patents

Soiウェーハの製造方法およびsoiウェーハ Download PDF

Info

Publication number
JP6772995B2
JP6772995B2 JP2017183912A JP2017183912A JP6772995B2 JP 6772995 B2 JP6772995 B2 JP 6772995B2 JP 2017183912 A JP2017183912 A JP 2017183912A JP 2017183912 A JP2017183912 A JP 2017183912A JP 6772995 B2 JP6772995 B2 JP 6772995B2
Authority
JP
Japan
Prior art keywords
diamond
support substrate
layer
soi wafer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2017183912A
Other languages
English (en)
Japanese (ja)
Other versions
JP2019062020A (ja
Inventor
祥泰 古賀
祥泰 古賀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumco Corp
Original Assignee
Sumco Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumco Corp filed Critical Sumco Corp
Priority to JP2017183912A priority Critical patent/JP6772995B2/ja
Priority to FR1858146A priority patent/FR3071663B1/fr
Publication of JP2019062020A publication Critical patent/JP2019062020A/ja
Application granted granted Critical
Publication of JP6772995B2 publication Critical patent/JP6772995B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69Inorganic materials
    • H10P14/6902Inorganic materials composed of carbon, e.g. alpha-C, diamond or hydrogen doped carbon
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326Deposition processes
    • H10P14/6328Deposition from the gas or vapour phase
    • H10P14/6334Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6336Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6502Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed before formation of the materials
    • H10P14/6506Formation of intermediate materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19Preparing inhomogeneous wafers
    • H10P90/1904Preparing vertically inhomogeneous wafers
    • H10P90/1906Preparing SOI wafers
    • H10P90/1922Preparing SOI wafers using silicon etch back techniques, e.g. BESOI or ELTRAN
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10Isolation regions comprising dielectric materials
    • H10W10/181Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/26Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using liquid deposition
    • H10P14/265Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using liquid deposition using solutions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901Materials
    • H10P14/2902Materials being Group IVA materials
    • H10P14/2905Silicon, silicon germanium or germanium
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202Materials thereof
    • H10P14/3204Materials thereof being Group IVA semiconducting materials
    • H10P14/3206Carbon, e.g. diamond-like carbon
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34Deposited materials, e.g. layers
    • H10P14/3402Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3406Carbon, e.g. diamond-like carbon
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/36Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done before the formation of the materials

Landscapes

  • Crystals, And After-Treatments Of Crystals (AREA)
  • Chemical Vapour Deposition (AREA)
  • Recrystallisation Techniques (AREA)
JP2017183912A 2017-09-25 2017-09-25 Soiウェーハの製造方法およびsoiウェーハ Active JP6772995B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2017183912A JP6772995B2 (ja) 2017-09-25 2017-09-25 Soiウェーハの製造方法およびsoiウェーハ
FR1858146A FR3071663B1 (fr) 2017-09-25 2018-09-11 Procede de fabrication de plaque soi, et plaque soi

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2017183912A JP6772995B2 (ja) 2017-09-25 2017-09-25 Soiウェーハの製造方法およびsoiウェーハ

Publications (2)

Publication Number Publication Date
JP2019062020A JP2019062020A (ja) 2019-04-18
JP6772995B2 true JP6772995B2 (ja) 2020-10-21

Family

ID=65858443

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017183912A Active JP6772995B2 (ja) 2017-09-25 2017-09-25 Soiウェーハの製造方法およびsoiウェーハ

Country Status (2)

Country Link
JP (1) JP6772995B2 (fr)
FR (1) FR3071663B1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7071775B2 (ja) * 2019-05-10 2022-05-19 国立研究開発法人産業技術総合研究所 ダイヤモンド結晶体を備える複合体
JP7600973B2 (ja) 2021-12-08 2024-12-17 株式会社Sumco 積層ウェーハ及びその製造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01138198A (ja) * 1987-11-26 1989-05-31 Nec Corp ダイヤモンド膜の製造方法
JPH02206118A (ja) * 1989-02-06 1990-08-15 Hitachi Ltd 半導体素子
JPH09263488A (ja) * 1996-03-27 1997-10-07 Matsushita Electric Ind Co Ltd ダイヤモンド膜の製造方法
JP3951324B2 (ja) * 1996-09-03 2007-08-01 住友電気工業株式会社 気相合成ダイヤモンドおよびその製造方法
JP4654389B2 (ja) * 2006-01-16 2011-03-16 株式会社ムサシノエンジニアリング ダイヤモンドヒートスプレッダの常温接合方法,及び半導体デバイスの放熱部
JP2010258083A (ja) * 2009-04-22 2010-11-11 Panasonic Corp Soiウェーハ、その製造方法および半導体装置の製造方法
KR101985526B1 (ko) * 2011-01-31 2019-06-03 다다또모 스가 접합 기판 제작 방법, 접합 기판, 기판 접합 방법, 접합 기판 제작 장치 및 기판 접합체
JP6248458B2 (ja) * 2013-08-05 2017-12-20 株式会社Sumco 貼り合わせウェーハの製造方法および貼り合わせウェーハ

Also Published As

Publication number Publication date
FR3071663A1 (fr) 2019-03-29
JP2019062020A (ja) 2019-04-18
FR3071663B1 (fr) 2022-02-18

Similar Documents

Publication Publication Date Title
JP7115297B2 (ja) 多結晶ダイヤモンド自立基板及びその製造方法
JP7172556B2 (ja) 多結晶ダイヤモンド自立基板の製造方法
CN104488080B (zh) 混合基板的制造方法和混合基板
JPH09223782A (ja) Soi基板の製造方法
TW200913128A (en) Method for manufacturing SOI wafer
CN101106073B (zh) 用于稳定结合界面的热处理
TWI355711B (en) Method of producing simox wafer
TW201133615A (en) Wafer adhesion method
JP2020038916A (ja) Soiウェーハ及びその製造方法
JP2009253237A (ja) 貼り合わせウェーハの製造方法
TWI609434B (zh) SOS substrate manufacturing method and SOS substrate
JP6772995B2 (ja) Soiウェーハの製造方法およびsoiウェーハ
JP6825509B2 (ja) ダイヤモンド積層シリコンウェーハの製造方法およびダイヤモンド積層シリコンウェーハ
CN105264641B (zh) 贴合晶圆的制造方法
TWI643250B (zh) Method for manufacturing epitaxial wafer and epitaxial wafer
JP7480699B2 (ja) 多結晶ダイヤモンド自立基板を用いた積層基板及びその製造方法
EP4682936A1 (fr) Procédé de production de substrat semi-conducteur, substrat semi-conducteur et dispositif à semi-conducteur
JP7600973B2 (ja) 積層ウェーハ及びその製造方法
JP7238753B2 (ja) 接合ウェーハ及びその製造方法
JP2009289948A (ja) 貼り合わせウェーハの製造方法
EP4693369A1 (fr) Procédé de fabrication d'un substrat semi-conducteur, substrat semi-conducteur et dispositif à semi-conducteur
JP2019110225A (ja) 貼合せウェーハの製造方法および貼合せウェーハ

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20190925

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20200825

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20200901

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20200914

R150 Certificate of patent or registration of utility model

Ref document number: 6772995

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250