JP7524736B2 - SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD, AND STORAGE MEDIUM - Google Patents

Description

The present disclosure relates to a substrate processing apparatus, a substrate processing method, and a storage medium.

In the manufacturing process of semiconductor devices, semiconductor wafers (hereinafter referred to as wafers) are transported between various processing modules in a substrate processing apparatus, where they are subjected to processes such as liquid processing and heat treatment. Wafers are transported to the substrate processing apparatus by a carrier. Patent Document 1 shows a substrate processing apparatus equipped with a carrier block that transfers wafers to the carrier. In this carrier block, two transport mechanisms are provided to sandwich a stack consisting of multiple substrate placement sections, and each transport mechanism has a holding section for transferring wafers between the placement sections, and a holding section for transferring wafers to the carrier.

JP 2013-69916 A

This disclosure provides technology that can increase the throughput of substrate processing equipment while reducing the amount of floor space required.

The substrate processing apparatus according to the present disclosure includes a carrier block including a carrier placement portion on which a carrier for storing a substrate is placed;
a processing block including a plurality of processing modules each for processing the substrate, the processing block being stacked on top of one another, and a main transport mechanism shared by the plurality of processing modules for transporting the substrate, the processing block being provided on either the left or right side of the carrier placement unit in a plan view;
a plurality of processing modules each for processing the substrate, the processing modules being stacked on top of one another; and a main transport mechanism shared by the plurality of processing modules for transporting the substrate, the main transport mechanism being overlapped in a vertical direction with respect to the first processing block;
a transport region for the substrate provided in the carrier block so as to be interposed between the carrier placement part, the first processing block, and the second processing block in a plan view;
a first transport mechanism provided in the transport region for transferring the substrate to the carrier;
a stack of platform parts, which are configured so that a first platform part, a second platform part, and a third platform part to which the substrate is transferred by the first transport mechanism, the main transport mechanism of the one processing block, and the main transport mechanism of the other processing block, are stacked one on top of the other in the vertical direction, and which are provided on one of the front and rear sides of the first transport mechanism in a plan view;
a second transport mechanism that is provided in the transport region so as to sandwich the stack from the front and rear together with the first transport mechanism in a plan view, and that transports the substrate between the first placement part and the second placement part and between the first placement part and the third placement part, respectively;
Equipped with.

This disclosure can increase the throughput of substrate processing equipment while reducing the amount of floor space required.

2 is a cross-sectional plan view of a coating and developing apparatus according to an embodiment of the substrate processing apparatus of the present disclosure. FIG. FIG. 2 is a vertical sectional front view of the coating and developing apparatus. FIG. 2 is a vertical sectional front view of the coating and developing apparatus. FIG. FIG. 2 is a vertical sectional side view of the coating and developing apparatus. 5A to 5C are explanatory views showing the operation of a transport mechanism provided in the coating and developing apparatus. 5A to 5C are explanatory views showing the operation of a transport mechanism provided in the coating and developing apparatus. 5A to 5C are explanatory views showing the operation of a transport mechanism provided in the coating and developing apparatus. 2 is a schematic diagram of a transport path in the coating and developing apparatus. FIG. 2 is a schematic diagram of a transport path in the coating and developing apparatus. FIG. 3 is a schematic diagram showing an air flow formed in the coating and developing apparatus. FIG. 2 is a schematic diagram showing a wafer transport path in the substrate processing apparatus; FIG.

A coating and developing apparatus 1 according to one embodiment of a substrate processing apparatus of the present disclosure will be described with reference to the cross-sectional plan view of FIG. 1 and the longitudinal front views of FIG. 2 and FIG. 3, respectively. FIGS. 2 and 3 show cross sections at different positions of the apparatus. In the coating and developing apparatus 1, a carrier block D1, a first processing block D2, a second processing block D3, and an interface block D4 are arranged in this order in a horizontal line, with adjacent blocks connected to each other. These blocks (carrier block, first and second processing blocks, interface block) D1 to D4 are each provided with a housing and are partitioned from each other, and a transport area for the substrate, i.e., the wafer W, is formed inside each housing.

In the following explanation, the arrangement direction of these blocks D1 to D4 is referred to as the left-right direction, with the carrier block D1 side being the left side and the interface block D4 being the right side. In addition, in terms of the front-to-rear direction of the device, when looking at the carrier block D1 from the left, the front is referred to as the front and the back is referred to as the rear. The exposure machine 20 is connected from the right side to the interface block D4, which is a relay block.

Before describing each of blocks D1 to D4 in detail, the general configuration of the coating and developing apparatus 1 will be described. A wafer W is transported to the coating and developing apparatus 1 while stored in a carrier C, for example, called a FOUP (Front Opening Unify Pod). The coating and developing apparatus 1 forms a coating film by supplying various coating liquids, including resist, to the wafer W, and develops the resist film exposed by the exposure machine 20.

The first processing block (left processing block) D2 and the second processing block (right processing block) D3 are each partitioned vertically into two parts. The lower and upper sides of the first processing block D2 partitioned from each other in this way are respectively referred to as the first lower processing block D21 and the first upper processing block D22. The lower and upper sides of the second processing block D3 partitioned from each other are respectively referred to as the second lower processing block D31 and the second upper processing block D32. Therefore, the first lower processing block D21 and the first upper processing block D22 are stacked on top of each other, and the second lower processing block D31 and the second upper processing block D32 are stacked on top of each other. The first lower processing block D21 and the first upper processing block D22 are adjacent to each other, and the second lower processing block D31 and the second upper processing block D32 are adjacent to each other.

Each of these processing blocks (D21, D22, D31, D32) includes the above-mentioned processing modules and a transfer mechanism (main transfer mechanism) capable of transferring to and from the processing modules. Furthermore, the first upper processing block D22 and the second upper processing block D32 are each provided with a transfer mechanism separate from the transfer mechanism that transfers to the processing modules. Hereinafter, this separate transfer mechanism will be referred to as a shuttle. This shuttle is a bypass transfer mechanism that transfers the wafer W to a downstream block without passing through the processing modules, and the first upper processing block D22 and the second upper processing block D32 in which the shuttle is provided are bypass transfer path forming blocks.

The first lower processing block D21 and the second lower processing block D31 form an outbound path for transporting wafers W from the carrier block D1 to the interface block D4. The first upper processing block D22 and the second upper processing block D32 form a return path for transporting wafers W that have been exposed by the exposure machine 20 from the interface block D4 to the carrier block D1, and the same type of processing modules are provided so that the same processing can be performed in both blocks. On the return path, the wafers W are transported to a processing module by a transport mechanism in one of the first upper processing block D22 and the second upper processing block D32 to be processed, and are transported by a shuttle in the other block.

The first lower processing block D21 and the second lower processing block D31 that make up the outbound path may be collectively referred to as the lower processing block G1, and the first upper processing block D22 and the second upper processing block D32 that make up the return path may be collectively referred to as the upper processing block G2. As described above, the lower processing block G1 and the upper processing block G2 are vertically stacked on top of each other. As a result of the shuttle being provided as described above, the wafer W is transported in the upper processing block G2 via one of two transport paths. Note that a module is a location other than the transport mechanism (including the shuttle) where the wafer W is placed, i.e., a placement portion for the wafer W. A module that processes the wafer W is described as a processing module as described above, but this processing also includes acquiring images for inspection.

Below, carrier block D1 will be described with reference to the side view of FIG. 4. Carriers C are transported in and out of carrier block D1 by a carrier transport mechanism (external transport mechanism) (not shown) provided in the clean room in which coating and developing apparatus 1 is installed. Carrier block D1 transports wafers W in and out of carrier C, and is a block that transfers wafers W to upper processing block G2 and lower processing block G1.

The aforementioned housing constituting carrier block D1 is designated as 11. Housing 11 is formed in a rectangular shape, and its lower side protrudes to the left to form support base 12. Furthermore, on the left side surface of housing 11 above support base 12, two points spaced apart from each other in the vertical direction protrude to the left, forming support bases 13 and 14. The lower support base and the upper support base are designated as 13 and 14, respectively.

Each of the support bases 12 to 14 can accommodate carriers C, for example, four at a time, spaced apart in the front-to-rear direction, and each of the support bases 12 to 14 is provided with a stage on which the carriers C are placed, and the stages are arranged, for example, in a 3 x 4 matrix when viewed from the left. The left end of the support base 12 protrudes further left than the support bases 13 and 14, and the stage of the support base 12 is provided on the right side of the support base 12, below the support bases 13 and 14. The inside of the support base 12 is an area in which bottles containing processing liquid for liquid processing in the first processing block D2 and the second processing block D3 are stored, as described above.

The carrier C can be transferred between the stages by the carrier transfer mechanism 21, which will be described later. Regarding each stage, the two front stages of each of the support tables 13 and 14 are configured as moving stages 15 on which the carrier C is placed to load and unload the wafer W into and from the device. Therefore, a total of four moving stages 15 are arranged in a 2 x 2 matrix when viewed from the left. The moving stages 15 move between a load position on the right side for loading and unloading the wafer W and an unload position on the left side for transferring the carrier C to and from the carrier transfer mechanism 21. In this example, the moving stage 15 of the support table 12 is used as a stage on which the carrier C is placed to eject the unprocessed wafer W into the device, and the moving stage 15 of the support table 13 is used as a stage on which the carrier C is placed to store the processed wafer W in the device.

Regarding the other stages, the two rear stages on the support bases 13 and 14 and the two stages on the support base 14 are configured as temporary placement stages 16. The other two stages on the support base 14 are configured as the carry-in stage 17 and the carry-out stage 18. For example, the stage on the rear end side and the stage on the front end side of the support base 14 are the carry-in stage 17 and the carry-out stage 18, respectively. These carry-in stage 17 and carry-out stage 18 are stages on which the carrier C is placed so that the external transport mechanism described above can carry the carrier C in and out of the coating and developing device 1, respectively.

The carrier C is transferred in the following order: loading stage 17 → movable stage 15 of support base 12 → movable stage 15 of support base 13 → unloading stage 18. When transferring the carrier C between stages in this way, if the destination stage is not available (if it is occupied by another carrier C), the carrier C is placed on the temporary placement stage 16 and waits until the destination stage becomes available.

A carrier transfer mechanism 21 is provided above the left side of the support base 12. The carrier transfer mechanism 21 includes a multi-joint arm 22 that can hold a held part provided on the upper part of the carrier C, and a movement mechanism 23 that can move the multi-joint arm 22 up and down and back and forth, and can transfer the carrier C between stages as described above.

Four transfer ports 24 for loading and unloading wafers W are formed on the left side wall of the housing 11, arranged in a 2 x 2 matrix to match the arrangement of the moving stages 15. A door 25 is provided at each transfer port 24. The door 25 is capable of holding the lid of the carrier C on the moving stage 15 in the load position, and can move while holding the lid to open and close the transfer port 24.

The transfer port 24 faces a transfer area 31 for the wafer W formed in the housing 11. The transfer area 31 is formed in a long straight line in a plan view, and is provided between the moving stage 15, which is a carrier placement section, and the first processing block G2 in a plan view. A transfer mechanism 32 is provided on the front side (the other side of the front and rear) of the transfer area 31. The transfer mechanism 32 includes a base that can move back and forth, rise and fall, and rotate around a vertical axis, and a wafer W holder that can move forward and backward on the base. The transfer mechanism 32, which is the first transfer mechanism, can access the carrier C on the moving stage 15 at the load position already described, and the module stack T1 and pre-processing inspection module 41 described below to transfer the wafer W.

The carrier block D1 is provided with a third processing module, a pre-processing inspection module 41, which captures an image of the surface of the wafer W before processing by the coating and developing device 1. The image data obtained by the capture is sent to the control unit 10, which will be described later, and the presence or absence of an abnormality in the wafer W is determined by the control unit 10 based on the image data. The pre-processing inspection module 41 has a housing that is elongated and flat in the left-right direction, with the right side located in the center of the front and rear of the transport area 31 and the left side penetrating the left wall of the housing 11 and protruding outside the housing 11.

Inside the housing of the pre-processing inspection module 41, there are provided a stage 42 that can move left and right within the module, a half mirror 43 provided above the path of movement of the stage 42, an illumination unit 44 that irradiates light downward through the half mirror 43, and a camera 45 provided to the left of the half mirror 43 (see FIG. 3). The transport mechanism 32 delivers the wafer W to the stage 42 located on the right side of the housing. While the stage 42 to which the wafer W has been delivered moves to the left side of the housing and passes under the half mirror 43, light is emitted by the illumination unit 44 and an image of the wafer W reflected in the half mirror 43 is captured by the camera 45, and the above image data is acquired.

1, a second transfer mechanism, transfer mechanism 33, is provided in the transfer area 31, located behind the pre-processing inspection module 41 in a plan view. The transfer mechanism 33 includes a base that can be raised and lowered and rotated about a vertical axis, and a holder for a wafer W that can move forward and backward on the base, and can deliver the wafer W to and from the module stack T1 and the shuttle TRS12 of the first upper processing block D22, which will be described later.

Next, the module stack T1 will be described. This module stack T1 is configured by vertically stacking transfer modules TRS, which temporarily place wafers W, and temperature adjustment modules SCPL, and is provided in the center of the front and rear of the transfer area 31. Therefore, in a plan view, the module stack T1 is located behind the transfer mechanism 32, and is sandwiched between the transfer mechanisms 32 and 33 from the front and rear, and overlaps with the right side of the pre-processing inspection module 41. Therefore, in a plan view, the pre-processing inspection module 41 is configured to extend leftward from a position overlapping the stack T1. In addition, with regard to the stages for the carrier C described above, the two vertical rows of stages on the front side, including the moving stage 15, are arranged forward of the module stack T1. And, with regard to the two vertical rows of stages on the rear side, one row is located to the left of the module stack T1, and the other row is located behind the module stack T1.

The transfer module TRS has, for example, multiple pins arranged horizontally, and the wafer W is transferred to the pins by the lifting and lowering operation of the transfer mechanism. The SCPL is configured such that, for example, a refrigerant flow path is connected to a plate on which the wafer W is placed, thereby cooling the temporarily placed wafer W, and the wafer W is transferred to the plate by the lifting and lowering operation of the transfer mechanism. Note that SCPLs are also provided in blocks other than the carrier block D1, and the SCPLs in blocks other than D1 have the same configuration as, for example, the SCPL in carrier block D1. TRSs are also provided in blocks other than D1. These TRSs have the same configuration as the TRS in carrier block D1, except for the TRS for the shuttle that transfers the wafer W between the shuttle, which will be described later.

Hereinafter, in order to distinguish the SCPL and TRS at each location, which are temporary placement modules, numbers are added after the SCPL and TRS. For example, multiple TRS and SCPL are stacked at each location. In other words, multiple TRS and SCPLs with the same number are provided, but for convenience of illustration, only one is shown. In this specification, a stack of modules means modules that are stacked in a plan view, and the modules may be separated from each other or may be in contact with each other.

Some of the modules constituting the module stack T1 are provided below the pre-processing inspection module 41, and the other parts are provided above the pre-processing inspection module 41. For example, they are provided from bottom to top in the order of TRS1, TRS2, SCPL1, TRS3, and SCPL2, with the pre-processing inspection module 41 located between SCPL1 and TRS3 (see FIG. 3). For example, TRS1, TRS2, and SCPL1 are each located at the height of the first lower processing block D21, and TRS3 and SCPL2 are each located at the height of the first upper processing block D22. The transport mechanism 33 can access each of the modules constituting the module stack T1, and the transport mechanism 32 can access TRS1 and TRS2. In addition, with regard to the transfer of wafers W to carrier C and between modules in module stack T1, transfer mechanism 32 is dedicated to transfer to carrier C, and transfer mechanism 33 is dedicated to transfer between modules in module stack T1.

TRS1 and TRS2 are used to transfer wafers W between the transfer mechanisms 32 and 33, and are both first placement units used to transfer wafers W to and from carriers C. SCPL1 is used to transfer wafers W between the first lower processing block D21 and carrier block D1. Therefore, the second placement unit SCPL1 can also be accessed by the transfer mechanism 6A of the first lower processing block D21, which will be described later. In addition, the third placement unit TRS3 is used to transfer wafers W between the first upper processing block D22 and carrier block D1. Therefore, the transfer mechanism 6B of the first upper processing block D22, which will be described later, can also be accessed by TRS3. SCPL2 is a module for adjusting the temperature of wafers W before they are developed in the first upper processing block D22, and is accessed by the transfer mechanism 6B.

A hydrophobization processing module 30, which is a fourth processing module that supplies processing gas to the wafer W before the formation of a coating film, is provided on the rear side (either the front or rear side) of the transfer mechanism 33. For example, the hydrophobization processing modules 30 are stacked at the height of the second upper processing block D22, and the transfer mechanism 33 transfers the wafer W to and from the hydrophobization processing module 30. The hydrophobization processing module 30 includes a hot plate on which the wafer W is placed, similar to the hot plate 55 provided in the heating module 54 described later, and a cover that can be raised and lowered to cover the hot plate. The wafer W is hydrophobized by supplying processing gas to an enclosed space formed by the cover above the hot plate.

Next, the first processing block D2 will be described with reference to FIG. 5, which is a vertical side view. The front side of the first processing block D2 is vertically partitioned to form eight levels, which are numbered E1 to E8 from bottom to top. The lower levels E1 to E4 are included in the first lower processing block D21, and the upper levels E5 to E8 are included in the first upper processing block D22. Each level forms an area in which a liquid processing module can be installed.

First, the first upper processing block D22 will be described. Each of the levels E5 to E8 is provided with a developing module 51 as a liquid processing module. The developing module 51 is equipped with two cups 52 arranged side by side and each of which stores a wafer W, and a nozzle (not shown), and performs processing by supplying the developing liquid supplied from the bottle by a pump (not shown) to the surface of the wafer W.

A wafer W transfer area 53 is provided at the rear of levels E5 to E8, and is formed in a straight line in a plan view from the left end to the right end of the upper processing block D22. Therefore, the extension direction of the transfer area 53 is perpendicular to the extension direction of the transfer area 31 of the carrier block D1. The transfer area 53 is formed from the height of level E5 to the height of level E8. In other words, the transfer area 53 is not divided into levels E5 to E8.

Then, behind the transport area 53, the processing modules are stacked vertically in, for example, seven stages, and two stacks of these processing modules are arranged side by side. That is, the stacks of these processing modules and each of the cups 52 are arranged along the extension direction of the transport area 53.

The stack of processing modules arranged side by side as described above is the rear processing unit 50. The processing modules constituting the rear processing unit 50 include a plurality of heating modules 54 and a plurality of post-processing inspection modules 57. The heating module 54 is a module that performs post-exposure baking (PEB), and includes a hot plate 55 on which the wafer W is placed and heated, and a cooling plate 56 that adjusts the temperature of the wafer W. The cooling plate 56 can move between a front position where the wafer W is transferred by the lifting and lowering operation of the transfer mechanism 6B described below, and a rear position where it overlaps with the hot plate 55. The lifting and lowering operation of pins (not shown) provided on the hot plate 55 cooperates with the corresponding movement of the cooling plate 56 to transfer the wafer W between the hot plate 55 and the cooling plate 56.

The post-processing inspection module 57 has the same configuration as the pre-processing inspection module 41, and is arranged so that the movement direction of the wafer W during imaging is the forward and backward direction. This post-processing inspection module 57 acquires image data of the surface of the wafer W that has been processed by the coating and developing device 1, more specifically, the surface of the wafer W on which a resist pattern has been formed by development, and transmits the image data to the control unit 10.

The transport area 53, which is the main transport path, is provided with the transport mechanism 6B, which is the main transport mechanism described above. The transport mechanism 6B has a base 61 that can move left and right, rise and fall, and rotate around a vertical axis, and a holder 62 for the wafer W that can move forward and backward on the base 61. Note that each holder of the transport mechanisms other than the shuttle in the coating and developing apparatus 1, including this transport mechanism 6B, is provided with two holders, and can move forward and backward independently of each other on the base.

A moving mechanism 63 for moving the base 61 of the above-mentioned transfer mechanism 6B left and right is provided below the rear processing unit 50, and a flat space 71A is formed between the moving mechanism 63 and the rear processing unit 50 (see FIG. 5). The space 71A is formed from the left end to the right end of the first upper processing block D22. The shuttle and the TRS12 and TRS14 for the shuttle are installed in the space 71A, which will be described in detail later. The above-mentioned transfer mechanism 6B can transfer wafers W to and from each processing module in the first upper processing block D22, the TRS3 and SCPL2 of the above-mentioned carrier block D1, and the TRS14 for the shuttle. In other words, the transfer mechanism 6B is shared by each liquid processing module provided in the stacked multiple levels and each processing module constituting the rear processing unit 50.

Next, the first lower processing block D21 will be described. The first lower processing block D21 has a configuration generally similar to the first upper processing block D22 already described, and the following description will focus on the differences from the first upper processing block D22. There are no processing modules on level E1, and levels E2 to E4 have anti-reflective film formation modules 47 as liquid processing modules. The anti-reflective film formation module 47, which is the first processing module and also a coating film formation module, has a configuration similar to the developing module 51, which is the second processing module, except that it supplies a coating liquid for forming an anti-reflective film from a nozzle instead of a developing liquid.

The rear processing section 50 is composed of heating modules 54. However, unlike the heating modules 54 in the first upper processing block D22, the heating modules 54 in the first lower processing block D21 and the second lower processing block D32 described below are used to remove solvent from the coating film. The main transport mechanism in the transport region 53 is shown as transport mechanism 6A and has the same configuration as the transport mechanism 6B described above. The transport mechanism 6A delivers wafers W to each processing module in the first lower processing block D21, the SCPL1 of the module stack T1 described above, and the module stack T2 described below. The first lower processing block D21 does not have a shuttle or a TRS for the shuttle.

The first processing block D2 is provided with a module stack T2 (see FIG. 1 and FIG. 3). This module stack T2 is provided to the right of the transfer area 53 of the first lower processing block D21 and to the right of the transfer area of the second upper processing block D22, and is composed of SCPLs. The SCPL in the first lower processing block D21 is indicated as SCPL3, and the SCPL in the first upper processing block D22 is indicated as SCPL4. The module stack T2 is provided so that its right end portion slightly enters the second processing block D3. SCPL3 is for adjusting the temperature of the wafer W before processing in the resist film forming module of the second lower processing block D22 described later, and SCPL4 is for adjusting the temperature of the wafer W before processing in the developing module 51 of the second upper processing block D22 described later.

To add a bit more about the layout of the modules in the first upper processing block D22 and the first lower processing block D21, the rear processing section 50 and the cups 52 of the liquid processing modules are located to the left of the module stack T2 so that they can be transferred by the transport mechanisms 6A and 6B. The layout of the liquid processing modules and rear processing section 50 is common to the first and second lower processing blocks D21, D31 and the first and second upper processing blocks D22, D32. Therefore, in the second lower processing block D31 and second upper processing block D32 described below, the rear processing section 50 and the cups 52 of the liquid processing modules are also located away from the right end of the blocks.

Next, the second processing block D3 will be described. The second processing block D3 has a configuration similar to that of the first processing block D2, except that the module stack T2 is not provided. The following description will focus on the differences between the first processing block D2 and the second processing block D3. First, the second upper processing block D32 will be described. The main transport mechanism in the second upper processing block D32 is 6D. A space 71B similar to the space 71A in the first upper processing block D22 is also formed between the moving mechanism 63 that moves the transport mechanism 6D and the rear processing unit 50. The space 71B is located at the same height as the space 71A and is connected to the space 71A. The shuttle and the TRS11 and TRS13 for the shuttle are installed in the space 71B, which will be described later. The transport mechanism 6D transfers the wafer W to and from each processing module in the upper processing block D22, the module stack T3 of the interface block D4 described later, and the TRS11 for the shuttle.

Next, the second lower processing block D31 will be described. Resist film forming modules 49 are provided on levels E2 to E4. The resist film forming modules 49 have the same configuration as the developing module 51, except that the processing liquid supplied to the wafer W is resist instead of a developer. The rear processing section 50 has the same configuration as the rear processing section 50 of the first lower processing block D21. The main transport mechanism in the second lower processing block D31 is the transport mechanism 6C. The transport mechanism 6C delivers the wafer W to and from each processing module in the lower processing block D21 and the module stack T3 of the interface block D4.

The interface block D4 will be described below. The interface block D4 has a module stack T3 in the center between the front and rear. This module stack T3 is composed of TRS5 to TRS7 and a temperature adjustment module ICPL, which are stacked on top of each other. In addition to these modules, a buffer module for temporarily holding the wafer W is also provided, but its description is omitted. The ICPL is a module to which the wafer W is transferred immediately before exposure, and is provided on the lower side of the module stack T3, and adjusts the temperature of the wafer W placed thereon in the same way as the SCPL. TRS5 and TRS6 are provided at the height of the lower processing block G1, and TRS7 is provided at the height of the upper processing block G2. Transport mechanisms 36, 37, and 38 are provided at the front, rear, and right of the module stack T3, respectively.

Transfer mechanisms 36 and 37 are configured similarly to transfer mechanism 33, and are capable of transferring wafers W between each module constituting module stack T3. Transfer mechanism 36 is also capable of transferring wafers W to back surface cleaning module 65, which will be described later, and transfer mechanism 37 is also capable of transferring wafers W to shuttle TRS13 and post-exposure cleaning module 66, which will be described later. Transfer mechanism 38 is configured similarly to transfer mechanism 32, and transfers wafers W between ICPL, TRS6, and exposure machine 20.

Furthermore, multiple back surface cleaning modules 65 are stacked and provided in front of the transfer mechanism 36. The back surface cleaning module 65 has a configuration similar to that of the developing module 51, except that instead of a nozzle that supplies developing solution to the front surface of the wafer W, a nozzle that supplies cleaning solution to the back surface of the wafer W is provided, and there is only one cup 52. Multiple post-exposure cleaning modules 66 are stacked and provided behind the transfer mechanism 37. The post-exposure cleaning module 66 has a configuration similar to that of the developing module 51, except that instead of a nozzle that supplies developing solution to the front surface of the wafer W, a nozzle that supplies cleaning solution to the front surface of the wafer W is provided, and there is only one cup 52.

Next, the shuttles provided in the first upper processing block D22 and the second upper processing block D32 will be described as 7A and 7B, respectively. The shuttle 7A comprises a moving mechanism 72A, a moving body 73A, and a support 74A. The moving mechanism 72A is configured as a long member extending left and right, and is provided to fit into the space 71A of the first upper processing block D22 described above. The moving body 73A is connected to the front side of the moving mechanism 72A and extends left and right. The support 74A is connected to the front side of the moving body 73A and is formed in a rectangular parallelepiped shape that is elongated left and right. The wafer W is supported on this support 74A and transported in a horizontal straight line along the left and right directions.

The moving mechanism 72A allows the moving body 73A to move left and right relative to the moving mechanism 72A. In response to the movement of the moving body 73A relative to the moving mechanism 72A, the support 74A moves left and right relative to the moving body 73A (see Figures 6 to 8). The moving body 73A moves between a right position where its right end is located to the right (interface block D4 side) of the right end of the moving mechanism 72A and a left position where its left end is located to the left (carrier block D1 side) of the left end of the moving mechanism 72A. When the moving body 73A is located in the right position, the right end of the support 74A is located to the right of the right end of the moving body 73A (the state shown in Figure 6). The position of the support 74A in this state is called the right transport position. When the moving body 73A is located in the left position, the left end of the support 74A is located to the left of the left end of the moving body 73A (the state shown in Figure 8). The position of the support 74A in this state is called the left transport position.

The shuttle 7A transports the wafer W from the TRS11 provided in the second upper processing block D32 to the TRS12 (fourth placement unit) provided in the first upper processing block D22. The TRS11 includes a support plate 75 forming a placement unit body formed to form a recess with an open left side in a plan view, three pins 76 protruding upward from the support plate 75, and a lifting mechanism (not shown) for raising and lowering the support plate 75, and is located, for example, at the left end of the second upper processing block D32. The lifting mechanism may be, for example, an actuator such as a cylinder or a motor, and is connected to the back side (lower side) of each support plate 75 and is provided at a position that does not interfere with the movement trajectory of the moving body 73A or the support 74A. As the support plate 75 rises and falls, the pins 76 move between a raised position and a lowered position to support the lower surface of the wafer W. In the above-mentioned right transfer position, the right end of the support 74A is fitted in the above-mentioned recess formed by the support plate 75 in a plan view, and the wafer W can be transferred between the support 74A and the TRS11 by raising and lowering the pins 76.

TRS12 has the same configuration as TRS11, except that the support plate 75 is formed to have a recess that is open on the right side in plan view. The left end of the support 74A in the above-mentioned left transfer position is in a state of being accommodated in the above-mentioned recess formed by the support plate 75 in plan view, and the wafer W can be transferred between the support 74A and TRS12. TRS12 is provided at the left end of the first upper processing block D22 so that the wafer W can be transferred between the support 74A and the transfer mechanism 33 of the carrier block D1. As described above, the transfer of the substrate (wafer W) supported by the support 74 is performed while multiple members provided in the front-rear direction, such as the movable body 73A and the support 74A, change their relative left-right positions with respect to each other. By transferring the substrate in this manner, TRS11 and TRS12, which are located on the left and right sides of the support 74A, are less likely to interfere with the movable body 73A, and it is possible to arrange the pins 76 at three or more positions where the substrate can be easily supported.

Shuttle 7B, which is the second bypass transport mechanism, is provided at a different height than shuttle 7A, for example, located lower than shuttle 7A. Shuttle 7B is configured in the same way as shuttle 7A, and the reference numerals for the components of shuttle 7B, the moving mechanism, moving body, and support, are indicated with a B instead of an A after the numerals to distinguish them from the components of shuttle 7A. Specifically, for example, the moving mechanism of shuttle 7B is indicated as 72B. This moving mechanism 72B is provided to fit within space 71B of the second upper processing block D32.

Shuttle 7B transports wafers W from TRS13 provided in second upper processing block D32 to TRS14 provided in first upper processing block D22. TRS13 has the same configuration as TRS11, and is provided at the right end of second upper processing block D32 so that wafers W can be transferred between it and interface block D4. TRS14 has the same configuration as TRS12, and is provided to the left of module stack T2 and to the right of TRS12 so that wafers W can be transferred between it and transfer mechanism 6B.

As described above, shuttle 7B is provided below shuttle 7A, so the height at which the second bypass substrate placement parts TRS13 and TRS14 are located is lower than the height at which the first bypass substrate placement parts TRS11 and TRS12 are located. In other words, as shown in FIG. 2, the set of shuttle 7A, TRS11, and TRS12, and the set of shuttle 7B, TRS13, and TRS14 are provided at positions offset from each other in the longitudinal direction (vertical direction).

Then, the transport path (first bypass transport path) of the wafer W by the shuttle 7A and the transport path (second bypass transport path) of the wafer W by the shuttle 7B are 77A and 77B, respectively, and the front and rear positions of these transport paths 77A and 77B are the same. In correspondence with the positions of TRS11 to TRS14 described above, the transport path 77A protrudes into the second upper processing block D22, and the transport path 77B protrudes into the first upper processing block D22. By protruding in this way, the right side of the transport path 77A and the left side of the transport path 77B overlap each other in a plan view. Note that the transport paths 77A and 77B may be positioned, for example, outside the heat plate 55 of the heating module 54 and overlapping with the standby position of the cooling plate 56 in a plan view. By arranging the transport paths relatively far from the heat plate 55 in this way, the effect of heat on the transported wafer W can be more reliably suppressed.

The transfer of the wafer W by the shuttle 7A will be described step by step with reference to Figures 6 to 8. The transfer mechanism 6D of the second upper processing block D32 transfers the wafer W, which has been processed in each processing module in the second upper processing block D32, onto the pins 76 in the raised position of the TRS11. The pins 76 move to their lowered positions, and the wafer W is transferred to the support 74A in the right transfer position already described (Figure 6). While the movable body 73A and the support 74A each move to the left, the pins 76 of the TRS11 return to their raised position (Figure 7).

When support 74A moves to the left transfer position described above, pins 76 in the lowered position of TRS12 move to the raised position to support wafer W (Figure 8). When support 74A moves toward the right transfer position, pins 76 return to the lowered position. After that, transfer mechanism 33 of carrier block D1 receives wafer W. In this way, shuttle 7A transfers wafer W toward carrier block D1, which is a downstream block. Shuttles 7B, TRS13, and TRS14 also operate in the same way as shuttles 7A, TRS11, and TRS12, respectively, and wafer W is transferred from TRS13 to TRS14. In other words, shuttle 7B transfers wafer W toward first upper processing block D22, which is a downstream block.

The coating and developing apparatus 1 also includes a control unit 10 (see FIG. 1). The control unit 10 is configured as a computer, and includes a program, a memory, and a CPU. The program includes a set of steps that allow a series of operations in the coating and developing apparatus 1 to be performed. The program causes the control unit 10 to output control signals to each part of the coating and developing apparatus 1, thereby controlling the operation of each part. Specifically, the operation of the transport mechanisms 6A-6D, shuttles 7A and 7B, and each processing module is controlled. This allows the transport of the wafer W, the processing of the wafer W, and the determination of abnormalities in the wafer W, which will be described later. The above program is stored in a storage medium, such as a compact disc, a hard disk, or a DVD, and installed in the control unit 10.

Next, the processing and transport path of the wafer W in the coating and developing apparatus 1 will be described with reference to Figures 9 and 10, which respectively show the forward and return paths already mentioned. In Figures 9 and 10, the transport mechanism used for the transport is shown on or near some of the arrows representing the transport of the wafer W between modules.

First, the wafer W is removed by the transfer mechanism 32 from the carrier C placed on the moving stage 15 of the support table 12. The wafer W is then transferred by the transfer mechanism 32 to the pre-processing inspection module 41, where image data is acquired and the presence or absence of abnormalities is determined.

Then, the wafer W is transferred to TRS1 by the transfer mechanism 32. After that, the wafer W is transferred by the transfer mechanism 33 to the hydrophobization processing module 30 and then to SCPL1, and then taken into the first lower processing block D21 by the transfer mechanism 6A, and is transferred in the order of anti-reflection film forming module 47 → heating module 54, where an anti-reflection film is formed. The wafer W is then transferred to SCPL4 of the module stack T2, and is transferred by the transfer mechanism 6C in the order of resist film forming module 49 → heating module 54, where a resist film is formed. The wafer W is then transferred to TRS5 of the module stack T3.

Then, the wafer W is transported by the forward transport mechanism 36 through the back surface cleaning module 65 and ICPL, and then by the transport mechanism 38 to the exposure machine 20, where the resist film on the front surface of the wafer W is exposed according to a predetermined pattern. After exposure, the wafer W is transported by the transport mechanism 38 to the TRS 6, and then by the rear transport mechanism 37 to the post-exposure cleaning module 66.

The wafer W is then transported through a path that undergoes processing in the first upper processing block D22 (referred to as the first path) and a path that undergoes processing in the second upper processing block D32 (referred to as the second path) as described above. Regarding the second path, the transport mechanism 37 transports the wafer W to TRS7 of the module stack T3, and the wafer W is taken into the second upper processing block D32 by the transport mechanism 6D. The wafer W is then transported through the heating module 54 → SCPL3 → developing module 51 → post-processing inspection module 57 in that order, and after a resist pattern is formed, image data is acquired and the presence or absence of abnormalities is determined.

Then, as explained in Figures 6 to 8, the wafer W is transported in the order of transport mechanism 6D → TRS11 → shuttle 7A → TRS12, and then the transport mechanism 33 of carrier block D1 receives the wafer W and transports it to TRS2. In this way, the wafer W is transported toward the downstream block by shuttle 7A and 6D, out of transport mechanisms 6B and 6D that are the main transport mechanisms of the first upper processing block D22 and the second upper processing block D22, which are bypass transport path forming blocks. The wafer W is then stored in carrier C on moving stage 15 of support table 13 by transport mechanism 32.

Next, regarding the first path, the wafer W is transported in the order of the transport mechanism 37 → TRS13 → shuttle 7B → TRS14 → transport mechanism 6B, and the wafer W is taken into the first upper processing block D22. The wafer W is then transported by the transport mechanism 6B in the order of the heating module 54 → SCPL2 → developing module 51 → post-processing inspection module 57, and after undergoing processing in the same manner as the wafer W on the second path, it is transported to TRS3 of the carrier block D1. In this way, the wafer W is transported toward the downstream block by the transport mechanisms 6B and 6D, which are the main transport mechanisms of the first upper processing block D22 and the second upper processing block D22, which are bypass transport path forming blocks, and the shuttle 7B. The wafer W is then transported to TRS2 by the transport mechanism 33, and thereafter, like the wafer W on the second path, it is transported by the transport mechanism 32 to the carrier C on the moving stage 15 of the support table 13.

As described above, the carrier block D1 in the coating and developing apparatus 1 is provided with a module stack T1 including TRS and SCPL for transferring the wafer W to the carrier C, the lower processing block (one processing block) G1, and the upper processing block (another processing block) G2. Then, the transport mechanisms 32 and 33 are provided, with the transport mechanism 32 handling transfer to the carrier C, and the transport mechanism 33 handling transfer between modules of the module stack T1. By dividing the roles of the transport mechanism 32 and the transport mechanism 33 in this way, the transport mechanism 32 can quickly load and unload the wafer W to and from the carrier C. On the other hand, in each of the processing blocks D21, D22, D31, and D32 constituting the lower processing block G1 and the upper processing block G2 to which the wafer W is transferred via the transport mechanism 33, processing modules are stacked, and the wafer W can be processed in each processing module. Therefore, the coating and developing apparatus 1 can obtain a high throughput. Furthermore, the transfer area 31, which faces the transfer port 24 through which the wafer W is transferred to the carrier C, extends in the front-to-rear direction, and the transfer mechanisms 32 and 33 are provided in the front and rear of the module stack T1 in this transfer area 31, respectively, making it possible to make the left-to-right width of the carrier block D1 relatively small. Therefore, the coating and developing apparatus 1 can reduce the footprint (occupied floor area).

The carrier block D1 is provided with a pre-processing inspection module 41. The right end of this pre-processing inspection module 41 overlaps with the module stack T1 and penetrates the side wall of the housing 11, so that its left end protrudes from the transport area 31. In other words, the pre-processing inspection module 41 is arranged by utilizing the space formed in the center of the front and rear of the transport area 31 by arranging the module stack T1, and the space outside the housing 11 where the carrier C is transferred. In other words, the pre-processing inspection module 41 is installed in the carrier block D1, while preventing an increase in the footprint of the carrier block D1.

Furthermore, a hydrophobization treatment module 30 is arranged as a treatment module behind the transfer mechanism 33, and is accessible by the transfer mechanism 33. This arrangement of the hydrophobization treatment module 30 also prevents the width of the coating and developing apparatus 1 from increasing in the left and right directions. The transfer mechanism 33 delivers the wafer W to the hydrophobization treatment module 30, and the transfer mechanism 32 delivers the wafer W to the pre-treatment inspection module 41. This prevents uneven load distribution between the transfer mechanisms 32 and 33, and prevents a decrease in throughput due to the provision of these treatment modules. However, the transfer mechanism 33 may also be configured to deliver the wafer W to the pre-treatment inspection module 41.

Furthermore, when providing multiple movable stages 15 on which carriers C are placed for loading and unloading wafers W, the movable stages 15 are provided in multiple stages on the front side of the module stack T1. By arranging the movable stages 15 so that they are concentrated on the front side of the module stack T1 in this manner, it is possible to install the number of movable stages 15 required to ensure sufficient throughput, while allowing the center of the front and rear of the transfer area 31 to be used as an installation area for the module stack T1 and pre-processing inspection module 41. By arranging the module stack T1 in this manner, the transfer mechanism 33 can be arranged behind it. Therefore, as already described, providing each movable stage 15 on the front side of the module stack T1 and at different heights from each other contributes to reducing the footprint of the device while increasing throughput.

By providing the temporary placement stage 16, which is a temporary placement section for carriers, unnecessary carriers C can be evacuated from the moving stage 15, so that wafers W can be loaded and unloaded efficiently from the carriers C. In the carrier block D1, the temporary placement stage 16 is provided at the same position as the module stack T1 in the front-to-rear direction, and at a rear position relative to the module stack T1. In other words, by providing the moving stage 15 in the layout already described, the temporary placement stage 16 is provided by utilizing the empty space that is not accessed by the transport mechanism 32. In other words, the temporary placement stage 16 is arranged in a layout that prevents the carrier block D1 from becoming too large.

Furthermore, the coating and developing apparatus 1 is provided with shuttles 7A and 7B, which transport the wafer W toward the carrier block D1. As a result, the wafer W that is processed in one of the first upper processing block D22 and the second upper processing block D32 is transported toward the carrier block D1 so as to bypass the processing modules of the other block. Therefore, the load on the transport mechanism 6B of the first upper processing block D22 and the transport mechanism 6D of the second upper processing block D32 (more specifically, the number of transport processes required within the block) is reduced. As a result, the throughput of the coating and developing apparatus 1 can be further improved.

By the way, airflow forming units (not shown) are provided on the top of the housing 11 of the carrier block D1, on the top of each housing of the first and second processing blocks D2 and D3, and on the top of the housing of the interface block D4. Each airflow forming unit takes in air from outside the coating and developing apparatus 1 and supplies it to the transport path of the wafer W in the block in which the airflow forming unit is provided, thereby forming an airflow. In FIG. 11, the airflow forming units of the carrier block D1 and the second processing block D22 are shown as 81 and 82, respectively. For convenience of illustration, these airflow forming units 81 and 82 are shown in positions away from the carrier block D1 and the first processing block D2, respectively.

The airflow forming unit 82 supplies air via a duct (not shown) to filters installed in the ceiling of each transport area 53 of the first lower processing block D21 and the first upper processing block D22 that make up the first processing block D2. The air supplied from the filters flows downward through the transport area 53 and is exhausted from exhaust ports (not shown) installed on the lower side of the first lower processing block D21 and the first upper processing block D22 (not shown).

For example, in carrier block D1, as shown in FIG. 11, a vertically long filter 83 is provided at the front end of the transport area 31. Air supplied from the airflow forming unit 81 to the filter 83 is supplied from the filter 83 toward the rear of the transport area 31. An exhaust hole 84 is opened, for example, at the bottom of the block behind the module stack T1, and the air supplied from the filter 83 is exhausted from the exhaust hole 84.

By adjusting the balance of the air supply amount and exhaust amount in each block, the first lower processing block D21 and the first upper processing block D22 are made to have a higher pressure than the transport area 31. As a result, a part of the air supplied to the transport area 53 as described above flows into the transport area 31 and is exhausted from the exhaust hole 84. In FIG. 11, the airflow formed in the transport areas 31 and 53 in this manner is indicated by arrows. The airflow formed in this manner more reliably prevents the processing gas used in the hydrophobization processing module 30 from flowing into the transport area 31. If the processing gas flows into the development module 51 through the transport area 31 and reacts with the developing solution, there is a risk of developing defects occurring, but the formation of the above airflow prevents such defects from occurring. In other words, the formation of the airflow prevents a decrease in the yield of products manufactured from the wafer W. The filter 83 and the airflow forming units 81 and 82 form an airflow forming mechanism.

However, instead of the pre-processing inspection module 41, a post-processing inspection module 57 may be provided at the position where the pre-processing inspection module 41 is provided. In that case, the outward route described in FIG. 9 may be a route that does not involve transport to the inspection module. Specifically, the wafer W may be transported in the order of carrier C → transport mechanism 32 → TRS1 → transport mechanism 33 → SCPL1 and loaded into the first lower processing block D21. The return route described in FIG. 10 may go through the post-processing inspection module 57 provided in the carrier block D1 in the same way. Specifically, the wafer W that has been processed and transported to TRS2 of the carrier block D1 may be transported by the transport mechanism 32 to the post-processing inspection module 57 and then returned to the carrier C.

When the post-processing inspection module 57 is arranged in the carrier block D1 in this manner, the pre-processing inspection module 41 may be provided as a processing module constituting, for example, the rear processing section 50 of the first lower processing block D21. Note that the carrier block D1 may be configured without either the pre-processing inspection module 41 or the post-processing inspection module 57, and in this case, the wafers W may be transferred between the transfer mechanisms 32 and 33 using each module of the module stack T1 to be transferred as appropriate.

In the above transfer example, the moving stage 15 (loader) on which the carrier C is placed to unload the wafer W is different from the moving stage 15 (unloader) on which the carrier C is placed to load the wafer W. However, one moving stage 15 may serve as both a loader and an unloader. The above transfer mechanism 32 is configured to be shared by four moving stages 15, which has the advantage that the use of the moving stages 15 can be easily switched in this way.

In addition, in the coating and developing apparatus 1, the upper processing block G2 may be the outgoing path of the wafer W, and the lower processing block G1 may be the return path of the wafer W. Specifically, for example, the anti-reflection film is not formed in the apparatus, and a resist film forming module 49 is provided as a liquid processing module in each of the first upper processing block D22 and the second upper processing block D32. A developing module 51 is provided as a liquid processing module in each of the first lower processing block D21 and the second lower processing block D31. The wafer W may be transported between the blocks on a transport path reverse to the transport path described above, and the resist film may be formed, exposed, and developed in order to form a resist pattern. Therefore, the shuttle is not limited to forming a return path, and the carrier block D1 is not limited to being configured to transfer the wafer W to the shuttle TRS that forms the return path. The shuttle may also be provided in the first lower processing block D21 and the second lower processing block D31. For example, the liquid processing modules of the first lower processing block D21 and the second lower processing block D31 are both resist film forming modules 49, and the apparatus can be configured so that a wafer W is processed in the resist film forming module 49 of one of the blocks using a shuttle.

In addition, the liquid processing performed by the apparatus is not limited to the above examples, and may include forming an insulating film by applying a chemical liquid, forming a protective film to protect the surface of a resist film by applying a chemical liquid, and applying an adhesive to bond wafers W to each other. A cleaning process may also be performed in which a cleaning liquid is supplied to the front or back surface of the wafer W. Therefore, the substrate processing apparatus of this technology is not limited to a coating and developing apparatus.

Furthermore, the lower processing block G1 and the upper processing block G2 do not have to be connected to each other by the interface block D4. The description will be made with reference to the schematic diagram of the substrate processing apparatus 8 in FIG. 12. Assume that the module stack T1 includes TRS21 to TRS23. TRS21 is for delivery to the carrier C, and the wafer W is transported between the carrier C and TRS21 by the transport mechanism 32. TRS22 and TRS23 are for delivery to the lower processing block G1 and the upper processing block G2, and the wafer W is transported between TRS21-TRS22 and between TRS21-TRS23 by the transport mechanism 33, respectively. The wafer W that is loaded from the carrier C via TRS21 to TRS22, and from TRS23 to the lower processing block G1 and the upper processing block G2, respectively, is returned to the carrier C via TRS22 and TRS23 to TRS21 after processing. In other words, the apparatus may be configured so that the wafer W is processed in only one of the lower processing block G1 and the upper processing block G2 and then returned to the carrier C.

Furthermore, each of the lower processing block G1 and the upper processing block G2 is not limited to being composed of two processing blocks arranged side by side, but may be composed of one processing block. Furthermore, each of the lower processing block G1 and the upper processing block G2 may be composed of three or more processing blocks arranged side by side, and the wafer W may be transported between the processing blocks arranged side by side.

In each processing block, the liquid processing module is located at the front and the processing module constituting the rear processing section 50 is located at the rear, but this layout may be reversed. In addition, in the carrier block D1, the layout of the transport mechanisms 32, 33 and each stage for the carrier C may be reversed. In addition, the arrangement of the carrier block D1 and the other blocks may also be reversed.

In the carrier block D1, other modules such as a post-treatment inspection module 57 may be provided instead of the hydrophobic treatment module 30, and the transfer may be performed by the transfer mechanism 33. However, the hydrophobic treatment module 30 does not need to move the placement part (hot plate) on which the wafer W is placed laterally when performing the treatment. In other words, when providing a treatment module behind the transfer mechanism 33, it is preferable to provide a treatment module that performs treatment without moving the placement part for the wafer W laterally in this way in order to prevent the carrier block D1 from becoming large, and thus the substrate processing apparatus from becoming large. Note that the order of the TRS and SCPL that make up the module stack T1 may be changed in height or stacked order as appropriate within the range in which the wafer W can be transported within the apparatus.

The hydrophobic processing module 30 may be arranged so as to overlap the TRS and SCPL that form the module stack T1. However, by arranging a large number of TRS and SCPL in the module stack T1 and placing the wafer W thereon, the transfer of the wafer W between the carrier block D1 and the first processing block D2 and between the carrier C and the carrier block D1 can be performed quickly. Therefore, as described above, it is preferable to arrange the hydrophobic processing module 30 on the rear side of the transfer area 31. Furthermore, in the coating and developing apparatus 1, after the transfer mechanism 32 transfers the wafer W to the pre-processing inspection module 41, the transfer mechanism 33 may receive the wafer W at the inspection module 41, transfer it to the SCPL1, and the wafer W may be taken into the lower processing block D21. In other words, the transfer of the wafer W between the transfer mechanisms 32 and 33 is not limited to being performed by the temporary placement module.

The embodiments disclosed herein should be considered in all respects as illustrative and not restrictive. The above-described embodiments may be omitted, substituted, modified, and combined in various forms without departing from the scope and spirit of the appended claims.

C carrier D2 first processing block D21 first lower processing block D22 first upper processing block 15 moving stage TRS transfer module T1 module stack W wafer 31 transfer area 32, 33 transfer mechanism 6A, 6B, 6C, 6D transfer mechanism

Claims (15)

a carrier block including a carrier placement portion on which a carrier for storing a substrate is placed;
a processing block including a plurality of processing modules each for processing the substrate, the processing block being stacked on top of one another, and a main transport mechanism shared by the plurality of processing modules for transporting the substrate, the processing block being provided on either the left or right side of the carrier placement unit in a plan view;
a plurality of processing modules each for processing the substrate, the processing modules being stacked on top of one another; and a main transport mechanism shared by the plurality of processing modules for transporting the substrate, the main transport mechanism being overlapped in a vertical direction with respect to the first processing block;
a transport region for the substrate provided in the carrier block so as to be interposed between the carrier placement part, the first processing block, and the second processing block in a plan view;
a first transport mechanism provided in the transport region for transferring the substrate to the carrier;
a stack of platform parts, which are configured so that a first platform part, a second platform part, and a third platform part to which the substrate is transferred by the first transport mechanism, the main transport mechanism of the one processing block, and the main transport mechanism of the other processing block, are stacked one on top of the other in the vertical direction, and which are provided on one of the front and rear sides of the first transport mechanism in a plan view;
a second transport mechanism that is provided in the transport region so as to sandwich the stack from the front and rear together with the first transport mechanism in a plan view, and that transports the substrate between the first placement part and the second placement part and between the first placement part and the third placement part, respectively;
A substrate processing apparatus comprising: The processing module of the one processing block and the processing module of the other processing block are respectively referred to as a first processing module and a second processing module.
The substrate processing apparatus according to claim 1 , further comprising a third processing module to which the substrate is transferred by the first transport mechanism or the second transport mechanism, the third processing module being disposed at a position overlapping the stack in a plan view. The substrate processing apparatus of claim 2, wherein the third processing module is an inspection module for inspecting the substrate. The substrate processing apparatus according to claim 3, wherein the inspection module extends to the other of the left and right sides from a position overlapping the stack in a plan view and protrudes outside the housing that forms the transport area. A substrate processing apparatus according to claim 3 or 4, in which the inspection module transports the substrate before it is transported to the first processing block and the second processing block. a fourth processing module to which the substrate is transferred by the second transfer mechanism is provided at one of the front and rear sides of the second transfer mechanism;
6. The substrate processing apparatus according to claim 2, wherein the substrate is transferred to the third processing module by the first transfer mechanism. a fourth processing module to which the substrate is transferred by the second transfer mechanism is provided at one of the front and rear sides of the second transfer mechanism;
The processing module of the one processing block and the processing module of the other processing block are respectively referred to as a first processing module and a second processing module.
the plurality of first processing modules or the plurality of second processing modules includes a coating film forming module that supplies a coating liquid to the substrate to form a coating film;
7. The substrate processing apparatus according to claim 1, wherein the fourth processing module is a hydrophobization processing module which performs a gas processing on the substrate to hydrophobize the substrate before the coating liquid is supplied. A substrate processing apparatus as claimed in claim 7, further comprising an airflow forming mechanism for forming an airflow from the other side of the transport area toward the fourth processing module and an airflow from the first processing block and the other processing block toward the transport area. A substrate processing apparatus according to any one of claims 1 to 8, wherein the carrier placement section is provided at multiple positions at different heights on the other side of the stack, front or rear. On one of the left and right sides of the transport area,
a temporary placement portion for a carrier, the temporary placement portion being provided at the same position as the stack in the front and rear or on one side of the stack in the front and rear;
The substrate processing apparatus according to claim 9 , further comprising: a carrier transfer mechanism that transfers the carrier between the temporary placement unit and the carrier placement unit. a relay block including a lifting and lowering mechanism for transporting the substrate between the first processing block and the second processing block is connected to one of the left and right sides of the first processing block and the second processing block;
11. A substrate processing apparatus as described in any one of claims 1 to 10, wherein the substrate is transported on an outward route from the carrier block via the one processing block to the relay block, and on a return route from the relay block to the carrier block via the other processing block. A substrate processing apparatus as described in claim 11, wherein at least one of the first processing block and the second processing block is provided with a third transport mechanism separate from the main transport mechanism and a fourth placement section on which the substrate is temporarily placed in order to transfer the substrate between the third transport mechanism and the second transport mechanism. at least one of the one processing block and the other processing block includes the plurality of stacked processing modules and the main transport mechanism, and is configured with a left processing block and a right processing block arranged side by side,
The substrate processing apparatus according to claim 12 , wherein the third transport mechanism is provided in each of the left processing block and the right processing block to transport the substrate toward a downstream block without passing through the processing module. placing a carrier for storing substrates on a carrier placement portion provided on a carrier block;
a process for transporting the substrate in a processing block provided on either the left or right side of the carrier placement unit in a plan view, the processing block including a plurality of processing modules stacked on top of each other and each processing the substrate, and a main transport mechanism shared by the plurality of processing modules and transporting the substrate;
a step of transporting the substrate in another processing block that overlaps the first processing block in a vertical direction, the processing block including a plurality of processing modules that process the substrate and are stacked on top of each other and a main transport mechanism that is shared by the plurality of processing modules and transports the substrate;
a step of transferring the substrate to the carrier by a first transport mechanism provided in a substrate transport region provided in the carrier block so as to be interposed between the carrier placement part, the first processing block, and the second processing block in a plan view;
a step of transferring the substrate to a first mounting portion, a second mounting portion, and a third mounting portion which are configured to be stacked on top of each other in the vertical direction and which constitute a stack of mounting portions provided on one of the front and rear sides of the first transport mechanism in a plan view, by the first transport mechanism, a main transport mechanism of the one processing block, and a main transport mechanism of the other processing block, respectively;
a step of transporting the substrate between the first placement part and the second placement part and between the first placement part and the third placement part by a second transport mechanism provided in the transport region so as to sandwich the stack from the front and rear together with the first transport mechanism in a plan view;
A substrate processing method comprising: A storage medium for storing a computer program for use in a substrate processing apparatus,
15. A storage medium, wherein the computer program is a set of steps for executing the substrate processing method according to claim 14.

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