JPH01100643A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the competition of and output by a wired OR line by the outputs of plural devices by preventing signals from becoming an active condition simultaneously by a NAND gate. CONSTITUTION:External device active signals 1, 2...4 are high-potential active and device active signals 6, 7...9 are low-potential active. Now, the overlapping of the active time of the signals 1...4 in the conversion from the signals 1...4 into the signals 6...9 is between signals 1-4, 1-2, 2-3 and 3-4. There, for the example of the signal 1-4, when the signal 4 is 'L', the signal 9 becomes 'H' surely. By obtaining the NAND of the signals 9 and 1, the signal 6 becomes 'L' only when the signal 1 is 'H' and the signal 9 is 'H'. Consequently, when the signal 4 is 'H', the signal 6 does not become 'L'. It is the same between the signal 1-2, 2-3, and 3-4 and the signals 6...9 do not become active simultaneously. It is the same when the signal 1...4 are low potential.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to semiconductor integrated circuits, and particularly to prevention of competition between outputs of semiconductor memories in a system that performs wired OR output of semiconductor memories.

[Conventional technology]

Figure 9 shows a conventional semiconductor integrated circuit device.
R circuit diagram, FIG. 10 is a signal waveform diagram showing the operation of a conventional semiconductor integrated circuit device. In the figure, Qo, (b),
a2. (to) is a semiconductor memory device, α→, (g).

αQ and α power are output terminals from each device, and data bus line with wired OR connection, as
, m, aI), (a) is a signal terminal that activates the semiconductor memory device from the outside when the logic of the signal is inverted, (to) is the device α0 and (2), (b) is the device a [and (b) and (to) are devices (b) and (2),
(to) indicates a period during which the outputs of devices (a) and (to) compete.

Next, the operation will be explained. The device active signal that enables output from the device normally appears at the output terminal when it is at a low potential. Therefore, during period (1), the signal terminal US activates the semiconductor memory device from the outside when the logic of the signal is inverted.

Since both (a) are in the low potential active state, the device (l
A conflict occurs between the outputs of a(to). Similarly period 6】)
is the device (to, αD output contention occurs, and the period (
b) There is a conflict between the outputs of devices Q◇ and @, and during the period)
This causes a conflict between the outputs of device (2) and Qal.

[Problem that the invention seeks to solve]

The wired OR circuit of a conventional semiconductor integrated circuit device is configured as described above, so if two or more signals become active due to synchronization difference between each signal, competition of outputs from the device will occur during that period. There were problems such as causing

This invention was made to solve the above-mentioned problems, and the signal for activating the device is two at the same time.
An object of the present invention is to obtain a semiconductor integrated circuit that does not become active for more than one time.

[Means for solving problems]

The semiconductor integrated circuit according to the present invention is provided in front of a terminal that puts the device into an active state.
NAN output of a signal whose active state is close to that of an external device active signal using an ND gate circuit
I got a D.

[Effect]

The semiconductor integrated circuit according to the present invention uses a NAND gate and prevents signals from becoming active at the same time, thereby preventing output competition due to wired OR connection of the outputs of a plurality of devices. ] Hereinafter, one embodiment of the present invention will be described with reference to the drawings. 1st
The figure is a wired OR circuit diagram showing a semiconductor integrated circuit according to an embodiment of the present invention. In Figure 1, (1)
, (21, (3), (/f) is the signal terminal that activates the device from the outside, (5) is the signal terminal from (1) to (
4) A signal conversion circuit that adjusts the signal waveforms up to 4). (6)
, (7).

(81, (9) is the semiconductor memory device fIo), (9)
, (2), and (6) are activated.

Next, the operation will be explained. FIG. 2 shows details of the signal conversion circuit (5) in the wired OR circuit diagram as shown in FIG. Further, the voltage waveforms of each signal are shown in FIG.

External device active signal (1), (2),
(31, (4) are assumed to be active at high potential, and device active signals (6), (7), (8)
, (9) are active at low potential, here, the signal (11, (21, (31, (41) to signal (6
), (7), (8), (93 conversion is as follows. Signals (1), (2), (3)
, (4) is activated and the stone signal is (1) -(4) , +1) -+2) , +2)
-+3), (3) -(4). Therefore, taking the signals (1) to (4) as an example, when the signal (4) is "L" (non-active), the signal (9) is always 1H" (non-active).

By NANDing the signals (9) and (1), the signal (6) is determined when the signal (1) is "H# (active)" and the signal (9) is "H# (active)".
) becomes 1L" (active) only when it is 'H' (non-active). Therefore, signal (4) is vIH#
(when active), signal (6) does not become 1L# (active) L signal (1) - (21, +2) - (3
), (3) and (4) in the same way, signals (6), (7), (8), and (9) will not be active at the same time, and the data will be on the data bus at (to). There will be no longer any period of commonality.

The above explanation was based on the case of 4 devices, but
Similar effects can be obtained for other numbers by increasing the number of NAND gates shown in FIG.

Also, in the above embodiment, the external active signal (1).

+21, (31, (The case where 41 is active at a high potential has been described, but the case where it is active at a low potential will be described below. The external active signals (II, m, @, @ are active at a low potential) are described below. Here, the signals (6), (7), (8), (9
), as shown in Figure 4, the signals (to), (a),
If 0° C. and @ are inverted by an inverter, the voltage waveform as shown in FIG. 5, which is the same as in the above embodiment, will be obtained, and the same effect will be obtained.

In addition, for an embodiment in which there are two devices, the external device active signal is set to one as shown in FIGS. 6 and 7.
can be made into The signal voltage waveform at this time is
As shown in the figure. Since the operation is exactly the same as in the above embodiment, the explanation will be omitted.

〔Effect of the invention〕

As described above, according to the present invention, by adding the semiconductor integrated circuit to a wired OR-coupled circuit, there is an effect that there is no need to take a margin between signals for activating the active device. This has the effect that no output contention occurs.

[Brief explanation of the drawing]

FIG. 1 is a wired OR circuit diagram showing a semiconductor integrated circuit according to an embodiment of the present invention, FIG. 2 is a signal conversion circuit diagram showing a semiconductor integrated circuit according to an embodiment of the invention, and FIG. 3 is a diagram showing a semiconductor integrated circuit according to an embodiment of the invention. FIG. 4 is a signal waveform diagram showing the operation of the semiconductor integrated circuit according to the embodiment. FIG. 4 is a signal conversion circuit diagram showing the semiconductor integrated circuit according to another embodiment of the invention. FIG. 5 is a semiconductor integrated circuit according to another embodiment of the invention. A signal waveform diagram showing the operation of the circuit, FIG. 6 is a wired OR circuit diagram showing a semiconductor integrated circuit according to another embodiment of the invention, and FIG. 7 is a signal conversion diagram showing a semiconductor integrated circuit according to another embodiment of the invention. circuit diagram,
FIG. 8 is a signal waveform diagram showing the operation of a semiconductor integrated circuit according to another embodiment of the present invention, FIG. 9 is a wired OR circuit diagram showing a conventional semiconductor integrated circuit device, and FIG. 10 is a conventional semiconductor integrated circuit device. In the signal waveform diagram showing the operation of 0, (1), +21, (31, (4)
is the signal terminal that activates the device from the outside, (
5) is a signal conversion circuit, (6), (7), (8)
, (9) is a signal terminal for activating an internal device, α(11,Ql), U, Ql are semiconductor memory devices,
α→, (to), αQ, αη are output terminals from the semiconductor memory device, (to) is a wired OR-connected data path line, as, m, a]), (a) is the inversion of the signal logic The signal terminal that activates the semiconductor memory device from the outside when it is activated, the signal terminal that activates the semiconductor memory device with one signal from the outside, (c), ni) is the signal that activates the internal semiconductor memory terminal,
(E), @ is the output terminal from the semiconductor memory device, (E)
is the wired OR-connected data path line, 翰 is the semiconductor memory device, (to) is the period when the outputs of device 001 and (to) are competing, and aη is the period when the outputs of device (1(+1) and (b) are During the contention period, (2) is the device (
The period in which the outputs of (b) and (2) are competing with each other, and (to) is the period in which the outputs of devices (6) and (to) are competing with each other. In addition, in the figures, the same symbols indicate the same or corresponding parts.

Claims (2)

[Claims] (1) A semiconductor integrated circuit characterized in that, in a system that performs wired OR output of semiconductor memories, a signal for activating each semiconductor memory is applied to the system through one NAND gate. (2) The semiconductor integrated circuit according to claim 1, wherein one inverter gate is added in front of each NAND gate by inverting the logic of each active signal.