JPH01100676A - Video binarization method - Google Patents

Video binarization method

Info

Publication number
JPH01100676A
JPH01100676A JP62257154A JP25715487A JPH01100676A JP H01100676 A JPH01100676 A JP H01100676A JP 62257154 A JP62257154 A JP 62257154A JP 25715487 A JP25715487 A JP 25715487A JP H01100676 A JPH01100676 A JP H01100676A
Authority
JP
Japan
Prior art keywords
signal
binary
circuit
threshold
binary image
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62257154A
Other languages
Japanese (ja)
Inventor
Toshimitsu Hamada
浜田 利満
Mitsuzo Nakahata
仲畑 光蔵
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62257154A priority Critical patent/JPH01100676A/en
Publication of JPH01100676A publication Critical patent/JPH01100676A/en
Pending legal-status Critical Current

Links

Landscapes

  • Closed-Circuit Television Systems (AREA)
  • Image Processing (AREA)

Abstract

PURPOSE:To separate a background noise by successively updating a threshold level and taking the AND of a binary signal obtained by the new threshold level and the enlarging signal of the binary signal obtained by one time earlier. CONSTITUTION:An object 1 is image picked up by an image pickup device 2 to detect a binary picture based on an initial threshold TH0 preset to a threshold setting circuit 6 by a binarization circuit 5 through a multivalued memory 4. Then, the binary signal 9 through an AND circuit 8 writes a signal 14 enlarging the pattern of the signal 9 to a circumference to a binary memory 7 through the shift registers 11, 12 of an enlarging circuit 10. The AND of the output of the circuit 5 changing the threshold by DELTATH and the output of the memory 7 is taken in the AND 8 to repeat this operation and obtain the signal 9. Thereby, the good binary signal in which the background and the pattern are separated is obtained to the object which cannot obtain the good binary signal by a fixed threshold because of the ruggedness of a surface.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は表面が凹凸するパターンを検査す名装置におけ
る映像2値化方式に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image binarization method in a famous device for inspecting patterns having uneven surfaces.

〔従来の技術〕[Conventional technology]

映像信号を2値化すると雑音が発生することがある。従
来は特開昭55−111131号公報に記載のように繰
返し映像をサンプリングし、S/Nを改善する方式や、
第14回S、ICE学術講演会「円形部品の高速自動外
観検査法の開発」に記載のように、得られた2値画像に
雑音処理を施す方式がある。
When a video signal is binarized, noise may occur. Conventionally, as described in Japanese Patent Application Laid-Open No. 55-111131, there has been a method of repeatedly sampling video to improve the S/N,
As described in the 14th S, ICE Academic Lecture "Development of High-speed Automatic Visual Inspection Method for Circular Parts", there is a method of performing noise processing on the obtained binary image.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記従来技術は対象物表面の凹凸により信号レベルの変
化が著しい映像信号に対し配慮されておらず、良好な2
値化が困難であった。すなわち、前者の方式では、信号
自体が変化しており、雑音ではないため、繰返し映像を
サンプリングしても良好な2値画像は得られない。また
、後者の方式では欠陥と信号レベルの変化を区別するこ
とが困難である。
The above-mentioned conventional technology does not take into account video signals whose signal level changes significantly due to unevenness on the surface of the object, and does not provide good 2
It was difficult to quantify. That is, in the former method, since the signal itself is changing and is not noise, a good binary image cannot be obtained even if the video is repeatedly sampled. Furthermore, in the latter method, it is difficult to distinguish between defects and changes in signal level.

本発明の目的は上記した従来技術の欠点をなくした映像
2値化方式を提供するにある。
An object of the present invention is to provide a video binarization method that eliminates the drawbacks of the prior art described above.

〔問題点を解決するための手段〕[Means for solving problems]

上記目的は閾値を逐次上げるまたは下げることのできる
2値化回路と、2値画像を拡大または縮小する手段と、
上記2値化回路の出力を拡大または縮小した2値画像を
用い、ゲートする手段を設け、まず予め設定した閾値に
より2値画像を検出し、その2値画像を拡大または縮小
した後、2値化回路の閾値を変化させ、2値化回路の出
力を拡大または縮小した2値画像によりゲートすること
により新たな2値画像を検出する処理を繰返すことによ
り達成される。
The above object is to provide a binarization circuit that can sequentially raise or lower a threshold value, a means for enlarging or reducing a binary image,
Using a binary image obtained by enlarging or reducing the output of the above-mentioned binarization circuit, gating means is provided, which first detects a binary image using a preset threshold value, enlarges or reduces the binary image, and then This is achieved by repeating the process of detecting a new binary image by changing the threshold value of the binarizing circuit and gating the output of the binarizing circuit using the enlarged or reduced binary image.

〔作 用〕[For production]

2値化回路の閾値を逐次変化させていくと、信号レベル
の変化の影響を受けず、対象を2値画像として検出する
ことができるが、一方では背景が2値画像の中に生じ、
雑音となる。そこで本発明では予め設定した閾値により
得られる2値画像を基準に、閾値を変化させて得られる
2値画像の有効部分を、基準となる2値画像を拡大また
は縮小して求まる部分にのみ限定するようにし、新たな
基準2値画像を検出することを繰返し行い、背景が雑音
として生じるのを防止している。
By successively changing the threshold of the binarization circuit, it is possible to detect the object as a binary image without being affected by changes in the signal level, but on the other hand, the background appears in the binary image,
It becomes noise. Therefore, in the present invention, the effective part of the binary image obtained by changing the threshold value is limited to the part determined by enlarging or reducing the reference binary image based on the binary image obtained by the preset threshold value. By repeatedly detecting a new reference binary image in such a way as to prevent the background from appearing as noise.

〔発明の実施例〕[Embodiments of the invention]

本発明の一実施例を第1図に示す。第1図において対象
物1を撮像装置2により撮像し、2より得られる1の画
像信号はA/D変換器3によりA/D変換された後、1
画面分の容量を有する多値メモリ4に入力される。5は
2値化回路であり、多値メモリ4を読み出し、閾値設定
回路6により指定された閾値と比較する。閾値設定回路
6には初期値Thoと閾値変更値ΔTHが与えられてお
り、2値化回路5への出力Thj、を、多値メモリ4全
体を2値化するごとに、ThL=Tho−ΔTHX(L
−1)(ここでi=1.2.・・・N)の演算を行い更
新していく、、7は1画面分の容量を有する2値メモリ
であり、初期状態(多値メモリ4への画像入力時)にお
いて、メモリ全体がプリセット(′1′を書込む)され
ており、2値化回路5が動作するのと同期して、その内
容が読み出される。5の出力と7の出力はANDゲート
8により論理積がと・3 ・ られ、2値化号9が出力される。そして2値化号9は拡
大回路10へ入力され、拡大した後、2値メモリ7へ書
き込まれる。このようにして多値メモリ4全体すなわち
1画面分についての処理が終了すると、閾値設定回路6
において、閾値の更新が行われ、同様の処理を設定回数
N回繰返し行い、N回目の2値化号9を求めるべき2値
化号とする。
An embodiment of the present invention is shown in FIG. In FIG. 1, an object 1 is imaged by an imaging device 2, and the image signal 1 obtained from 2 is A/D converted by an A/D converter 3, and then
The data is input to a multilevel memory 4 having a capacity for a screen. Reference numeral 5 denotes a binarization circuit, which reads out the multi-level memory 4 and compares it with a threshold specified by the threshold setting circuit 6. The threshold value setting circuit 6 is given an initial value Tho and a threshold value change value ΔTH, and each time the output Thj to the binarization circuit 5 is binarized as a whole of the multilevel memory 4, ThL=Tho−ΔTHX (L
-1) (here i = 1.2...N) is calculated and updated. , 7 is a binary memory with a capacity for one screen, and the (at the time of image input), the entire memory is preset ('1' is written), and its contents are read out in synchronization with the operation of the binarization circuit 5. The outputs of 5 and 7 are ANDed by an AND gate 8, and a binary code 9 is output. Then, the binary code 9 is input to the enlarging circuit 10 and written into the binary memory 7 after being enlarged. When the processing for the entire multi-level memory 4, that is, for one screen is completed in this way, the threshold value setting circuit 6
In , the threshold value is updated, and the same process is repeated a set number of times N times, and the Nth binarization code 9 is used as the binarization code to be obtained.

次に拡大回路10の具体的構成例について説明する。第
1図において、2値化号9は長さが撮像装置2の走査線
の長さに相当するシフトレジスタ群11を介し、n X
 71のシリアルインパラレルアウトのシフトレジスタ
12へ入力される。12の多値はORゲート13へ入力
されることにより、13の出力には2値化号9における
パターン(′1′である部分)を周囲へn/2画素拡大
した拡大信号14を得ることができる。
Next, a specific example of the configuration of the enlargement circuit 10 will be explained. In FIG. 1, the binarization code 9 is passed through a shift register group 11 whose length corresponds to the length of the scanning line of the imaging device 2, and
71 serial-in-parallel-out shift register 12. By inputting the 12 multi-values to the OR gate 13, the enlarged signal 14 obtained by enlarging the pattern ('1' part) in the binary code 9 by n/2 pixels is obtained at the output of the 13. Can be done.

以上が本発明の一実施例であるが、第1図において、2
値化号9がどのように変化するかを、第2図、第3図を
用いて説明する。
The above is an embodiment of the present invention. In FIG.
How the value code 9 changes will be explained using FIGS. 2 and 3.

第2図において照明光15を(a)のように対象°4 
 。
In Fig. 2, the illumination light 15 is aimed at 4° as shown in (a).
.

物1に照射すると、表面の凹凸により乱反射が生じ、映
像信号は(b)のように、レベル変化の大きくなり、一
定の閾値で2値化したのでは良好な2値画像を得ること
ができない。このような対象物の画像を第1図において
、N=3として2値化する場合の例を第3図に示す。第
3図(a)に示すように1回目の2値化では閾値Th□
= Thoにより、検出すべきパターン(パターンは背
景に対し、反射率が高く、明るく検出されると仮定)の
一部が、(b)のように2値化号9に出力される。そし
て(b)の2値化号は拡大回路10により拡大され。
When the object 1 is irradiated, diffuse reflection occurs due to the unevenness of the surface, and the video signal has a large level change as shown in (b), and it is not possible to obtain a good binary image by binarizing with a fixed threshold value. . FIG. 3 shows an example in which the image of such an object in FIG. 1 is binarized with N=3. As shown in Fig. 3(a), in the first binarization, the threshold Th□
= Tho, a part of the pattern to be detected (assuming that the pattern has a high reflectance and is detected brightly compared to the background) is output to the binarization code 9 as shown in (b). Then, the binarized code in (b) is expanded by the expansion circuit 10.

(c)に示す2値化号が2値メモリ7に書き込まれる。The binary code shown in (c) is written into the binary memory 7.

次いで閾値設定回路6において、Th2= Th□−Δ
Thが閾値として設定されることにより、2回目の2値
化が行われ、(e)に示すような2値化号が2値化回路
5より出力され、2値メモリ7の内容、すなわち(c)
の2値化号とANDがとられ、(f)のように2値化号
9は出力される。そして(f)の2値化号は拡大回路1
0により拡大され、(g)に示す2値化号が2値メモリ
7に書き込まれる。次いで閾値設定回路6において、T
h3= Th2−ΔTHが閾値として設定されることに
より、3回目の2値化が行われ、(i)に示すような2
値信号が2値化回路5より出力され2値メモリ7の内容
、すなわち(g)の2値信号とANDすることにより、
求めるべき2値信号9が得られる。以上のように背景が
2値信号として現われない(′1′にならない)ような
閾値Th工では、良好なパターンの2値画像は得られな
く、パターン全体が2値信号として現われる(′1′に
なる)ような閾値Th3では背景が2値信号として現わ
れる(11′になる)ような場合、本発明では閾値を逐
次更新しながら、かつ新たな閾値で得られる2値信号を
1回前で得られた2値信号の拡大信号によりANDする
ことにより、パターンと背景を分離した良好な2値信号
を得るようにしている。
Next, in the threshold value setting circuit 6, Th2=Th□−Δ
By setting Th as a threshold value, the second binarization is performed, and the binarization signal as shown in (e) is output from the binarization circuit 5, and the content of the binary memory 7, that is, ( c)
is ANDed with the binary code 9, and the binary code 9 is output as shown in (f). And the binarization code of (f) is the expansion circuit 1
It is enlarged by 0 and the binary code shown in (g) is written into the binary memory 7. Next, in the threshold value setting circuit 6, T
The third binarization is performed by setting h3 = Th2 - ΔTH as the threshold, and the binarization as shown in (i) is performed.
By outputting the value signal from the binarization circuit 5 and ANDing it with the contents of the binary memory 7, that is, the binary signal of (g),
The desired binary signal 9 is obtained. As described above, with the threshold value Th technique in which the background does not appear as a binary signal (does not become '1'), a good binary image of the pattern cannot be obtained, and the entire pattern appears as a binary signal ('1'). In the case where the background appears as a binary signal (becomes 11') at threshold Th3 such as By performing an AND operation with the enlarged signal of the obtained binary signal, a good binary signal in which the pattern and the background are separated is obtained.

また、以上の説明では拡大回路を用い、パターンを周囲
へ広げ、閾値を下げていく例について説明したが、10
の拡大回路を縮小回路にし、8のゲート回路をANDか
らORに変更し、閾値を上げていくことによっても、同
様の結果が得られることは明らかである。
In addition, in the above explanation, an example was explained in which the enlargement circuit is used to spread the pattern to the surroundings and lower the threshold value.
It is clear that similar results can be obtained by changing the enlargement circuit of 8 to a reduction circuit, changing the gate circuit 8 from AND to OR, and increasing the threshold value.

〔発明の効果〕〔Effect of the invention〕

本発明によれば表面の凹凸により映像信号の変化が大き
く、固定閾値では良好な2値画像を得られないような対
象に対しても、背景とパターンを分離した良好な2値画
像を得ることができる。
According to the present invention, it is possible to obtain a good binary image by separating the background and pattern even for an object where the image signal changes greatly due to surface irregularities and a good binary image cannot be obtained with a fixed threshold value. Can be done.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の構成図、第2図は対象の例
の説明図、第3図は本発明による2値化処理過程の説明
図である。 1・・・対象物、2・・・撮像装置、3・・・A/D変
換器。 4・・・多値メモリ、5・・・2値化回路、6・・・閾
値設定回路、7・・・2値メモリ、8・・・AND回路
、9・・・2値信号、10・・・拡大回路。
FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an explanatory diagram of a target example, and FIG. 3 is an explanatory diagram of a binarization process according to the present invention. 1... Target object, 2... Imaging device, 3... A/D converter. 4... Multi-value memory, 5... Binarization circuit, 6... Threshold value setting circuit, 7... Binary memory, 8... AND circuit, 9... Binary signal, 10... ...Expansion circuit.

Claims (1)

【特許請求の範囲】[Claims] 1、撮像装置からの映像信号を2値化する手段と、2値
化の閾値を変更する手段と、2値画像信号より、パター
ンの隣接部分を抽出する手段を設け、予め設定した閾値
により求まる2値画像信号をパターンの隣接部分に対し
、拡大もしくは縮小した2値画像を創成し、閾値を変更
して得られる2値画像と合成する手段を設け、合成した
2値画像信号を新たな2値画像とし、パターンの隣接部
分に対し、拡大もしくは縮小した2値画像を創成し、閾
値を変更して得られる2値画像と合成する処理を所定回
数行うことにより、映像を2値化することを特徴とする
映像2値化方式。
1. A means for binarizing the video signal from the imaging device, a means for changing the binarization threshold, and a means for extracting adjacent parts of the pattern from the binary image signal, and the method is determined using a preset threshold. A means is provided to create a binary image by enlarging or reducing the binary image signal with respect to the adjacent portion of the pattern, and to synthesize it with the binary image obtained by changing the threshold, and to convert the synthesized binary image signal into a new binary image. Binarize the video by creating a binary image by enlarging or reducing the adjacent parts of the pattern, and performing the process of combining it with the binary image obtained by changing the threshold value a predetermined number of times. A video binarization method featuring:
JP62257154A 1987-10-14 1987-10-14 Video binarization method Pending JPH01100676A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62257154A JPH01100676A (en) 1987-10-14 1987-10-14 Video binarization method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62257154A JPH01100676A (en) 1987-10-14 1987-10-14 Video binarization method

Publications (1)

Publication Number Publication Date
JPH01100676A true JPH01100676A (en) 1989-04-18

Family

ID=17302462

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62257154A Pending JPH01100676A (en) 1987-10-14 1987-10-14 Video binarization method

Country Status (1)

Country Link
JP (1) JPH01100676A (en)

Similar Documents

Publication Publication Date Title
US4949390A (en) Interconnect verification using serial neighborhood processors
JPH04264681A (en) Setting method for binarized threshold
JPH041866A (en) Method and device for image processing
JP2710527B2 (en) Inspection equipment for periodic patterns
JPH01100676A (en) Video binarization method
JPH04147045A (en) Surface inspection device
JP2988059B2 (en) Circular container inner surface inspection device
JP2018128261A (en) Inspection apparatus and method
JPH063541B2 (en) Pattern inspection equipment
JPS61205811A (en) Defect detection method
JPS5816837B2 (en) pattern detection device
JPS62212506A (en) Method for detecting flaw
JP2770637B2 (en) Pattern inspection equipment
JP4538135B2 (en) Defect inspection equipment
JP4299908B2 (en) Object boundary determination method and apparatus
JP2827756B2 (en) Defect inspection equipment
JP3144067B2 (en) Inspection equipment for printed wiring boards
JPH0332723B2 (en)
JPH0785263B2 (en) Pattern scratch detector
EP0356463A1 (en) Interconnect verification using serial neighborhood processors
JP2634064B2 (en) Binarization device
JP3109237B2 (en) Line segment constituent pixel extraction method and line segment judgment method in image
JPH0480427B2 (en)
JPH07318511A (en) Periodic pattern inspection apparatus
JPH0812697B2 (en) Pattern defect inspection system