JPH01100794A - Memory access system - Google Patents

Abstract

PURPOSE:To use the high speed access mode of a DRAM by holding the DRAM in the condition except writing when the access request of the DRAM is not continuously executed after a dynamic memory element (DRAM) is accessed at least once. CONSTITUTION:When the access request of DRAM is not executed continuously after the DRAM is accessed at least once, the strobo signal of the row address of the DRAM is made into the active condition and the DRAM is held at the condition except the writing. Namely, in a PEND condition 204, the inverse of RAS signal 103 is in the active condition and during the time, the condition except the writing is obtained to the DRAM. Thus, even when between the DRAM and the access of the DRAM, other memory such as ROM except the DRAM and an I/O (peripheral input output device) are accessed, the processing speed of the system as a whole can be improved since the high speed access mode of the DRAM is not interrupted.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a memory access method, and particularly to a memory access method suitable for high-speed access control of a dynamic RAM having high-speed access modes such as static column mode and page mode. Regarding the method.

[Conventional technology]

In recent years, as semiconductor memories have become faster, devices with access times of less than 100 nanoseconds have become commercially available, even in MOS dynamic RAM (CDRAM). Some of these DRAMs are equipped with a special mode that allows faster read/write operations during consecutive memory accesses. For example, Hitachi's 1 megabit DRAM, HM5110
Static column mode in 02S, same HM51100
In 0S, it is a speed-up means such as page mode. The operation timings of these DRAMs are listed in Hitachi's data book "Hitachi IC Memory" March 1985 edition (C8746W)
p, 374-p, 383 (HM511002S) and p, 347-p, 355 (HM511000
S).

Next, the above-mentioned high-speed access mode will be explained using FIG. 2. In FIG. 2, 1 represents a DRAM memory cell. In the figure, cells are arranged in n rows and m columns. Generally, when accessing a DRAM, the address of the cell to be accessed is specified twice, once for the row and once for the column.

For example, when accessing cell (i, j) 102, first specify the row address i to select m cells on the i-th row 101 of the memory cell, and then specify the column address j. This allows access. What should be noted here is that when a row address is specified, all 10 memory cells are activated. Therefore, for example, when continuously accessing memory cells in row 1101, there is no need to respecify the row address each time.
It should be possible to simply specify the column address and access it. The above-mentioned static column mode and page mode DRAM utilize this principle.

These access timings will be explained with reference to FIG. R.A.
S I O 3 is a strobe signal for row address 106 . C5104 is a chip select signal, and the solid line portion corresponds to a static column mode DRAM. CA S 104, 105 in parentheses is column address 10
7, and the dotted line portion 105 corresponds to the page mode DRAM. Accessing a certain address (i, j) initially takes time for the TF 109, but accessing another column address within the same row address i, Q...
・To access 2107 etc., Ts is shorter by TR108.
The figure shows that the access time is only 110 minutes.

Time TEso TERA S 103 Oyohi CS 104
is inactive.

(2) The next access was made to a row address other than i.

(2) Other memory elements (including RAM and ROM) were accessed.

Indicates that one of the following states has occurred: (1) an access was made to I10, and (2) an idle cycle (no access was made). In this case, the next time an access request occurs, the first time will be TF10.
Therefore, it takes 9 hours to perform the access operation.

FIG. 4 is a state transition diagram showing the memory control of the prior art described above. 201 is a standby state (hereinafter referred to as 5TBY state) in which there is no access request to the memory, and the standby state 201 remains via path 205 unless there is an access request. 202 indicates the first memory access state (hereinafter referred to as the IST state). IS
In the T state 202, memory access is performed at the timing of the period of TFIO9 in FIG. 203 indicates the memory access state in the same row after the second time (hereinafter referred to as 2ND state). The 2ND state 203 is TsllO in FIG.
Memory access is performed at a timing corresponding to the period.

When a memory access request is made in the 5TBY state 202, a transition is made to the IST state 202 via a path 206. I
When the access in ST state 202 is completed, if there is no next memory access request, 5 is sent via path 207.
Return to TBY state.

If the next access request occurs in the IST state 202, 2
The following state transitions occur. The first case is when there is an access request to the same row address among the previous memory addresses as shown in FIG. The second case is when there is an access request to a different row address from the forward one, in which case the state transits to the IST state 202 again via path 208.

In the 2ND state 203, if there is no next memory access request after the access is completed, the 5
Transition to TBY state 201. When the next access request occurs in the 2ND state 203, two state transitions occur. This is similar to the IST state 202; the first case is when there is an access request to an address in the same row, and in this case, the state transits to the 2ND state 203 again via the path 211. The second case is when an access request is made to another row address, in which case a transition is made to the IST state 202 via path 210.

In addition, as a problem specific to DRAM, the RAS signal 103 and C3 (CAS) signal 104 in FIG.
For this reason, for example, the 2ND
If the state remains in state 203, timeout (T, O,
), it is normal to control the transition to the IST state via path 210 even if the memory is accessed within the same row.

[Problem that the invention seeks to solve]

An example of the operation of a microcomputer system using the conventional access control method shown in FIG. 4 is shown in FIG. 5(A). In an actual system, not only RAM (DRAM here) but also ROM (read-only memory) and I10 (peripheral input/output device) are accessed in this way. Since the probability of successive accesses to addresses within the same row address of RAM is high, 1 For example, access 3 for RAM accesses such as accesses 302 to 305.
RAM access cycles after 03 can be shortened. However, as in the example of accesses 306-311, for example, R
Even if the access to AM is to an address in the same row, the RO is inserted between RAM accesses.
If accesses to M and Ilo are mixed, the fourth
In the control method shown in the figure, the 5TBY state 201 and the IST state 202
Therefore, the high-speed access mode of DRAM cannot be utilized. In other words, although the above technology considers continuous access to DRAM, it does not consider speeding up DRAM access when accesses to other memories or Ilo are mixed between accesses between DRAMs, which often occurs in actual systems. First, there was a problem in that the high-speed access mode of DRAM could not be fully utilized.

An object of the present invention is to provide a memory access method that can take advantage of the high-speed access mode of DRAM even when accesses to memories other than DRAM and memory devices 10 are mixed.

[Means for solving problems]

In order to achieve the above object, the present invention provides an access method for a DRAM device having a high-speed access mode, in which, after accessing the DRAM at least once, if there is no continuous access request for the DRAM, the DR
The strobe signal of the AM row address is made active, and the DRAM is held in a state other than writing.

The high speed access mode is one, for example, static column mode or page mode. Specifically, the fourth
In the control system shown in the figure, when an access request to the DRAM is interrupted, the path 207 or 212 is used to
A state in which the high-speed access mode state is suspended until the next DRAM access without transitioning to the TBY state 201 (Fig.
04). This means that the RAS in Figure 3
This corresponds to controlling to wait for the next DRAM access while keeping the signal 103 at "L" level, that is, active.

[Effect]

In a DRAM having a high-speed access mode, after entering the high-speed access mode, basically after a column address is determined, reading and writing becomes possible only in an access time defined by the physical characteristics of the element. Stop accessing DRAM once. That is, when the RAS signal is made inactive, a precharge time is required before the RAS signal is made active next time. This becomes the first loss time. When the next access starts, the row address is first made valid, but after that, a row address holding time is required before the column address is made valid. This is the second
This will result in lost time. After these two procedures, the DRAM
is once again in a state where it can be accessed at high speed. Therefore, when the same row address is accessed continuously, the RAS signal is kept active as much as possible.

It is better to maintain a state where high-speed access is possible. Therefore, if the RAS signal is kept active even when access to DRAM is interrupted, the next time there is a request to access DRAM, if the access is within the same row address, the read/write operation can be performed without loss time. become able to.

〔Example〕

FIG. 1 is a state transition diagram of an embodiment of the control method of the present invention. The 5TBY state 201, the IST state 202, and the 2ND state 203 are the same as those shown in FIG.
It is characterized by the provision of 4). The control method shown in FIG. 1 will be explained below with reference to FIG. 5.

The 5TBY state 201 in FIG. 1 is a state when the DRAM is not operating, and unless an access request occurs, the path 2
05, it remains in the 5TBY state 201. This corresponds to section 201 in FIG. 5(C). The symbols assigned to each section in FIG. 5(C) match the symbols for the four states in FIG.

Furthermore, each section in FIG. 5(C) corresponds to each access in CB) in the same figure.

When an access request occurs in the 5TBY state 201,
A transition is made to the IST state 202 via path 206 . The timing at this time is shown in section 202 in FIG. 5(C), which corresponds to access 302 in FIG. 5(B). If there are no consecutive access requests at the time this access ends, a transition is made to the PEND state 204 via path 214 in FIG. The PEND state 204 means that the RAS signal 103 is
"level.

In other words, this is control to maintain the active state. When access requests occur consecutively in the IST state 202, two types of transition occur. The first case is when there is an access request to a different row address, in which case the state is transited to the IST state 202 again via the path 208 and access is performed. The second case is when there is an access request to an address within the same row address, in which case a transition is made to a 2ND state 203 via a path 209. In the case of Von Neumann type computers, program and data locality, that is, the probability of accessing an address near the currently accessed address is very high, so in many cases, the 2ND state 2
Transition to 03. This is access 303 in Figure 5(B).
This corresponds to section 203 in FIG. 2ND
After finishing the access in the high speed access mode in the state 203, if there is no continuous access, the state transits to the PEND state 204 via the path 213. This corresponds to accesses 306, 308, and 310 in FIG. 5(B).
This corresponds to section 204 in C). When access requests occur consecutively in the 2ND state 203, three transitions occur. The first case is when an access request to an address within another row address occurs, in which case a transition is made to the IST state 202 via path 210. The second case is when there is an access request to an address in the same row, and in this case, route 2
11, the state transits to the 2ND state 203 again. This corresponds to section 203 in Figure 5 (C>) which corresponds to accesses 304 and 305 in Figure 5 (B). Of the three transitions, this transition has the highest probability. The third In a special case, even though there is an access request to an address in the same row, due to a problem specific to DRAM elements, the maximum period for which the RAS signal 103 can be kept active at that time has been reached (hereinafter, a timeout occurs). ).

At this time, since it is necessary to return the RAS signal 103 to inactive once again, a transition is made to the IST state via path 210 as in the first case.

The PEND state 204 is the state that most characterizes the present invention. That is, as shown in section 204 in FIG. 5(C), R
While the AS signal 103 remains active, the DRA
M is kept in a state other than writing. Of course DR
If read data is held in a state where it is output from AM, the data output will not drive the system data bus.

A 3-state data buffer (or 3-state data latch) is inserted between the data output terminal of the DRAM and the system data bus, and its output is kept in a high impedance state during the PEND state 204. The PEND state 204 remains in the PEND state 204 via path 216 until an access request to the DRAM occurs in the PEND state 204 .

There is an exception to this case; if the aforementioned timeout occurs, a transition is made to the 5TBY state 201 via path 217. This situation is shown in sections 204' and 204' in Figure 5 (C).
1'.

When an access request occurs in the PEND state 204, if it is an access request to an address in another row, a transition is made to the IST state 202 via a path 215.

Further, if the access request is to an address within the same row, a transition is made to a 2ND state 203 via a path 218.

As described above, since the probability of occurrence in this case is large, compared to the conventional control method shown in FIG. 5(A), the processing speed in FIG. 5(B) using the control method of the present invention can be increased by time 315.

Next, consider a case where the present invention is implemented in main memory control of a personal computer or the like (hereinafter simply referred to as a personal computer). In a personal computer, when the system is started up, the main memory DRA
It is common to check M. The check program at this time is stored in the ROM, and the program continuously writes a certain value to the DRAM, and then continuously reads the DRAM and compares the written value and the read value. is taken. In recent years, DR
AM is also increasing in capacity, and the capacity installed in personal computers is also increasing.

As a result, main memory DR is performed every time the system is started up.
I started spending tens of seconds to several minutes checking AM. While this check program is running, a processor (hereinafter referred to as CPU) alternately fetches instructions from the ROM and reads and writes to consecutive addresses in the DRAM.

That is, accesses such as accesses 309 to 311 in FIG. 5(A) occur frequently. In DRAMs with a high-speed access mode currently available on the market, the ratio of the normal access time to the access time in the high-speed mode is approximately 3=1. However, in the conventional control system, this high-speed access mode is interrupted by ROM reading, increasing the processing time of the check program. According to the control method of the present invention, R
Even if an OM instruction is read, the DRAM high-speed access mode is not interrupted, so the main memory DRAM is
This has the effect of reducing the check time to approximately 1/2. Also, from a price point of view, the DRA used in computers
Since the number of M is large, the price of the DRAM control circuit is about 115 to 1150 yen compared to the price of DRAM. The addition of the main functions of the present invention only increases the logical scale by about 10 to 20% compared to conventional control circuits. Therefore, it is much more economically advantageous than replacing the DRAM itself with an expensive high-speed version DRAM.

Although the present invention has been described in detail above, the essence of the control method according to the present invention is that the PEND state 204 is provided, and the state transitions shown in the embodiment of FIG. For example, there may be other state transitions including the refresh state of the DRAM. Also, PEND status 2
04 means that the KAS signal 103 is active and the DRA
As long as M is in a state other than writing, it does not matter what form of control it takes; these differences do not deviate from the essence of the present invention.

〔Effect of the invention〕

According to the present invention, even if other memory such as ROM other than DRAM or Ilo is accessed between DRAMs and DRAMs, the high-speed access mode of DRAM is not interrupted, thereby improving the processing speed of the entire system. Can be done.

[Brief explanation of the drawing]

Fig. 1 is a state transition diagram of an embodiment of the control method of the present invention, Fig. 2 is a diagram explaining the principle of DRAM high-speed access mode, Fig. 3 is a timing diagram of high-speed access mode, and Fig. 4 is conventional control. The state transition diagram of the system, FIG. 5, is an explanatory diagram comparing the conventional system and the system of the present invention. 201...5TBY state, 202...IsT state. 203...2ND state, 204...PEND state. 1st l/I 2nd figure ol 1st + concave FOIA/'=T? OW

Claims (1)

[Claims] 1. In an access method for a dynamic memory element (hereinafter referred to as DRAM) having a high-speed access mode, when there is no continuous access request to the DRAM after accessing the DRAM at least once, , said D.R.
A memory access method characterized in that a strobe signal of an AM row address is activated and the DRAM is held in a state other than writing. 2. The memory access method according to claim 1, wherein the high-speed access mode is a static column mode. 3. The memory access method according to claim 1, wherein the high-speed access mode is a page mode.