JPH01100943A - Semiconductor integrated circuit device of masterslice layout - Google Patents

Abstract

PURPOSE:To enable chips to be measured automatically form selecting nondefectives and to simplify lot administration, by incorporating an electronic circuit and bonding pads into a chip so that the chip itself can electrically check its own data, for example a name of product, design change history and the like. CONSTITUTION:All types of first function circuit sections 2 having a common substrate are completely identical, including functions of bonding pads 6-9 and lay-out within an IC chip 1, except data stored in an ROM 5. The ROM 5 stores data related to a second function circuit section 3, for example, a name of the IC chip 1 (production number), a revision number, a function name etc., in binary codes serially in the order. of their addresses. If content of the second function circuit section 3 or the number, of type is changed, the data stored in the ROM 5 is also changed simultaneously in the metallizing process. Accordingly, data related to the second function circuit section 3 can be obtained from a counter increment terminal pad 7 in the first function circuit section 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a master slice type semiconductor integrated circuit device, and more particularly to a master slice type semiconductor integrated circuit device in which metal wiring patterns are changed for each product type.

[Conventional technology]

Conventionally, master slice type semiconductor integrated circuit devices have the advantage of shortening the development period and being able to be manufactured at low cost compared to dedicated products, and have been considered suitable for high-mix, low-volume production.

[Problem that the invention seeks to solve]

However, in the conventional master slicing semiconductor integrated circuit device, firstly, even if the number and layout of the bonding pads in the chip are the same, multiple products are arranged irregularly on one wafer. Since the test pattern of the IC tester needs to be changed for different types, there is a problem that it becomes impossible to automatically measure the chips in the wafer using the IC tester to select non-defective products, and even if it were possible, the process of classifying the types after the guising process However, the disadvantage is that productivity is poor. Second, when a specific IC package is used in common for multiple types, it is impossible to distinguish the types of chips with the naked eye, which makes loft management difficult and reduces productivity, especially in the process of stamping product names. It has the disadvantage of being inferior.

SUMMARY OF THE INVENTION An object of the present invention is to provide a master slicing semiconductor integrated circuit device that can select non-defective chips by automatic chip measurement and simplify loft management.

[Means for solving problems]

The master slice type semiconductor integrated circuit device of the present invention incorporates a first functional circuit section and a second functional circuit section into the same semiconductor monolithic chip, and a second functional circuit section is installed in the first functional circuit section. It is constructed by providing means for electrically extracting the information to be referred to outside.

That is, the present invention incorporates an electronic circuit and a bonding pad into the chip itself so that information about the chip itself, such as product name, design change history, etc., can be electrically checked.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) and 1(b) are plan views of an IC chip for explaining a first embodiment of the present invention, respectively.

As shown in FIG. 1(a), the Tc chip 1 includes a first functional circuit section 2, a second functional circuit section 3 corresponding to a conventional master slice type semiconductor integrated circuit device,
It is composed of pads for connecting to the first functional circuit section 2 and the second functional circuit section 3. The first functional circuit section 2 includes a counter circuit 4 and a read-only memory (hereinafter referred to as R
This counter circuit 4 has a counter increment terminal and a 5-digit output terminal, and the ROM 5 has an output terminal and 5 address terminals. The output is connected to five address terminals of ROM5. The pads 6 to 9 formed outside the first functional circuit section 2 serve as power supplies, counter increment terminals, and counter increment terminals for the counter circuit 4 and ROM 5 included in the first functional circuit section 2, respectively.
It is a bonding pad for drawing out the output and GND potential to the outside, and the bonding pad 10 formed outside the second functional circuit section 3 is used for each purpose of the second functional circuit section 3. It is a padding pad to bring out the function to the outside.

The above-mentioned first functional circuit section 2 is completely the same, including the functions of the bonding pads 6 to 9 and the layout within the IC chip 1, in all types that share the same substrate, except for the storage information in the ROM 5. be. In addition, the output of the counter circuit 4 is such that the potential of the power supply terminal changes from the GND potential to the power supply potential 5.
The circuit is designed so that when the voltage changes to V, it becomes clear, that is, becomes 0.

Furthermore, the storage information of the ROM 5 is, for example, 1. , , Information referring to at least the second functional circuit section 3, such as the type name (product number) of the C chip 1, revision number 2, and function name, is serially stored in binary code in address order. When the contents of the second functional circuit section 3 change or the product name changes, the information stored in the ROM 5 is also changed at the same time in the metallization process.

Next, as shown in FIG. 1(b), the second functional circuit section 2
The information in the ROM 5 is read out as follows.

First, ground the power supply pad 6, GND potential pad 9, and counter increment terminal pad 7, and then apply power supply voltage 5■ to the power supply pad 6, the contents of the counter 4 will become 0, and the contents of address 0 of the ROM 5 will be output. pad 8
is output to.

Next, after setting the counter increment terminal pad 7 from the GND potential to the power supply voltage of 5V, and then returning it to the GND potential, the content of the counter 4 increases by one to l, and the ROM
The contents of address 1 of 5 are output to output pad 8. Similarly, if you repeat raising and lowering the potential of the counter increment terminal pad 7, the contents of the counter will increase by - increments up to 31.
5 can be read from the output pad 8.

Therefore, from the counter increment terminal pad 7 in the first functional circuit section 2 to at least the second functional circuit section 3.
It is possible to obtain information referring to the second functional circuit section (product type information).

FIGS. 2(a) and 2(b) are a plan view of an IC chip and a signal waveform diagram, respectively, for explaining a second embodiment of the present invention.

As shown in FIG. 2(a), this IC chip 1 has a power supply pad 6 in the first functional circuit section 2 shown in FIG. 1(a).
and GND pad 9 are removed, and the first functional circuit section 3 is
This embodiment differs from the first embodiment in that it is connected via a lead wire 13 to a bonding GND pad 12 for drawing out the power supply/GND potential of the counter 4 and ROM 5 to the outside. The other numbers are the same as those in the first embodiment, so their explanation will be omitted. By sharing the power supply pad 11 and the GND pad 12 in this way, the second embodiment has the advantage that the number of bonding pads on the entire IC chip 1 can be reduced without degrading the functionality of the first embodiment. .

Further, as shown in FIG. 2(b), the first functional circuit section 2
The information in the ROM 5 is read out in the same manner as in the first embodiment.

FIG. 3 is a plan view of an rc chip for explaining a third embodiment of the present invention.

As shown in FIG. 3, the IC chip 1 includes a first functional circuit section 2 and a second functional circuit section 3, and the first functional circuit section 2 has nine 100Ω resistors 14 connected in series. connect to
Ten taps 15 are drawn out from both ends of each resistor 14. Among these 10 taps, pads 6 to 9 are pads 6 to 9, respectively, for pulling out four taps to the outside. Further, the second functional circuit section 3 corresponds to a conventional master slice type semiconductor integrated circuit, and the pad 10 connected to it is a bonding pad for drawing out the second functional circuit section 3 to the outside. be. The nine resistors 14 in the first functional circuit section 2 described above
is controlled to have a resistance value of 95 to 105 Ω in the base process of the master slice semiconductor integrated circuit, and in the product manufacturing process, which of the 10 taps to connect the bonding pads 6 to 8 to is determined by the product name. (Product No).

Revision number 1 Information referring to at least the second functional circuit section 3 such as function name can be obtained 5 Each bonding, pad 6 -
In this embodiment, the bonding pad 9 is common to all types and is connected to the same tap.

Information actually referring to the second functional circuit section 3 can be obtained as follows.

That is, after measuring the resistance values R6, R7, and R8 between the pounding pad 9 and each of the pounding pads 6 to 8, divide each value by 100 Ω and take the integer closest to the quotient as L-M-N. For example, 3-digit integer 100L+1
0M+N is obtained. Therefore, by creating a correspondence between a 3-digit integer and the second functional circuit section 3 in advance, information referring to the second functional circuit section 3 can be obtained by the first functional circuit section 2. I understand that.

The master slice type semiconductor integrated circuits of the three embodiments described above are: - When multiple types of chips with the same chip size, number of bonding pads, layout, etc. are arranged irregularly within the wafer; However, the IC tester's program requires that the IC tester first learns the second functional circuit section, that is, the product type, from the first functional circuit section, and then changes the test pattern corresponding to the product type to select and test the IC. Therefore, it becomes possible to select non-defective products by automatically measuring chips in a wafer using an IC tester. In addition, since the product type can be determined in the same manner even after the bonding process, there is no need to classify the product type not only after the dicing process but also during the mounting, bonding, and stamping processes. Therefore, there is an advantage that productivity in processes such as wafer checking, assembly, marking 1 sorting, and inspection is improved.

〔Effect of the invention〕

As described above, the master slice type semiconductor integrated circuit of the present invention has the effect of improving productivity in each process of its manufacturing, ie, checking inside the wafer, assembly, marking 1 sorting, and inspection.

[Brief explanation of the drawing]

FIGS. 1(a) and (b) are a plan view and a signal waveform diagram of an IC chip for explaining the first embodiment of the present invention, respectively, and FIGS. 2(a) and (b) are respectively A plan view and a signal waveform diagram of an IC chip for explaining the second embodiment, and FIG.
FIG. 3 is a plan view of the C chip. 1... IC chip, 2... First functional circuit section of IC,
3... Second functional circuit section of IC, 4... Counter circuit, 5... Read only memory (ROM), 6...
・Power supply pad of the first functional circuit section, 7... Counter increment terminal pad, 8... ROM output pad,
9... GND pad of the first functional circuit section, 10... Pad of the second functional circuit section, 11... Power supply pad of the second functional circuit section, 12... GND pad of the second functional circuit section ,
13...Lead wiring, 14...Resistor, 15...Tap.

Claims (1)

[Claims] 1. A first functional circuit section and a second functional circuit section are incorporated into the same semiconductor monolithic chip, and information referring to the second functional circuit section is externally provided to the first functional circuit section. 1. A master slice type semiconductor integrated circuit device characterized by being provided with a means for electrically extracting. 2. The master slice type semiconductor integrated circuit according to claim 1, wherein the first functional circuit section is formed of a counter circuit and a read-only memory, and the output of the counter circuit is connected to the address of the read-only memory. circuit device.