JPH01101596A - electronic musical instruments - Google Patents

Abstract

PURPOSE: To reduce the size of a circuit and to easily set up the optimum number of time-divided channels corresponding to a condition such as an operation speed by using a RAM as a data register for executing time-divided waveform information processing and switching an address generation pattern to be supplied to the RAM. CONSTITUTION: Relating to the electronic musical instrument provided with a time-divided waveform information processing means, the processing means is provided with a storage means such as a RAM 21 capable of reading out/ writing data from/in an optional storage address and address signal generation means 26, 27 having plural address generation patterns to be applied to the storage means and capable of selecting the number of time-divided channels by controlling the switching of the address generation patterns. An optional address pattern is selected from plural address patterns generated from the means 26, 27 and applied to the RAM 21. Consequently the number of time- divided channels is set up, the size of the circuit is reduced and the number of time-divided channels corresponding to a condition such as an operation speed is easily selected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electronic musical instrument that can be used by switching the number of time-division channels.

[Conventional technology]

Conventionally, electronic musical instruments having time-division waveform information processing means have used shift registers as data registers.

FIG. 4 is a block diagram showing the basic configuration of a waveform information processing section of such a conventional electronic musical instrument. In the figure, the time-division waveform information processing section has a current address register 1, a pitch data register 2, and a reproduction flag register 3 in which a current address, pitch data, and reproduction flag are stored, respectively. These registers 1.2.3 have, for example, 16 time-division channels, and clock CL
This is a shift register that shifts data by K. The outputs of the pitch data register 2 and reproduction flag register 3 are returned to the input side and written again, and the AND gate 4
Enter. The output of the current address register 1 and the output of the AND gate 4 are added by an adder 5, and the added output is input to and written into the current address register 1. The output of this current address register 1 is given to a waveform memory (not shown) as a current address CA for reading.

In the time-sharing information processing section of such a conventional electronic musical instrument, when the playback flag in the playback flag register 3 is "1",
Pitch data, which is the output of the pitch data register 2, is output from the AND gate 4.

The pitch data output from the AND gate 4 is added to the output of the current address register 1 by an adder 5, and then input to the current address register 1 again and written therein. Therefore, the current address CA output from the current address register 1 advances as pitch data is accumulated.

Incidentally, there are cases where it is desired to reduce the number of time-division channels for use due to conditions such as calculation speed. For example, when using dynamic RAM, access time is longer than when using static RAM. In such a case, if there is a requirement to operate 16 time divisions in 8 time divisions due to the condition of calculation speed, it is necessary to operate as shown in FIG. 5 when constructed using conventional shift registers. That is, as registers corresponding to the conventional current address register 1, pitch data register 2, and playback flag register 3, there are two current address registers 6.6' and pitch data register 7.7' divided by 8 times, respectively.
, a playback flag register 8.8' are provided, and a selector for controlling the selection of inputs A and H is provided between the current address register 6.6', pitch data register 7.7', and playback flag register 8.8'. 9.10.11 is provided. The other configurations are the same as in FIG. 4.

With this configuration, selector A of 9.10.11
By controlling the inputs to be selected, a 16 time division circuit operation similar to that shown in FIG. 1 is performed.

Also, by controlling the B input of selector 9.10.11 to be selected, one of shift registers 6', 7', and 8' is not used, and shift registers 6.7.
8 becomes valid, and the circuit operates in 8 time divisions.

[Problem that the invention seeks to solve]

However, with the conventional circuit configuration as described above, it is necessary to divide each shift register and add a selector in order to switch and use the time division channels.
There was a problem that the circuit scale became large.

In addition, if the above circuit is configured with a gate array, etc., the shift register generally has a large circuit scale per unit storage capacity, so there may be problems such as the gate array's chip size becoming large or not being able to be stored on a chip. was occurring.

SUMMARY OF THE INVENTION An object of the present invention is to enable an electronic musical instrument to easily switch the number of time-division channels according to calculation speed with a small circuit scale.

[Means for solving problems]

The means of the present invention provides an electronic musical instrument equipped with a time-division waveform information processing means, in which the time-division waveform information processing means includes a storage means such as a RAM, which can read and write data to an arbitrary storage location, and a storage means that provides data to the storage means. The device has a plurality of address generation patterns, and includes address signal generation means for switching and controlling the address generation patterns to select the number of time-division channels.

[For production]

The operation of the means of the invention is as follows. An arbitrary one is selected from among the plurality of address patterns from the address signal generating means and applied to the RAM as a storage means of the time-division waveform information processing means. As a result, the number of time division channels is set.

Therefore, the circuit scale can be reduced and the number of time-division channels can be easily selected in accordance with conditions such as calculation speed.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a waveform information processing section of an electronic musical instrument that implements the function of a shift register using a RAM. In the same figure, RAM (RandomAccess
Me+wory) 21 is used to realize the function of a conventionally used shift register, and is a storage means that can read and write to any storage location.

The address input terminal of this RAM 21 is supplied with an address signal from an address signal generation section, which will be described later, and the input terminal of the chip select signal is grounded. A chip write enable signal (WE) and a read/write signal (R/W) given from a control section (not shown) are input to an OR gate 22, and the output of this OR gate 22 is
It is input to the input terminal of the write enable signal (WE) of the RAM 21. In addition, the above read/write signal (R/
W) is input to the input terminal of the output enable signal (dpi) of the RAM 21 and the control terminal of the tri-state buffer 24 via the inverter 23. This tri-state buffer 24 is a gate that is set to an output state when an "O" (low level) signal is applied to its control terminal, and becomes a high impedance state when a "1" (high level) signal is applied to its control terminal. Output data from the data input/output (110) terminal of the RAM 21 is applied to the output data flip-flop 25 at a predetermined timing described later, and data (DATA 0UT) is provided in synchronization with the clock CLK applied to the flip-flop 25. Output. Input data (DATA IN) is input to the input data flip-flop 26, and is sent to the tri-state buffer 2 in synchronization with the clock CLK applied to the flip-flop 26.
4 to the data input/output (Ilo) terminal of the RAM 21.

, FIG. 2 is a block diagram showing the configuration of a read address signal generating section applied to the RAM 21 of FIG. 1. In the figure, an address counter 27 is a counter that generates an address signal, and outputs A0 to A3 for each bit (4 bits in the embodiment) of this address counter 27 are outputted to AND gates 28-1 to 28-2, respectively. is input. The other of these AND gates 28-1 to 28-4 receives a control signal α for controlling the number of time-division channels. ~α3 is inputting. And gates 28-1 to 28-4
The output of is given to RAM21.

An example of the operation of the waveform information processing section of the electronic musical instrument having the above configuration will be described.

FIG. 3 is a timing chart showing the operation of the waveform information processing section of FIGS. 1 and 2. FIG. As shown in Figure 3 (, R
By giving an address signal to AM21 and a read/write signal (R/W) that is "O" in the first half of each time-division channel and "1" in the second half, writing is performed in the first half of each time-division channel, and writing is performed in the second half. Perform read operation.

First, when reading data, rnJ is applied to the address signal in the latter half of time division channel "n III. During this time, since the read/write signal (R/W) is "1", Wπ is "1". π is "0", and the signal BC applied to the control terminal of the tristate buffer 24 is "1".
” and is in a high impedance state, and the data for time division channel “n” is in the time division channel “n, -1”.
In the last part of the second half, the I10 signal is determined with a delay of the RAM 21 access time. This I10 signal is given to the output flip-flop 25, and the next clock CL
Since it is taken in at the rising edge of K, it is determined as the DATAOUT signal output from the flip-flop 25 within the section of time division channel "n".

Next, when data is written, it is performed in the first half of each time-division channel. If the time-division channel "nl" is used as the calculation interval for the time-division channel "nl," the calculation result is determined at the end of the time-division channel "nl."

The result of this operation is given to the input data flip-flop 26 as a DATA IN signal, and the next clock CL
Since it is taken in at the rising edge of K, the calculation result for the time division channel "n" is determined as the output of the input data flip-flop 26 at the time division channel "n+1". The output of the input data flip-flop 26 is input to the tri-state buffer 24, and since the BC signal is given "O" in the first half of each time-division channel and "1" in the second half, the output of the tri-state buffer 24 is is output as definite data in the first half of the time division channel like the BOUT signal, and becomes high impedance in the second half. On the other hand, the address signal is the time division channel “n
rnJ is set in the first half of ``+1'', and a chip write enable signal (CWT) that becomes ``0'' is given in the first half of each time division channel, so while it is at rOJ, WE is at rOJ and the data is Writing is performed.

In the above operation, calculations are performed using the read data,
It is assumed that this calculation result will be written again, but if calculation and rewriting are not performed, only the read operation is required, so the address signal in the first half of the time division channel is irrelevant, and the calculation interval is If the length is short, it becomes possible to provide other address signals.

Next, the operation of switching the number of time-division channels when performing the above-described control will be described.

As shown in FIG. 2, the address counter 27 outputs a read address signal and a control signal α. , α1, α2
, α3 is fixed at “0”, the number of time-division channels is halved. For example, α.

, α8, α2 are set to “1” and α3 is set to rOJ, the most significant bit A3 is fixed to “0” and the time division channel is halved. Further, by setting other control signals to "0", the number of time division channels can be further halved.

Generally, the circuit now has time division channels O11, 2, .
...When operating in N time division consisting of N-1, if you want to operate the same circuit in N/2 time division, for example, fix any 1 bit of the address signal to rOJ or "1". Just let it happen. For example, the most significant bit (
MSB) is fixed to rOJ, the circuit will operate in N/2 time division consisting of time division channels O11, 2, . . . N/2-1. Furthermore, by using an address signal generating means in which the value of N can be programmed, it becomes possible to arbitrarily set the number of time division channels.

As described above, since RAM is used as a data register and has the function of a shift register, and the address pattern given to the RAM can be switched, the circuit scale is small (and time-sharing channels can be easily switched). In addition, if you want to increase the operation speed of waveform information processing, set the number of time division channels to a small number,
When the operating speed of waveform information processing can be slow, by setting a large number of time-sharing channels, you can give one time-sharing channel the necessary and sufficient calculation time and still allow the operating speed of waveform information processing. It becomes possible to obtain a larger number of time division channels in the range.

〔Effect of the invention〕

As explained above, according to the present invention, a RAM is used as a data register for time-division waveform information processing, and the address generation pattern supplied to this RAM can be switched, so the circuit size can be reduced. In addition, it becomes easy to set the optimal number of time-division channels according to conditions such as calculation speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a waveform information processing section of an electronic musical instrument according to an embodiment of the present invention, and FIG. 2 is a block diagram of a generation section of an address signal given to the RAM of FIG. 1 according to an embodiment of the present invention. , FIG. 3 is a timing chart showing the operation of the waveform information processing section of FIG. 1 according to an embodiment of the present invention, FIG. 4 is a block diagram of the waveform information processing section of a conventional electronic musical instrument, and FIG. 5 is a conventional one. FIG. 3 is a block diagram of a waveform information processing section of another electronic musical instrument. 21...RAM. 22...OR gate, 23...Inverter, 24...Tri-state buffer, 25...Flip-flop for output data, 26...
Flip-flop for input data, 27... Address counter, 28-1.28-2.28-3.28-4... AND gate. Patent applicant Casio Computer Co., Ltd. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Scope of Claims] An electronic musical instrument equipped with a time-division waveform information processing means, wherein the time-division waveform information processing means comprises a storage means that can read and write data to an arbitrary storage location, and an address generation pattern given to the storage means. Have multiple
An electronic musical instrument comprising: address signal generating means for selecting the number of time-division channels by switching and controlling the address generation pattern.