JPH01102795A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To improve resistance for a software error by providing a memory cell capacity in a parity bit group larger than that in a normal bit group. CONSTITUTION:In the memory cell, MOS transistors T1-T4 are formed by a dispersing layer 1 and a polycrystal silicon layer 2 to constitute a word line formed on the dispersing layer. And the normal bit group and the parity bit group can be formed by using the memory cells, and the dispersing area of the memory cell capacity of the parity bit group is set larger than that of the memory cell capacity of the normal bit group. In such a way, it is possible to obtain the high resistance for the software error.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device using a flip-flop type static memory cell.

[Conventional technology]

Conventionally, such semiconductor memory! There is a semiconductor memory device in which a parity bit group is provided in addition to a normal bit group in the chip in order to detect malfunctions due to soft errors such as a-line.

The 20th is a block diagram of a semiconductor memory device constructed using conventional static memory cells and having nine regular bit groups and a harness bit group.

As shown in FIG. 2, reading and writing operations regarding the regular bit group 7 are performed in the KX address buffer 5. X decoder 6, and Y address buffer 11.
Although this is done via the Y decoder 12, the explanation here will be omitted and only the harness bit group 8 will be described.

First, in the write operation, the data input/output terminal l10
When -V write data is input from 1 to I/On, the output of the input data control circuit 9 is input to the input data parity generation circuit 10, and parity data is generated.

The parity data is assigned to the parity bit group 8 via the sense switch circuit 13.

In addition, in the 1g readout operation, read data from the regular bit group 7 and the parity bit group 8 is input to the output data parity detection circuit 15 via the sense switch circuit 13 and the output data control circuit 14. This output data parity detection circuit 15 compares the parity generated from the regular output data with the data read from the parity bit, and outputs information on whether they match or do not match to the error terminal. Ru.

In this way, in addition to the regular bit group 7, the parity bit group 8
Providing this is nothing but a guarantee that the cell cleanup information of the normal bit group 7 destroyed by alpha rays etc. will not be erroneously transmitted to the outside. Therefore, the memory cells in parity bit group 8 are required to have higher reliability than the memory cells in regular bit group 7.
The tube-shaped static memory cell has a large cell size and has sufficient resistance to soft errors such as alpha rays. Therefore, the regular bit group 8 and the parity bit group 7 are composed of memory cells of the same size and shape.

[Problems to be Solved by the Invention] However, as the capacity of semiconductor memory devices increases, the memory cell capacity decreases, and the soft error resistance of the normal bit group 7 and the parity bit group 8 is no longer sufficient. This will be explained in more detail.

FIG. 3 is a circuit diagram of a conventional 7-rip type static memory cell, and FIG. 4 is a plan pattern diagram of a conventional static memory cell.

As shown in FIG. 3, this static memory cell circuit consists of four MOS transistors T1 to T4 and two load resistors R1 and R2, DL is a digit line, and W is a digit line.
L represents a word line. ~Also, as shown in Figure 4,
In the pattern of the static memory cell, the load resistance (几1゜几2) is completely omitted for the sake of simplicity, and the diffusion layer 1 forming the drain/source and the polycrystalline silicon layer 2 forming the gate) 1 are shown.
and contacts 3 which serve as connection points for these. The ff information of this static memory cell is determined. Here, when α rays that cause the above-mentioned soft errors are injected into the static memory cell, electrons or holes are generated within the substrate, and these charges are absorbed by the node N1 or N2.

These generated charges are transferred to nodes N1 and N2 of the memory cell.
This will disturb the potential of In other words, if the amount of charge stored in the capacitors of the nodes N1 and N2 of the memory cell is larger than the amount of charge generated by the α rays and flowing into the nodes N1 and N2 of the memory cell, the information of the memory cell is is not destroyed. However, if the node Nl of the meli cell
If the capacitance of ' and N2 is not sufficient, more charge will flow into the φα particles than the charge held in the capacitance, and the memory cell information will be destroyed. In particular, the destruction of memory information of a group of parity bits is a fatal drawback for semiconductor storage devices.

An object of the present invention is to provide a semiconductor memory device that improves reliability by making soft error resistance in a parity bit group higher than that in a regular bit group.

[Means for solving problems]

In the semiconductor memory device of the present invention, a normal bit group and a parity bit group are formed using flip-flop type static memory cells, and a diffusion region of a memory cell capacity of the parity bit group is a diffusion region of a memory cell capacity of the normal bit group. It is configured to be larger than the diffusion area.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

In FIG. 1, a polycrystalline silicon layer 2 and a polycrystalline silicon layer 2 constituting a word line (WL) are used to explain an embodiment of the present invention. 'rl,'r4''
6 form. Note that 3 is a contact that serves as a connection point between the diffused RIJ1 and the polycrystalline silicon layer 2, and Nl, N2
is the node Nl in FIG.

It is a node similar to N2, and VS2 shown by a dotted line indicates that it is connected to the ground potential.

In this embodiment, the areas of the nodes Nl and N2 are formed larger than those of the nodes Nl and N2 shown in FIG. 4 to increase the memory cell capacity. In this way, by increasing the memory cell capacity, the parity bit group, which requires high reliability, can have a larger memory cell capacity than the regular bit group, and it is possible to obtain sufficient noise resistance.

〔Effect of the invention〕

As explained above, in the semiconductor memory device of the present invention, by making the memory cell capacity of the parity bit group larger than that of the regular bit group, the parity bit group has higher resistance to soft errors than the regular bit group, and is even more reliable. It has the effect of increasing sex.

[Brief explanation of the drawing]

FIG. 1 is a planar pattern diagram of a static memory cell for explaining one embodiment of the present invention, and the gz diagram is a semiconductor memory device having a regular bit group and a parity bit group configured using conventional static memory cells. Figure 3 is a circuit diagram of a conventional 7-lip-flop static memory cell. FIG. 4 is a plan pattern diagram of a static memory cell for explaining a conventional example. 1...Diffusion layer, 2...Polycrystalline silicon layer, 3...-Contact, Nl, N2...
- Node that connects the load element and MOS transistor. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] A semiconductor characterized in that a regular bit group and a parity bit group are formed using flip-flop type static memory cells, and the memory cell capacity of the parity bit group is made larger than the memory cell capacity of the regular bit group. Storage device.