JPH011040A - Microcomputer with built-in test circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] A microcomputer with a built-in test circuit according to the present invention has external terminals f and 1. +2 A read-only memory circuit is provided with a control circuit that performs an interpolation process on the data, and is equipped with a function to perform an independent operation test of the microcomputer based on test command data input from the outside. It is said that

This results in high Jl fffi of the microcomputer.
There is no report that the number of test circuits will increase due to the development of new technologies, and the M moat is to carry out independent operation tests based on the data inputted from the outside one after another. For this reason, "TfI" refers to reducing the size of microcomputer test circuits and reducing production costs.

[Industrial application field]

Unissued II relates to a microcomputer with a built-in test circuit, and more specifically relates to a structure related to a self-sustaining operation test of a microcomputer.

[Conventional technology]

FIG. 4 is a diagram 1jl1 of a conventional example.

The circuit includes 14 central processing circuits 2. Instruction content f-data read-only memory circuit (ROM) 3, instruction data read-only memory circuit (ROM) for testing 4. A microcomputer with a built-in test circuit is shown, which is composed of a memory circuit (RAM) 5 for reading and reading data at any time.

By the way, the test data essential for the self-sustaining operation test of the microcomputer is stored in ROM4.

[Problems that Kan II attempts to solve]

By the way, according to the conventional example, a dedicated ROM 4 is provided for testing the self-sustaining operation of the microcomputer. For this reason, as microcomputers become more sophisticated,
Contents of ROM4 for testing in the conductor chip 1. This will force an increase in the area occupied.

In addition, if there is a change in the operation test of a semiconductor chip that has been commercialized, the existing ROM cannot handle it, so it may be necessary to change the mask for all four chips or Due to the accompanying increase in the number of 5J manufacturing processes, there is a problem in that the production cost of microcomputers increases by one.

The present invention has been created in view of such conventional problems, and aims to make self-operation testing of microcomputers with increasingly high aa performance opportunistic and economical. The purpose is to provide microcomputers.

[R stage to solve the problem]

The principle of the microcomputer with a built-in test circuit according to the present invention is shown in FIG. The input read-only storage circuit 13, the control circuit 14 that controls the input processing of the instruction data 16 for the test, and the external terminal 15 for inputting the instruction data 16 for the test are set to 1 and the test is input from the outside. It is characterized by having a machine that tests the operation of the microcomputer based on the instruction data for the microcomputer.

[Effect]

According to the unissued II+, the instruction data 16 for testing can be input from the outside, so the instruction data 16 for testing is read out via the 1 circuit 14 and the storage circuit 13 for +7.
From time to time, it is Ii billion to leave it to I;

As a result, the 111th order test instruction data 16 is
As a result, it becomes possible to perform operational tests on a microcomputer with a high aperture without increasing or destroying the number of test circuits.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

2 and 3 are diagrams illustrating a microcomputer with a built-in test circuit according to an embodiment of the present invention.

214(a) is a diagram showing a first embodiment of the present invention, in which a central processing circuit (CPU) 12 and 1. ! ; Read-only memory circuit (RAM) 13 and test instruction data 1
6, a control circuit 14 for controlling the connection, and an external terminal 'f-
(port) 15 and an instruction data read-only memory circuit (R
OM) 17 shows a microcomputer with a built-in test circuit.

Note that test command data 16 necessary for a single operation test of the microcomputer is input from the external terminal (-15).

Next, FIG. 2(b) is a block diagram of a microcomputer with a built-in test circuit, which is a further embodiment of FIG. 2(a).

The configuration includes a central processing circuit (CPU) 22 in the semiconductor chip 21, a RAM 23, and a control means 241. Select L stage 242 and RAM 23 AT't- for selecting whether to send data from the external/test input terminal 'f-252 to the CPU 22 or to the RAM 23.
A control circuit consisting of a one-stage counter 243, a data input terminal Y-, and an input terminal r of the test instruction data 26.
a select terminal 251 for selecting and a data input terminal r-
and the input terminal f- of the test command data 26.
-28 and an A/D converter 29 are provided.

Next, to explain the operation, first set the input code (not shown) of the test command data 26 necessary for the self-sustaining operation test, select the select terminal 251, and select the external/test input terminal/
' Enter in 252. Note that when the select terminal 1'-251 is operated, a signal indicating that the test command data 26 is to be input is sent to the control circuit 24 and the CPU 22, and is sent to the RAM.
23 prepares the instruction data 26 for testing. Further, the first select stage 242 of the control circuit 24 changes the external input data mode from the CPU 22 to the RAM 23, and selects test instruction data or external input data 26. In addition, when not testing, select "Row 242 is CPU
22 to send external input data l1-i.

Next, test t9') data 26 is +ir primary RA
Processing is performed in M23. Note that the control-1 circuit 24 is
The 12-input processing of the RAM 23 and the counter 243 that counts the address of the RAM 23; tj control r stage 24
Control by 1 -1. Further, the counter 243 transmits the count amplifier to the CPU 22, and ends the preemption processing.

In this way, the test ri instruction data 26 inputted from the outside can be used without increasing the number of test circuits.
PU22, RAM23, RAM27, timer,
The functions of the microcomputer itself, which consists of A/D converters, etc., are used to perform operation tests on each unit, from input calculation of obtained data to output, etc.
It becomes a moat.

FIG. 3 is a diagram illustrating a microcomputer with a built-in test circuit according to a second embodiment.

Theory 1 in the first embodiment (Figure 2)! ■Those with the same numbers indicate the same a moat, so I will omit the explanation)
/: 1 for the test command data 16 that is not stored in the ROM 17 and is necessary for the operation test! ; Read-out storage circuit 1
This embodiment differs from the first embodiment in that the central processing circuit 12 also serves as the control circuit 14 that performs the filling process.

This allows the central processing function to use test instruction data 16.
However, the test circuit occupied in the semiconductor chip should be made as small as possible, and the microcomputer's self-control function based on the test command data 16 input from the outside should be added. It is possible to perform an operation test.”
r fE.

〔Effect of the invention〕

As explained above, according to the invention, command data for the test is inputted from the outside, and the cliff 1st order 1. 1.Be able to test the operation of a microcomputer on a white machine.

Therefore, it is possible to solve the problem of an increase in the number of tests 1 and 11 due to the high a moat of the microcomputer, and it is also possible to suppress an increase in production costs.

4. Figure 1 is a diagram explaining the principle of the microcomputer with a built-in test circuit of the present invention 11, Figure 2 is a diagram illustrating the principle of the microcomputer with a built-in test circuit according to the first embodiment, Figure 3 is a diagram explaining the principle of the microcomputer with a built-in test circuit, and Figure 3 is a diagram explaining the principle of the microcomputer with a built-in test circuit of the present invention. The first one to emit! Theory 1 regarding the example of J'S2! $114゜Figure 4 is an 11th diagram of a conventional example.

(Explanation of symbols) 1.11...Par; conductor chip, 2.12...CPU (central processing circuit), 3...
ROM (test content data storage circuit), 4.17.27
...ROM (test instruction data storage circuit).

5.1: 3.23...RAM (anytime 11: Reading/reading storage circuit), 15.25...External terminal - f-2 251...-Select terminal, 252... External/test input terminal- L, 16.26...Test instruction data or external input data, 24...Control circuit, 241...Control 1 stage.

242...Selector, 243...Counter, 28...timer, 29...A/D controller 8-.

Claims (2)

[Claims] (1) A central processing circuit (12) that processes data;
An occasional write/read storage circuit (13) and a control circuit (14) that controls the writing process of test instruction data (16).
) and an external terminal (15) for inputting test instruction data (16), and has the function of performing an independent operation test of the microcomputer based on the test instruction data (16) input from the outside. A microcomputer with a built-in test circuit. (2) The central processing circuit (12) is connected to the control circuit (14).
2. The microcomputer with a built-in test circuit according to claim 1, which also functions as a control processing function.