JPH01105222U

JPH01105222U -

Info

Publication number: JPH01105222U
Application number: JP81888U
Authority: JP
Priority date: 1988-01-07
Filing date: 1988-01-07
Publication date: 1989-07-14

Description

[Brief explanation of the drawing]

第１図は本考案の実施例を示すフリツプフロツ
プ回路の回路図、第２図は従来のフリツプフロツ
プ回路の回路図、第３図は第２図の回路の動作を
示すタイミングチヤート、及び第４図は第１図の
回路の動作を示すタイミングチヤートである。Ｄ，……データ入力、逆相データ入力端子、
ＣＬ，……クロツク入力、逆相クロツク入力
端子、Ｑ，……回路出力、逆相回路出力端子、
ＦＦ１，ＦＦ２……第１、第２の同期形フリツプ
フロツプ、ＳＥＬ……セレクタ、Ｄ１，Ｄ２，Ｄ
Ｓ１，ＤＳ２……入力端子、１，２，１
，２……逆相入力端子、Ｃ１，Ｃ２，ＣＳ…
…クロツク端子、１，２，……逆相クロ
ツク端子、Ｑ１，Ｑ２，ＱＳ……出力端子、１
，２，……逆相出力端子。 FIG. 1 is a circuit diagram of a flip-flop circuit showing an embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional flip-flop circuit, FIG. 3 is a timing chart showing the operation of the circuit of FIG. 2, and FIG. 2 is a timing chart showing the operation of the circuit of FIG. 1. FIG. D, ...data input, reverse phase data input terminal,
CL, ... clock input, negative phase clock input terminal, Q, ... circuit output, negative phase circuit output terminal,
FF1, FF2...first and second synchronous flip-flops, SEL...selector, D1, D2, D
S1, DS2...Input terminal, 1, 2, 1
, 2...Reverse phase input terminal, C1, C2, CS...
...Clock terminal, 1, 2, ...Negative phase clock terminal, Q1, Q2, QS ...Output terminal, 1
, 2, ... reverse phase output terminal.

Claims

[Claims for Utility Model Registration] A data input terminal to which a data signal is input, a clock input terminal and a reverse phase clock input terminal to which a clock signal is input, and first and second terminals each having an input terminal, a clock terminal, and an output terminal. a synchronous flip-flop; a selector having first and second input terminals, a clock terminal, an anti-phase clock terminal, and an output terminal; the data input terminal and the input terminals of the first and second synchronous flip-flops; The clock input terminal is connected to the clock terminal of the first synchronous flip-flop and the negative phase clock terminal of the selector, respectively, and the negative phase clock input terminal and the clock terminal of the second synchronous flip-flop are connected to each other. A clock terminal and a clock terminal of the selector are connected, an output terminal of the first synchronous flip-flop and a first input terminal of the selector are connected, and an output terminal of the second synchronous flip-flop and the selector are connected. 2. A flip-flop circuit, wherein a circuit is configured by connecting a second input terminal of a selector to a second input terminal of the selector, and an output terminal of the selector is used as an output terminal of the circuit.