JPS6286740U - - Google Patents
Info
- Publication number
- JPS6286740U JPS6286740U JP17849485U JP17849485U JPS6286740U JP S6286740 U JPS6286740 U JP S6286740U JP 17849485 U JP17849485 U JP 17849485U JP 17849485 U JP17849485 U JP 17849485U JP S6286740 U JPS6286740 U JP S6286740U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- frequency
- exclusive
- clock signal
- flop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Manipulation Of Pulses (AREA)
Description
第１図は本考案の一実施例のデイジタル可変周
波数回路の構成を示す回路図、第２図は第１図の
回路の動作を説明するための波形図である。
１……クロツク信号ＣＫの入力端子、２……周
波数選択信号ＳＥＬの入力端子、３……３分周回
路、４，９……２分周回路、５，７……フリツプ
・フロツプ、６，８……排他的論理和回路、１０
……出力端子。
FIG. 1 is a circuit diagram showing the configuration of a digital variable frequency circuit according to an embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining the operation of the circuit shown in FIG. 1...Input terminal for clock signal CK, 2...Input terminal for frequency selection signal SEL, 3...3 frequency divider circuit, 4,9...2 frequency divider circuit, 5,7...flip-flop, 6, 8...exclusive OR circuit, 10
...Output terminal.
Claims (1)
るＮ分周回路と、 前記クロツク信号を２分周する２分周回路と、 周波数選択信号を前記クロツク信号に同期して
保持する第１のフリツプ・フロツプと、 この第１のフリツプ・フロツプの出力と前記ク
ロツク信号との排他的論理和を出力する第１の排
他的論理和回路と、 前記Ｎ分周回路の出力を前記第１の排他的論理
和回路の出力に同期して保持する第２のフリツプ
・フロツプと、 この第２のフリツプ・フロツプの出力と前記２
分周回路との排他的論理和を出力する第２の排他
的論理和回路と、 この第２の排他的論理和回路の出力を２分周す
る２分周回路とを備えたことを特徴とするデイジ
タル可変周波数回路。[Claims for Utility Model Registration] An N frequency divider circuit that frequency divides a clock signal by N (N is an integer of 3 or more); a 2 frequency divider circuit that divides the frequency of the clock signal by 2; and a frequency selection signal that divides the frequency of the clock signal. a first flip-flop that holds the first flip-flop in synchronization with the clock signal; a first exclusive OR circuit that outputs an exclusive OR of the output of the first flip-flop and the clock signal; and the N-divider. a second flip-flop that holds the output of the circuit in synchronization with the output of the first exclusive OR circuit;
The present invention is characterized by comprising a second exclusive OR circuit that outputs an exclusive OR with the frequency divider circuit, and a divide-by-2 circuit that divides the output of the second exclusive OR circuit by two. Digital variable frequency circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17849485U JPH03758Y2 (en) | 1985-11-19 | 1985-11-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17849485U JPH03758Y2 (en) | 1985-11-19 | 1985-11-19 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6286740U true JPS6286740U (en) | 1987-06-03 |
| JPH03758Y2 JPH03758Y2 (en) | 1991-01-11 |
Family
ID=31120676
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17849485U Expired JPH03758Y2 (en) | 1985-11-19 | 1985-11-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03758Y2 (en) |
-
1985
- 1985-11-19 JP JP17849485U patent/JPH03758Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03758Y2 (en) | 1991-01-11 |
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