JPH01105672A - Device for correcting image defect for solid-state image pickup device - Google Patents

Abstract

PURPOSE:To prevent the degradation of picture quality due to over-correction or non-correction by adding a defect correcting signal, which is generated from a defect correcting signal generating means, to the output signal of a solid-state image pickup element and executing defect correction. CONSTITUTION:Color image pickup outputs (SR), (SG) and (SB) of RGB 3 channels, which are obtained in an image pickup part 2 to be composed of three pieces of image sensors 2R, 2G and 2B, are supplied from a preamplifier 7 through a correcting signal adding circuit 8 to a signal processing system 9. Concerning the CCD image sensors 2R, 2G and 2B, a defect test is executed to analyze the position of a detect picture element, the type ot defect and a defect level, etc., in advance and these data are stored to a memory 10 as correcting data. Then, based on the correcting data to be read from the memory 10 to the correcting signal generating circuit 11, a white flaw defect correcting signal (WCP), a black flaw defect correcting signal (BCP), a white shading correcting signal (WSM) or a black shading correcting signal (BSM), etc., are formed with the timing of the output signal if the defect picture element of the CCD image sensors 2R, 2G and 2B.

Description

[Detailed description of the invention] Hereinafter, the present invention will be explained in the following order.

A. Field of industrial application B. Summary of the invention C. Prior art D. Problems to be solved by the invention E. Means for solving the problems F. Effects G. Example 01 Configuration of a video camera to which the present invention is applied (first (Fig. 2) G, CCD image sensor defect test (Fig. 3) 03 memory map (Fig. 4) Specific example of G4 correction signal generation circuit and its peripheral circuit (Fig. 5)
Figure) GS correction operation (Figures 6, 7, and 8) Effects of the invention A Industrial field of application The present invention is applicable to charge coupled devices (CCDs).
Regarding an image defect correction device for a solid-state imaging device that uses signal processing to correct image quality deterioration caused by image pickup output from a defective pixel included in a solid-state imaging device such as a Data regarding the level of defective components contained in the output signal is read from the storage means, a defect correction signal is formed at the timing of the output signal of the defective pixel among the output signals of the solid-state image sensor, and the defect correction signal is output from the solid-state image sensor. The present invention relates to an image defect correction device for a solid-state imaging device that performs defect correction by adding to a signal.

B. Summary of the Invention The present invention provides a charge coupled device (CCD).
The data about the position of a defective pixel included in a solid-state image sensor such as ``upledDevice'' and the defect component level included in its output signal is read out from the storage means, and the data about the output signal of the defective pixel among the output signals of the solid-state image sensor is In an image defect correction device for a solid-state imaging device that performs defect correction by forming a defect correction signal at a timing and adding it to the output signal of the solid-state imaging device, a reference signal level that is varied according to imaging conditions and the above-mentioned defect correction are provided. By comparing the signal level of the defect correction signal generated from the signal generating means and extracting the defect correction signal with a signal level higher than the reference signal level and performing defect correction processing, image quality due to over-correction or under-correction can be improved. This prevents deterioration and makes it possible to obtain a good image pickup output signal of one image quality.

C. Conventional technology In general, in solid-state imaging devices made of semiconductors such as COD, defective pixels are always added to the imaging output according to the amount of incident light due to local crystal defects in the semiconductor. It is known that there is a deterioration in image quality due to the image output from the defective pixel. An image defect in which a constant bias voltage is always added to the image pickup output is called a white spot defect because it appears as a high-intensity spot on a monitor screen when this image defect signal is processed as is.

Conventionally, in order to correct image quality deterioration caused by image pickup output from defective pixels included in the above-mentioned solid-state image sensor by signal processing, for example, information indicating the presence or absence of a defect in each pixel of the above-mentioned solid-state image sensor is stored in memory. Based on the information in the memory, a signal interpolated with the image output obtained from the pixel adjacent to the defective pixel is used instead of the image output from the defective pixel. Note that in order to store information indicating the presence or absence of defects for each pixel of the solid-state image sensor in the memory in this way, it is necessary to use a memory with a huge storage capacity equivalent to the total number of pixels of the solid-state image sensor. Instead of sequentially storing the presence or absence of a defect for each pixel, the applicant encodes the distance between defective pixels and stores it in the memory as data indicating the position of the defective pixel included in the solid-state image sensor. He was the first to propose a technology to reduce storage capacity (Special Publication No. 60-34872).
(see publication).

Conventionally, in the correction process using interpolation, a large correction error occurs if there is no correlation between the imaging outputs obtained from pixels in the vicinity of the defective pixel. Data regarding the level of defective components included in the output signal is stored in a memory, and based on the data read from the memory, a defect correction signal is generated at the timing of the output signal of the defective pixel among the output signals of the solid-state image sensor. An image defect correction device for a solid-state imaging device has also been proposed in which defect correction is performed by forming and adding it to the output signal of the solid-state imaging device (see Japanese Patent Laid-Open No. 60-513780).

D. Problem to be Solved by the Invention Incidentally, in a solid-state image sensor formed of a semiconductor, the signal level due to false signal charges caused by dark current is large, and the image defect due to the white defective pixel appears relatively prominently. However, at room temperature, the defects are extremely small and do not pose a problem, and as the temperature increases, they increase exponentially.

In this way, in order to correct temperature-dependent white spot defects, it is necessary to further perform temperature correction processing on the correction signal. If there is an error, there is a problem that over-correction or under-correction occurs in the white flaw defect correction using the white flaw defect correction signal, and so-called corrected flaws remain in the image pickup output after the defect correction process.

Therefore, in view of the above-mentioned problems, the present invention does not apply correction processing to defects with a small defect level where correction scratches become a problem, and selectively performs correction processing only on defects with large defect levels. Provided is an image defect correction device for a solid-state imaging device having a novel configuration, which performs correction processing on the image to prevent image quality deterioration due to over-correction or non-correction, and obtains a non-life insurance output signal with good image quality. It is something to do.

Means for Solving the Problems The present invention solves the conventional problems as described above.
A storage means that stores data regarding the position of a defective pixel included in the solid-state image sensor and the level of defective components contained in the output signal thereof; and a defect correction signal generating means for generating a defect correction signal at the timing of the output signal of the defective pixel, the defect correction signal being generated by the defect correction signal generating means being added to the output signal of the solid-state image sensor to correct the defect. In the image defect correction apparatus for a solid-state imaging device, a comparison means is provided for comparing a reference signal level that is varied depending on imaging conditions and a signal level of a defect correction signal generated from the defect correction signal generation means, *ta indicates that a defect correction signal having a signal level higher than the reference signal level is extracted and defect correction processing is performed based on the output of the comparison means.

F Function: In the image defect correction device for a solid-state imaging device according to the present invention, the output of the comparison means for comparing the signal level of the defect correction signal generated from the defect correction signal generation means with the reference signal level that is varied according to the imaging conditions. Based on this, by extracting a defect correction signal with a signal level higher than the reference signal level and performing defect correction processing, correction processing is performed for defects with small defect levels where correction scratches become a problem. To selectively perform correction processing only on flaws and defects with large defect levels.

G. Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

GI video camera configuration In the embodiment shown in the block diagram of FIG. 1, an image of a subject is captured by color-separating the imaging light into the three primary color components of red (R), green (G), and blue (B) using the imaging optical system 1. The present invention is applied to a color video camera that captures a color image using a three-panel type imaging section 2 configured with three solid-state image sensors that form an image on a surface.

In this embodiment, as shown in FIG. 2, the solid-state image sensor constituting the imaging section 2 includes a large number of light receiving sections S arranged in a matrix, each corresponding to a pixel, and each of the light receiving sections S, as shown in FIG. It consists of a vertical transfer register section VR provided along the vertical direction on one side of the section S, and a horizontal transfer register section HR provided at each end side of each vertical transfer register section VR, and is obtained in each light receiving section S. A signal charge corresponding to the amount of received light is transferred to each vertical transfer register section VR corresponding to each vertical line every field period or every frame period, and the signal charge is transferred through each vertical transfer register section VR. Three interline transfer type CCD image sensors 2R, 2G which transfer signal charges to a horizontal transfer register HR and extract signal charges for each horizontal line from the horizontal transfer register HR as imaging outputs.
, 2B are used.

The driving circuit 3 of the above-mentioned imaging/imaging section 2 is supplied with vertical transfer pulses φV and horizontal transfer pulses φ synchronized with the synchronization signal 5YNC given by the sync generator 4 shown in FIG. 1 from the timing generator 5. At the same time, each light receiving section S of the COD image sensor 2R, 2G, 2B
A readout mode that specifies a field readout mode in which all signal charges corresponding to the amount of light received by the light receiving section S are read out in one field period, and a frame readout mode in which all signal charges obtained in each light receiving section S are read out in one frame period. Mode designation signal and the above COD image sensor 2R, 2G
, 2B, and a shutter control signal that controls the speed of a so-called electronic shutter is supplied from the system controller 6.

Here, the CCD image sensors 2R, 2G, and 2B constituting the imaging section 2 have a charge accumulation time of 1/30 seconds, whereas the frame readout mode has a charge accumulation time of 1/30 seconds.
In the /60 second field readout mode, the charge accumulation amount is 1/2 of the above frame readout mode, so by adding and reading out the signal charges obtained by two vertically adjacent light receiving sections S, the above The sensitivity is the same as the frame readout mode.

The above three CCD image sensors 2R and 2G.

RGB 3-channel color imaging output (SR), (SO), (
Sl) is supplied from the preamplifier 7 to the signal processing system 9 via the correction signal addition circuit 8, and after being subjected to defect correction processing in the correction signal addition circuit 8, the signal processing system 9 performs gamma correction. Along with correction and shading correction, processing is applied to CCIR (Consultative Committee on International Radio Communications) and E
It is converted into a video signal (soot) that conforms to a predetermined standard television system standardized by the IA (Electronic Industries Association) and output.

In addition, in this embodiment, the above COD image sensor 2R
, 2G, and 2B, a defect test was conducted in advance to analyze the position of the defective pixel, the type of defect, the level of the defect, etc.
These data are stored in the memory IO as correction data, and the timing of the output signal of the defective pixel of the COD image sensor 2R, 20, 2B is determined based on the correction data read out from the memory 10 by the correction signal generation circuit 11. A white blemish defect correction signal (TI4CP), a black blemish defect correction signal (BcP), a white shading correction signal (WS-, a black shading correction signal (B□), etc.) are formed, and these correction signals (Wcp), (BCF), 01g,
) and (Bsm) to the correction signal addition circuit 8 and the signal processing system 9 through the correction signal switching circuit 12, the image defects are corrected in the correction signal addition circuit 8 and the signal processing system 9. It is supposed to be done.

Furthermore, the imaging section 2 is provided with a temperature sensor 13, and the COD image sensors 2R, 2G.

2B temperature is detected and each correction signal (Wc
r) and (Bsv) are subjected to temperature correction processing by temperature correction circuits 14 and 15, respectively, based on the detection output from the temperature sensor 12. Furthermore, the temperatures of the COD image sensors 2R, 2G, and 2B indicated by the detection output from the temperature sensor 13 are analog/digital (
The data is digitized by an A/D converter 16 and supplied to the memory 10 as address data.

G. Defect Test for COD Image Sensors Defect tests for the COD image sensors 2R, 2G, and 2B are performed at a test temperature higher than normal temperature at which image defects are likely to appear. In the defect test, for example, as shown in FIG. 3, the COD image sensors 2R, 2G, 2B
Each position Ar, Az of white defective pixel, black defective pixel, etc.
..., and determine the type and level of the defect i1
゜it ... is detected, and the position data of each defective pixel is obtained as follows. That is,
The first defective pixel position A counting from the reference point A0 is expressed by encoding the distance l1lIdl from the reference point A0 and using predetermined bits of digital data, and other defective pixel positions A
, (n is any integer) is the previous defective pixel position Al
1-, the distance d from 1- to , Az is the dummy defective pixel position AH41 between
If the relative distance from any defective pixel to the next defective pixel is too large to be represented by the digital data of the predetermined bits, a dummy defective pixel is set between the defective pixels. , the above relative distance d is changed from the first defective pixel position lA1 to the dummy defective pixel position ADII+
and the distance d from the dummy defective pixel position AIIMI to the second defective pixel position A, respectively, and each is represented by digital data of the predetermined bits.

Here, the above-mentioned CCD image sensors 2R and 2G.

If the position A+, Az, etc. of the defective pixel of 2B is expressed as a two-dimensional absolute address, for example, a total of 20 bits of address data, 10 bits in the horizontal direction and 10 bits in the vertical direction, is required. Defective pixel position A, (
n is any integer) is the previous defective pixel position A7-1
By encoding each of the distances Md from and using relative addresses represented by digital data of predetermined bits, address data can be compressed to the number of bits necessary to represent the maximum value of the relative address, For example, 12-bit relative address data is compressed into 8-bit data for the position of one defective pixel. Furthermore, assuming that the maximum relative distance that can be represented by 12-bit relative address data is, for example, 4.5 lines, the relative distance d7 from one defective pixel position A7 to the next defective pixel position A, l is 4.5 lines. If the distance is greater than or equal to the relative distance d
, by setting one or more dummy defective pixel positions AD between the defective pixel positions A@+A++++ so that the number of lines is within 4.5 lines.
Defective pixel position Aゎ based on bit relative address data.

1 can be represented. In this way, if the relative distance d7 from any defective pixel position A7 to the next defective pixel position A p (+1) is too large to be represented by the digital data of the predetermined bits, the distance between the defective pixels is By setting a dummy defective pixel and dividing the relative path @d, all defective pixel positions can be represented by predetermined bits of digital data. Note that the dummy defective pixel position A□ 1 can be set within the blanking period BLK of the imaging output signals read from the CCD image sensors 2R, 2G, and 2B, so that the quality of the imaging output signals will not be adversely affected.

G-Core Memory Map In this embodiment, the memory 9 is divided into a field readout area ARFD from address 0 to address 4095 and a frame readout area ARFM from address 4096 to address 8191, as shown in the memory map of FIG. Furthermore, the readout areas ARFD and ARFM are respectively set to the minimum correction amplitude data area AR5A, correction data area ARCM, and shutter speed data area AR3S.
It is divided into and used.

In the minimum correction amplitude data area AR3A, the CCD
For the imaging output of image sensors 2R, 2G, and 2B,
N pieces of minimum correction amplitude data (DSA) indicating the minimum correction amplitude to be subjected to correction processing according to imaging conditions such as temperature and shutter speed are written. The above minimum correction amplitude data (DSA) is the minimum correction amplitude data (DSAR) of each RGB channel.

4 bits each are used for (DSAG) and (DSAB), 2 bits are used for cycle time data, and the remaining 2 bits are used for cycle time data.
It consists of 2 bytes of data with unused bits.

Further, correction data (DCM) obtained by performing the above-described defect test on the CCD image sensors 2R, 2G, and 2B is written in the correction data area ARCM. The above correction data (DCM) includes 8-bit amplitude data (DCMA) corresponding to the defect level, 2-bit mode select data (DMS) indicating the type of defect, and 2-bit color code data (DMS) indicating the correction channel.
CC) and 12-bit relative address data (RADR) indicating the distance to the next defective pixel position. This correction data (DCM)
includes the correction data for the dummy defective pixels mentioned above (
DCM') is also included.

Further, the shutter speed data area AR5S contains shutter data (SOD) for converting 4-bit shutter speed data indicating the set shutter speed of the electronic shutter into 3-bit data, and the correction data area AR5S.
Fifteen pieces of 2-byte data consisting of 12-bit first address data (PADR) indicating the CM start address, ie, address 2N, are written.

Specific example of the G4 correction signal generation circuit and its peripheral circuits In this embodiment, the correction signal generation circuit 11 and its peripheral circuits, as shown in FIG. is supplied7
latch circuits 21゜22.23.24, 25.26.
27 and a strobe generating circuit 2B.
゛When performing an imaging operation in the operation mode set in the system controller 6, the correction signal generation circuit 11 performs an initial setting operation during the blanking period for each field or frame, and sends the correction signal to the system controller 6. Each RGB channel is read out from the minimum correction amplitude data area AR3A of the memory 10 according to the imaging operating conditions such as the set shutter speed and the temperature data provided from the temperature sensor 13 via the A/D converter 16. Minimum corrected amplitude data (DSAR), (
DSAG) and (DSAB) are latched into the first to third latch circuits 21゜22.23, and the shutter data (SHD) read from the shutter speed data area AR3S of the memory IO is latched into the fourth latch circuit 24. The strobe generating circuit
8 causes the address counter 40 to read the correction data (DCM) r from the beginning of the correction data area ARCM of the memory 10, that is, address 2N, and generates relative address data indicating the distance from the origin A0 to the first defective pixel position AI. (RADR) is latched in the strobe generation circuit 28, and its amplitude data (DCMA), color code data (DCC) and mode select data (DN
S) is latched in the fifth to seventh latch circuits 25, 26, and 27.

Then, when the strobe pulse generation circuit 28 finishes the initial setting operation and enters the correction operation state, the relative address data (RADR) latched in the initial setting operation is
), a strobe pulse is output at the timing of the first defective pixel position A, and the address counter 40
is incremented, the next correction data (DCM) * is read out from the correction data area ARCM of the memory 10, and relative address data indicating the distance to the next defective pixel position A is latched into the strobe generation circuit 28. , the amplitude data (MCMA), color code data (DCC), and mode select data (DNS) are latched in the fifth to seventh latch circuits 25, 26, and 27, and a strobe pulse is generated at the timing of each defective pixel position AM. Performs an operation to output sequentially.

The first to third latch circuits 21, 22゜23 are as follows:
The minimum correction amplitude data (DSAR), (DSAG), (DSAB) of each RGB channel read from the minimum correction amplitude data area AR3A of the memory 10 is latched, and the minimum correction amplitude data (DSAR),
(DSAG).

(DSAB) to the comparator 30 via the selector 29.
supply to.

Further, the fourth latch circuit 24 is connected to the memo +710.
The shutter data (SHD) read from the shutter speed data area AR3S is latched, and the shutter data (SHD) is supplied to the bit shift circuit 31 as control data.

Furthermore 1. The fifth to seventh latch circuits 25°26
．． 27 is designed to latch amplitude data (DCMA), color code data (DCC), and mode select data (DNS) of the correction data (DCM) read from the correction data area ARCM of the memory 10.

The amplitude data (DCM^) latched by the fifth latch circuit 25 is supplied to the comparator 30 as well as directly and via the bit shift circuit 31 to the first switch circuit 32. The signal is supplied from the first switch circuit 32 to a digital-to-analog (D/A) converter 33 . The color code data (DCC) latched by the sixth latch circuit 26 is supplied to the selector 29 as control data, and is also supplied as control data to a first decoder 43, which will be described later.

Further, the mode select data (DNS) latched by the seventh latch circuit 27 is supplied to the first switch circuit 32 as control data, and is also supplied to a second switch circuit 41 and a second decoder, which will be described later. 47 as control data.

The selector 29 selects the minimum corrected amplitude data ([1SAR) of each RGB channel latched in the first to third latch circuits 21, 22, and 23.

For (DSAG) and (DSAB), select the minimum amplitude correction data (DSA) of one of the RGB channels specified by the color code data (DCC) supplied as control data from the sixth latch circuit 26. and is supplied to the comparator 30. The comparator 30 compares the minimum correction amplitude data (DSA) selected by the selector 29 with the amplitude data (DCMA) latched in the fifth latch circuit 25,
The third switch circuit 4 uses the comparison output as control data.
2, and when the amplitude data (DCMA) is larger than the minimum corrected amplitude data (DSA), the third switch circuit 42 is closed.

Further, the bit shift circuit 31 performs the following operations on the amplitude data (DCMA) supplied from the fifth latch circuit 25 in accordance with the shutter data (SHD) supplied as control data from the fourth latch circuit 24. For example, bit shift processing as shown in Table 1 is performed, and the bit-shifted amplitude data (DCMA) is supplied to the D/A converter 34 via the first switch circuit 32.

[Margin below]

l: Bit shift The first switch circuit 32 uses the mode select data (DNS) supplied from the seventh latch circuit 27 as control data, and uses the mode select data (D?I) as control data.
Control is performed so that the bit shift circuit 31 is selected when S) indicates a white spot defect mode, and the fifth latch circuit 25 is selected when S) indicates a white spot defect mode.

The D/A converter 33 converts the amplitude data (DCMA) supplied via the first switch circuit 32 into analog data. The analog amplitude signal obtained by the D/A converter 33 is transmitted to the first and second level adjustment circuits 3
4.35 and to the first and second temperature compensation circuits 14.15, which circuits 34.15.
35.14°15 to first to fourth signal switching circuit 3
6, 37, 38, and 39 as various amplitude correction signals.

Further, the strobe generation circuit 28 is connected to the memory 10.
Based on the relative address data (RADR) of the first address data (FADR) read from the shutter speed data fi1mARSS of Each CCD image sensor 2R forming part 2.

Each defective pixel position of 2G and 2B A + , A t ・
A strobe pulse is generated at a timing corresponding to ..., and this strobe pulse is supplied directly from the second switch circuit 41 and via the third switch 42 to the first decoder 43, and at the same time, the first address data and the Relative address data is preset in the address counter 40 of the memory IO.

The second switch circuit 41 is connected to the seventh latch circuit 2.
Mode select data (DIllS) supplied from 7
is the control data, and the above mode select data (DM
S) is controlled to select the third switch circuit 42 when it indicates the white flaw defect mode, and to select the first decoder 43 when it is in another defect mode. A strobe pulse of 1. is supplied to the first decoder 43 via the third switch circuit 42; Strobe pulses of other defective modes are directly supplied to the first decoder 43. Further, the third switch circuit 4
2, the fifth latch circuit 25 is controlled to open and close using the output of the comparator 30 as control data.
The amplitude data (DCM^) latched in is the minimum corrected amplitude data (DSA) selected by the selector 29.
The second switch circuit 41
A strobe pulse in the white spot defect mode is supplied to the first decoder 43 via the strobe pulse.

The first decoder 43 is connected to the sixth latch circuit 26.
2-bit color code data (DCC) supplied as control data from the D-type flip-flops 44, 45, 46 of any RGB channel or all channels selected as shown in Table 2. The strobe pulse is supplied to the second decoder 47.

Margin below C] 2: Car code - The above-mentioned flip-flops 44, 45, and 46 generate clock pulses that match the phases of each color component of the imaging output obtained by the above-mentioned COD image sensors 2R, 2G, and 2B, that is, each RGB channel. (φ,), (φ.), (φ,)
is supplied from the timing generator 5 to each clock input terminal, and regarding the strobe pulse supplied from the first decoder 43, the clock pulse (
φi, (φ.).

(φ proverb).

Here, the CCD image sensor 2 for imaging the edge (G)
G to 1/ with respect to other COD image sensors 2R and 2B.
When the imaging unit 2 is constructed by employing a spatial pixel shifting method in which pixels are shifted by two pixels, the clock pulses (φl) and (φ.) are used.

Of (φ, ), the clock pulse for G channel (φG
) to the other R, B channel clock pulses (φi, (
This can be handled by setting the phase opposite to φ, ).

The second decoder 47 is connected to the seventh latch circuit 27.
With the 2-bit mode select data (DNS) supplied as control data from the strobe pulse, selection control data corresponding to the correction mode specified as shown in Table 3 is formed from the strobe pulse, and It is applied to each control input terminal of the fourth correction signal switching circuit 36, 37, 38, and 39.

The first to fourth correction signal switching circuits 36.
37, 38, and 39 are each analog output from the D/A converter 33 via the first or second level adjustment circuit 34.35 or the first or second temperature correction circuit 14.15. The amplitude signal is sent to the second decoder 47.
According to the selection control data, the signals are switched as follows and output as various correction signals.

That is, the above mode select data (DNS) is (L
When the white spot defect mode is indicated in L), the third correction signal switching circuit 38 converts the analog amplitude signal outputted from the D/A converter 33 via the first temperature correction circuit 14 into the white spot defect mode. As the defect correction signal (Wcr), RGB shown in the color code data (DCC) above
Selectively output to channels. Further, when the mode select data (DNS) is (LH) indicating the black defect mode, the first correction signal switching circuit 36 switches the D/A converter 33 from the first level adjustment circuit 3.
The analog amplitude signal output through 4 is used as a black defect correction signal (BCP), and the color code data (DC
Selectively output to the RGB channels indicated by (:). Furthermore, the above mode select data (DMS)
When (HL) indicates the black shading mode, the fourth correction signal switching circuit 39 changes the analog amplitude signal output from the D/A converter 33 via the second temperature correction circuit 15. The black shading correction signal (B
□), it is selectively output to the RGB channels indicated by the color code data (DCC). Furthermore, the above mode select data (DNS) is (H)
When the white shading mode is indicated by (), the second correction signal switching circuit 37 is connected to the D/A converter 33.
The analog amplitude signal output from the second level adjustment circuit 35 is converted into a white shading correction signal (lls
, I), it is selectively output to the RGB channels indicated by the color code data (DCC).

Furthermore, in this embodiment, correction data (DCM) is read out from the correction data area ARCM of the memory 10, and various correction signals (Lp) are generated as described above.

When forming (BCF), (Ils, I), and (BsH), as shown in FIG. Read timing of the signal charge, that is, read timing of the above correction data (DCM) (1 m)
The power supplied to the memory 10 is cut off or power save control is performed except for a period (TI) of several 10 clocks before and after the period including the period TI. This prevents unnecessary power consumption by the memory 10 and reduces power consumption.

G, correction operation, and in this embodiment, color imaging output (S*) of each RGB channel obtained by the imaging unit 2;
(se) and (sm) are the first and third correction signal switching circuits 36 and 38 that constitute the correction signal switching circuit 12 for the analog amplitude signal output from the D/A converter 33. At each defective pixel position A + ,
The white flaw defect correction signal (Lp) and black flaw defect correction signal (Bcp) obtained by switching and selecting according to the defect mode at the timing of A t ... are added by the correction signal adding circuit 8. As a result, image defects due to white flaws and black flaws are corrected.

The white spot defect correction signal (Mar) selected by the first correction signal switching circuit 36 is as shown in FIG.
Regarding the amplitude (2w) of the analog amplitude signal output from the /A converter 33, each CO constituting the imaging section 2
By performing temperature correction processing in the first temperature correction circuit 14 to which the detection output from the temperature sensor 13 that detects the temperature of the D image sensors 2R12G and 2B is supplied, the white image can be adjusted at the operating temperature in the actual imaging state. By setting the amplitude (j!@') that optimally corrects the scratch defect and adding it to the imaging output obtained by the imaging section 2 in the correction signal addition circuit 8, the temperature-dependent white scratch defect can be optimally corrected. Can be corrected.

Here, the defect level of the temperature-dependent white flaw defect is extremely small at room temperature and does not pose a problem as a defect, and increases exponentially as the temperature increases, so the white flaw correction signal (Wcp ), if there is a correction error in the first temperature correction circuit 14 etc. that performs temperature correction processing on the temperature correction signal (tact'), over-correction or under-correction may occur in white flaw correction using the white flaw correction signal (tact'), resulting in so-called correction flaws. will remain in the image output after defect correction processing. Therefore,
In this embodiment, data such as shutter speed and operating temperature is used as address data in the above memory by the above-mentioned initial setting operation. The minimum correction amplitude data CD5A') read from the minimum correction amplitude data area AR3A of
．． 22.23 is latched, and the correction amplitude data (DCMA) read from the correction data area ARCM of the memory 1o during the actual lifting operation is smaller than the minimum correction amplitude data (DSA), and white flaw defect correction is performed. By selectively performing correction processing only on white flaws with large defect levels, while not performing correction processing on small white flaw defects where correction flaws would become a problem,
This makes the white spot defect correction processing more effective.

Furthermore, in each of the CCD image sensors 2R, 2G, and 2B constituting the imaging unit 2, when an electronic shutter function is added by controlling the charge accumulation time, the image output is output according to the charge accumulation time, that is, the shutter speed. The signal level of the white defect signal included in the image changes. In this embodiment, the above-mentioned correction signal generation circuit 11
Based on the shutter data latched by the fourth latch circuit 24, the bit shift circuit 31 applies the bit shift processing shown in Table 1 above to the corrected amplitude data (DCMA) during the actual damage operation. By this, the gain of the white spot defect correction signal (KAI) is made to correspond to the set shutter speed, so that optimal white spot defect correction processing can be performed at all times. Note that in order to make the gain of the white spot defect correction signal (KAI) correspond to the set shutter speed, in addition to the bit shift circuit 31, for example, the white spot defect correction can be performed using the shutter speed, that is, the charge accumulation time as a coefficient. A multiplier that performs digital or analog multiplication processing on the signal (Wcp) may be provided.

Furthermore, each CCD image sensor 2R of the imaging section 2,
In 2G and 2B, when an electronic shutter function is added by controlling the charge accumulation time, for example, as shown in Fig. 8, the amount of signal charge obtained by reducing the charge accumulation period to 1/2 in the field read mode can also be reduced. 17 in normal mode
However, in frame readout mode, the effective charge accumulation time is 1/4 of that in normal mode, and even if the same shutter speed is set, the effective charge accumulation time differs depending on the signal charge readout mode. The signal level of the white flaw defect signal included in the imaging output is also different. In this embodiment, the memory 10 has a field readout area A.
RFD and frame readout area ARFM are provided, and minimum correction amplitude data (DSA) in each readout mode,
Write correction data (DCM), shutter data (SHD), etc. in advance, then read the data from the field readout area ARFD or frame readout area ARFM corresponding to the actually set readout mode, and perform the initial setting operation described above. By performing the and correction operations, optimal defect correction processing can be performed in either read mode.

Further, in this embodiment, regarding the image pickup output that has been subjected to the image defect correction processing due to white flaw defects and black flaw defects as described above, the above-mentioned signal processing system 9 includes the A black shading correction signal (B,) obtained by switching and selecting the analog amplitude signal output from the D/A converter 33 in the second and fourth correction signal switching circuits 36 and 38 according to the defect mode. Shading correction processing is performed using white shading correction signals (Ws, I).

The black shading correction signal (B□) selected by the fourth correction signal switching circuit 39 is transmitted to the D/A converter 33.
The second temperature correction circuit 15 to which the detection output from the temperature sensor 13 is supplied performs temperature correction processing on the amplitude of the analog amplitude signal output from the temperature sensor 13. Shading can be corrected to the least amount.

Therefore, in this embodiment, temperature-dependent white flaws and black shading that appear conspicuously due to pixel defects of the CCD image sensors 2R, 2G, and 2B constituting the imaging section 2 are corrected, and the above-mentioned correction is also performed. It also compensates for non-temperature-dependent black scratches and white shading that cannot be removed by using the same method. Furthermore, it does not perform correction processing on small defects where compensation scratches become a problem, but it can be used to correct large defects without performing correction processing. Since the correction process is selectively performed only on scratch defects, it is possible to prevent image quality deterioration due to over-correction or non-correction, and to obtain imaging output with extremely good image quality.

H Effects of the Invention In the image defect correction device for a solid-state imaging device according to the present invention, a comparison means compares a reference signal level that is varied depending on the imaging conditions and a signal level of the defect correction signal generated from the defect correction signal generation means. By extracting a defect correction signal with a signal level higher than the reference signal level and performing defect correction processing based on the output of the Since the correction process is selectively performed only on scratches and defects with large defect levels without performing any correction, deterioration in image quality due to over-correction or non-correction can be prevented, and an image pickup output signal with good image quality can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a video camera to which the present invention is applied, FIG. 2 is a schematic diagram showing the structure of a CCD image sensor constituting the imaging section of the video camera, and FIG. FIG. 4 is a schematic diagram for explaining pixel defects of the CCD image sensor and their imaging output; FIG. 4 is a memory map of a memory that stores data regarding pixel defects of the CCD image sensor; and FIG. FIG. 6 is a block diagram showing the specific configuration of a correction signal generation circuit that reads correction data and forms various correction signals, together with its peripheral circuits. FIG. 7 is a waveform diagram for explaining the defect correction processing operation using the correction signal generated by the correction signal generation circuit, and FIG. 8 is a waveform diagram for explaining the field readout mode and frame of the CCD image sensor. FIG. 7 is a waveform diagram for explaining the relationship between charge accumulation time and charge accumulation amount in read mode. 2... to the most image parts 2R, 2G, 2B... CCD image sensor 3...
CCD drive circuit 4...sync generator 5...timing generator 6...system controller 8...correction signal addition circuit 10...memory 11...correction signal generation circuit 12...correction signal switching circuit

Claims (1)

[Claims] A storage means that stores data regarding the position of a defective pixel included in the solid-state image sensor and the level of defective components contained in the output signal thereof; and a defect correction signal generating means for generating a defect correction signal at the timing of the output signal of the defective pixel, the defect correction signal being generated by the defect correction signal generating means being added to the output signal of the solid-state image sensor to correct the defect. In the image defect correction apparatus for a solid-state imaging device, a comparison means is provided for comparing a reference signal level that is varied depending on imaging conditions and a signal level of a defect correction signal generated from the defect correction signal generation means, An image defect correction device for a solid-state imaging device, characterized in that, based on the output of the comparison means, a defect correction signal having a signal level higher than the reference signal level is extracted and defect correction processing is performed.